From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MaK8w-0007pM-CD for qemu-devel@nongnu.org; Sun, 09 Aug 2009 21:57:46 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MaK8r-0007jj-LN for qemu-devel@nongnu.org; Sun, 09 Aug 2009 21:57:45 -0400 Received: from [199.232.76.173] (port=60783 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MaK8r-0007jG-GH for qemu-devel@nongnu.org; Sun, 09 Aug 2009 21:57:41 -0400 Received: from pop-borzoi.atl.sa.earthlink.net ([207.69.195.70]:38156) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MaK8r-0004OS-1Y for qemu-devel@nongnu.org; Sun, 09 Aug 2009 21:57:41 -0400 Message-ID: <4A7F7E91.5000903@earthlink.net> Date: Sun, 09 Aug 2009 21:57:37 -0400 From: Robert Reif MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] sparc sun4m changes List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Blue Swirl I just took a look at the sun4m interrupt controller and noticed the recent changes. There are at least 3 different interrupt controllers used by sun4m: ss600mp with VME and MBUS specific support, ss 10/20 with MBUS support and ss 4/5/lx with slavio support. This doesn't even address the java stations. intbit_to_level in slavio_intctrl.c needs to be different for each controller chip used. There also needs to be a controller specific interrupt mask used. The NCR slavio chip is only used for single processor systems (ss 4/5/lx). It is a subset of the ss 10/20 which is a subset of the ss600mp. We really should address these differences.