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From: Heiko Schocher <hs@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] 83xx and LCRR setting
Date: Thu, 20 Aug 2009 07:45:19 +0200	[thread overview]
Message-ID: <4A8CE2EF.303@denx.de> (raw)
In-Reply-To: <20090819193128.62f9a4b3.kim.phillips@freescale.com>

Hello Kim,

Kim Phillips wrote:
> On Tue, 18 Aug 2009 15:23:47 +0200
> Heiko Schocher <hs@denx.de> wrote:
> 
>> Hello Kim,
> 
> Hello Heiko, sorry for the late reply,

No problem, thanks for your response!

>> I actually work on an u-boot mpc8321 port (mostly identical with the kmeter1
>> port already in mainline), and I have to set the LCRR (Clock Ratio Register
>> Reference Manual 10.3.1.14). As I see in
>>
>> cpu/mpc83xx/cpu_init.c cpu_init_f()
>>
>> this is done while running from flash. Hmm... the Reference manual
>> says in chapter 10.3.1.14 page 474:
>>
>> NOTE
>> For proper operation of the system, this register setting must not be altered
>> while local bus memories or devices are being accessed. Special care needs
>> to be taken when running instructions from an local bus controller memory.
>>
>> Hmm...
>>
>> On my board (and for example on the MPC832XEMDS) the flash is connected
>> to the localbus ... and this register setting is done, while
>> running from flash ... Hmm.. is this safe?
> 
> yeah, I'm not quite sure how that works myself!

:-(

>> I only can set the LCRR register succesfully on my board port, if
>> I set the LCRR_DBYP bit in the CONFIG_SYS_LCRR define, without it
>> I couldn;t run u-boot (with it, it works fine)
>>
>> Unfortunately this LCRR_DBYP bit (0x80000000) is not documented in
>> the MPC8323ERM ... there, it is just marked as reserved (and set
>> to 1 on reset)
>>
>> So, it is ok, just to set this LCRR_DBYP bit? Or should the LCRR
>> register only changed, if u-boot runs from ram? Or ...?
> 
> I'd say set the bit - my guess it the bit always existed, but it just
> got documented in later parts' docs. E.g, this is from the mpc8315
> documentation:
> 
> 0 PBYP PLL bypass. This bit should be set when using low bus clock frequencies (66 MHz or lower).
>        When in PLL bypass mode, incoming data is captured in the middle of the bus clock cycle.
>        0 The PLL is enabled.
>        1 The PLL is bypassed.

Thanks, I found this bit also in the 8360 Reference Manual.

bye
Heiko
-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

  reply	other threads:[~2009-08-20  5:45 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-08-18 13:23 [U-Boot] 83xx and LCRR setting Heiko Schocher
2009-08-20  0:31 ` Kim Phillips
2009-08-20  5:45   ` Heiko Schocher [this message]
2009-08-20 10:05   ` Heiko Schocher
2009-08-20 11:03     ` Detlev Zundel
2009-08-21 20:56       ` Kim Phillips
2009-08-22  6:32         ` Heiko Schocher
2009-08-24 10:15           ` Detlev Zundel
2009-08-24 16:43             ` Kim Phillips
2009-08-21 20:55     ` Kim Phillips
2009-08-22  6:17       ` Heiko Schocher
2009-08-24 16:32         ` Kim Phillips

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