From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MebnE-0003hd-01 for qemu-devel@nongnu.org; Fri, 21 Aug 2009 17:37:04 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Mebn9-0003hH-6I for qemu-devel@nongnu.org; Fri, 21 Aug 2009 17:37:03 -0400 Received: from [199.232.76.173] (port=35886 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Mebn9-0003hE-1n for qemu-devel@nongnu.org; Fri, 21 Aug 2009 17:36:59 -0400 Received: from mx20.gnu.org ([199.232.41.8]:3260) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Mebn8-0005dq-NW for qemu-devel@nongnu.org; Fri, 21 Aug 2009 17:36:58 -0400 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Mebn7-0007Ag-4K for qemu-devel@nongnu.org; Fri, 21 Aug 2009 17:36:57 -0400 Message-ID: <4A8F136C.4000907@codesourcery.com> Date: Fri, 21 Aug 2009 18:36:44 -0300 From: Daniel Gutson MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------050403060305060008010508" Subject: [Qemu-devel] [PATCH] ARM NEON shift emulation fix List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This is a multi-part message in MIME format. --------------050403060305060008010508 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Hi, the attached patch fixes a bug that caused some NEON shift operations to shift a wrong amount of bytes. The problem was that a variable holding an immediate value representing the amount of bits to shift was later overwritten with another value (used for something different) within a loop. Please commit this for me if approved, since I don't have write access. Thanks! Daniel. --- 2009-08-21 Daniel Gutson * target-arm/translate.c (disas_neon_data_insn): Fixed shift operand. -- Daniel Gutson CodeSourcery www.codesourcery.com --------------050403060305060008010508 Content-Type: text/x-diff; name="neon_fix.patch" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="neon_fix.patch" diff -Naurp qemu-0.10.5-orig/target-arm/translate.c qemu-0.10.5-dfg/target-arm/translate.c --- qemu-0.10.5-orig/target-arm/translate.c 2009-05-20 13:47:00.000000000 -0700 +++ qemu-0.10.5-dfg/target-arm/translate.c 2009-08-21 13:26:08.000000000 -0700 @@ -4440,6 +4440,7 @@ static int disas_neon_data_insn(CPUState } else if (insn & (1 << 4)) { if ((insn & 0x00380080) != 0) { /* Two registers and shift. */ + uint32_t shift_imm; op = (insn >> 8) & 0xf; if (insn & (1 << 7)) { /* 64-bit shift. */ @@ -4466,17 +4467,17 @@ static int disas_neon_data_insn(CPUState } switch (size) { case 0: - imm = (uint8_t) shift; - imm |= imm << 8; - imm |= imm << 16; + shift_imm = (uint8_t) shift; + shift_imm |= shift_imm << 8; + shift_imm |= shift_imm << 16; break; case 1: - imm = (uint16_t) shift; - imm |= imm << 16; + shift_imm = (uint16_t) shift; + shift_imm |= shift_imm << 16; break; case 2: case 3: - imm = shift; + shift_imm = shift; break; default: abort(); @@ -4485,7 +4486,7 @@ static int disas_neon_data_insn(CPUState for (pass = 0; pass < count; pass++) { if (size == 3) { neon_load_reg64(cpu_V0, rm + pass); - tcg_gen_movi_i64(cpu_V1, imm); + tcg_gen_movi_i64(cpu_V1, shift_imm); switch (op) { case 0: /* VSHR */ case 1: /* VSRA */ @@ -4530,7 +4531,7 @@ static int disas_neon_data_insn(CPUState neon_store_reg64(cpu_V0, rd + pass); } else { /* size < 3 */ /* Operands in T0 and T1. */ - gen_op_movl_T1_im(imm); + gen_op_movl_T1_im(shift_imm); NEON_GET_REG(T0, rm, pass); switch (op) { case 0: /* VSHR */ --------------050403060305060008010508--