From: Ayaz Abdulla <aabdulla@nvidia.com>
To: David Miller <davem@davemloft.net>
Cc: "manfred@colorfullife.com" <manfred@colorfullife.com>,
"akpm@osdl.org" <akpm@osdl.org>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>
Subject: Re: [PATCH] forcedeth: updated phy errata
Date: Fri, 04 Sep 2009 09:57:59 -0400 [thread overview]
Message-ID: <4AA11CE7.7050400@nvidia.com> (raw)
In-Reply-To: <20090902.232201.248326790.davem@davemloft.net>
David Miller wrote:
> From: Ayaz Abdulla <aabdulla@nvidia.com>
> Date: Mon, 31 Aug 2009 19:08:37 -0400
>
>
>>This patch updates the special programming (and/or errata) needed in
>>order to setup the phy for various vendor models.
>>
>>The new models include:
>>Marvell E1116
>>Marvell E1111
>>Marvell E1011
>>Marvell E3016
>>Broadcom 9507
>>Broadcom AC131
>>Broadcom 50610
>>
>>Signed-off-by: Ayaz Abdulla <aabdulla@nvidia.com>
>
>
> Please document what these individual bits mean which you
> are clearing, by using an individual define for each register
> bit to describe it's purpose, and then define the mask as
> a concatenation of these bits.
>
> Having an opaque bitmask is not how to do this.
Unfortunately, the phy vendors don't want us exposing the meaning of
their non-standard bits.
>
> Thanks.
next prev parent reply other threads:[~2009-09-04 19:25 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-08-31 23:08 [PATCH] forcedeth: updated phy errata Ayaz Abdulla
2009-09-03 6:22 ` David Miller
2009-09-04 13:57 ` Ayaz Abdulla [this message]
2009-09-04 22:00 ` David Miller
2009-09-04 17:22 ` Ayaz Abdulla
2009-09-04 22:54 ` David Miller
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