From: Magnus Lilja <lilja.magnus@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] imx51:Add support basic boot code of freescale imx51 bbg board
Date: Mon, 21 Sep 2009 19:55:27 +0200 [thread overview]
Message-ID: <4AB7BE0F.4020602@gmail.com> (raw)
In-Reply-To: <12534677012313-git-send-email-fanyefeng@gmail.com>
Hi
I've scanned the patch briefly and have some comments below.
gareatech at gmail.com wrote:
> From: Fred Fan <fanyefeng@gmail.com>
>
> This patch just supports boot into u-boot from mmc or spi-nor flash.
> It just implements console, iomux and clock. There are no ethernet,
> nor-flash, mmc or other peripheral drivers.
>
> Sign-of-by: Fred.Fan <fanyefeng@gmail.com>
> Sign-of-by: Fred.Fan <r01011@freescale.com>
Should be 'Signed-off-by: FredFan <fanyefeng@gmail.com>'.
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 620604c..5fb1221 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -549,6 +549,10 @@ Fabio Estevam <Fabio.Estevam@freescale.com>
>
> mx31pdk i.MX31
>
> +Fred Fan <fanyefeng@gmail.com>
> +
> + imx51 i.MX51
> +
Is imx51 really the name of this board? Later on it looks like the name is MX51_BABBAGE.
> Peter Figuli <peposh@etc.sk>
>
> wepep250 xscale
> diff --git a/MAKEALL b/MAKEALL
> index edebaea..ed8c437 100755
> --- a/MAKEALL
> +++ b/MAKEALL
<snip>
> diff --git a/board/freescale/imx51/Makefile b/board/freescale/imx51/Makefile
> new file mode 100644
> index 0000000..fbd40f2
> --- /dev/null
> +++ b/board/freescale/imx51/Makefile
<snip>
> diff --git a/board/freescale/imx51/board-imx51.h b/board/freescale/imx51/board-imx51.h
> new file mode 100644
> index 0000000..7a2cae0
> --- /dev/null
> +++ b/board/freescale/imx51/board-imx51.h
> @@ -0,0 +1,64 @@
> +/*
> + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
> + */
> +
> +/*
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#ifndef __BOARD_FREESCALE_BOARD_IMX51_H__
> +#define __BOARD_FREESCALE_BOARD_IMX51_H__
> +
> +/*!
> + * @defgroup BRDCFG_MX51 Board Configuration Options
> + * @ingroup MSL_MX51
> + */
> +
> +/*!
> + * @file mx51_3stack/board-imx51.h
> + *
> + * @brief This file contains all the board level configuration options.
> + *
> + * It currently hold the options defined for MX51 3Stack Platform.
> + *
> + * @ingroup BRDCFG_IMX51
> + */
> +
> +/* CPLD offsets */
> +#define PBC_LED_CTRL (0x20000)
> +#define PBC_SB_STAT (0x20008)
> +#define PBC_ID_AAAA (0x20040)
> +#define PBC_ID_5555 (0x20048)
> +#define PBC_VERSION (0x20050)
> +#define PBC_ID_CAFE (0x20058)
> +#define PBC_INT_STAT (0x20010)
> +#define PBC_INT_MASK (0x20038)
> +#define PBC_INT_REST (0x20020)
> +#define PBC_SW_RESET (0x20060)
> +
> +/* LED switchs */
> +#define LED_SWITCH_REG 0x00
> +/* buttons */
> +#define SWITCH_BUTTONS_REG 0x08
> +/* status, interrupt */
> +#define INTR_STATUS_REG 0x10
> +#define INTR_MASK_REG 0x38
> +#define INTR_RESET_REG 0x20
> +/* magic word for debug CPLD */
> +#define MAGIC_NUMBER1_REG 0x40
> +#define MAGIC_NUMBER2_REG 0x48
> +/* CPLD code version */
> +#define CPLD_CODE_VER_REG 0x50
> +/* magic word for debug CPLD */
> +#define MAGIC_NUMBER3_REG 0x58
> +/* module reset register*/
> +#define MODULE_RESET_REG 0x60
> +/* CPU ID and Personality ID */
> +#define MCU_BOARD_ID_REG 0x68
> +
> +#endif /* __BOARD_FREESCALE_BOARD_IMX51_H__ */
> diff --git a/board/freescale/imx51/config.mk b/board/freescale/imx51/config.mk
> new file mode 100644
> index 0000000..d8b0f10
> --- /dev/null
> +++ b/board/freescale/imx51/config.mk
> @@ -0,0 +1,2 @@
> +LDSCRIPT = board/$(VENDOR)/$(BOARD)/u-boot.lds
> +TEXT_BASE = 0x97800000
> diff --git a/board/freescale/imx51/flash_header.S b/board/freescale/imx51/flash_header.S
> new file mode 100644
> index 0000000..6790679
> --- /dev/null
> +++ b/board/freescale/imx51/flash_header.S
> @@ -0,0 +1,113 @@
> +/*
> + * Copyright 2009 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
I wouldn't mind a short description of what this file does and why it's needed.
> +#include <config.h>
> +#include <asm/arch/mx51.h>
> +#include "board-imx51.h"
> +
> +#ifdef CONFIG_FLASH_HEADER
> +#ifndef CONFIG_FLASH_HEADER_OFFSET
> +# error "Must define the offset of flash header"
> +#endif
> +#define MXC_DCD_ITEM(i, type, addr, val) \
> +dcd_node_##i: \
> + .word type ; \
> + .word addr ; \
> + .word val ; \
> +
> +.section ".text.flasheader", "x"
> + b _start
> + .org CONFIG_FLASH_HEADER_OFFSET
> +app_code_jump_v: .word _start
> +app_code_code_barker: .word CONFIG_FLASH_HEADER_BARKER
> +app_code_csf: .word 0
> +dcd_ptr_ptr: .word dcd_ptr
> +super_root_key: .word 0
> +dcd_ptr: .word dcd_array_start
> +app_dest_ptr: .word TEXT_BASE
> +dcd_array_start:
> +magic: .word 0xB17219E9
> +dcd_array_size: .word dcd_data_end - dcd_array_start - 8
> +/* DCD */
> +/* DDR2 IOMUX configuration */
> +MXC_DCD_ITEM(1, 4, IOMUXC_BASE_ADDR + 0x8a0, 0x200)
> +MXC_DCD_ITEM(2, 4, IOMUXC_BASE_ADDR + 0x50c, 0x20c5)
> +MXC_DCD_ITEM(3, 4, IOMUXC_BASE_ADDR + 0x510, 0x20c5)
> +MXC_DCD_ITEM(4, 4, IOMUXC_BASE_ADDR + 0x83c, 0x2)
> +MXC_DCD_ITEM(5, 4, IOMUXC_BASE_ADDR + 0x848, 0x2)
> +MXC_DCD_ITEM(6, 4, IOMUXC_BASE_ADDR + 0x4b8, 0xe7)
> +MXC_DCD_ITEM(7, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x45)
> +MXC_DCD_ITEM(8, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x45)
> +MXC_DCD_ITEM(9, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x45)
> +MXC_DCD_ITEM(10, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x45)
> +MXC_DCD_ITEM(11, 4, IOMUXC_BASE_ADDR + 0x820, 0x0)
> +MXC_DCD_ITEM(12, 4, IOMUXC_BASE_ADDR + 0x4a4, 0x3)
> +MXC_DCD_ITEM(13, 4, IOMUXC_BASE_ADDR + 0x4a8, 0x3)
> +MXC_DCD_ITEM(14, 4, IOMUXC_BASE_ADDR + 0x4ac, 0xe3)
> +MXC_DCD_ITEM(15, 4, IOMUXC_BASE_ADDR + 0x4b0, 0xe3)
> +MXC_DCD_ITEM(16, 4, IOMUXC_BASE_ADDR + 0x4b4, 0xe3)
> +MXC_DCD_ITEM(17, 4, IOMUXC_BASE_ADDR + 0x4cc, 0xe3)
> +MXC_DCD_ITEM(18, 4, IOMUXC_BASE_ADDR + 0x4d0, 0xe2)
> +/* Set drive strength to MAX */
> +MXC_DCD_ITEM(19, 4, IOMUXC_BASE_ADDR + 0x82c, 0x6)
> +MXC_DCD_ITEM(20, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x6)
> +MXC_DCD_ITEM(21, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x6)
> +MXC_DCD_ITEM(22, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x6)
> +/* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */
> +/* CAS=3, BL=4 */
> +MXC_DCD_ITEM(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000)
> +MXC_DCD_ITEM(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000)
> +MXC_DCD_ITEM(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0)
> +MXC_DCD_ITEM(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x333574aa)
> +MXC_DCD_ITEM(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x333574aa)
> +/* Init DRAM on CS0 */
> +MXC_DCD_ITEM(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
> +MXC_DCD_ITEM(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a)
> +MXC_DCD_ITEM(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801b)
> +MXC_DCD_ITEM(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00448019)
> +MXC_DCD_ITEM(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x07328018)
> +MXC_DCD_ITEM(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
> +MXC_DCD_ITEM(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
> +MXC_DCD_ITEM(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
> +MXC_DCD_ITEM(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x06328018)
> +MXC_DCD_ITEM(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x03808019)
> +MXC_DCD_ITEM(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00408019)
> +MXC_DCD_ITEM(39, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000)
> +/* Init DRAM on CS1 */
> +MXC_DCD_ITEM(40, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
> +MXC_DCD_ITEM(41, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801e)
> +MXC_DCD_ITEM(42, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801f)
> +MXC_DCD_ITEM(43, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801d)
> +MXC_DCD_ITEM(44, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0732801c)
> +MXC_DCD_ITEM(45, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
> +MXC_DCD_ITEM(46, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
> +MXC_DCD_ITEM(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
> +MXC_DCD_ITEM(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0632801c)
> +MXC_DCD_ITEM(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0380801d)
> +MXC_DCD_ITEM(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0040801d)
> +MXC_DCD_ITEM(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004)
> +MXC_DCD_ITEM(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xb2a20000)
> +MXC_DCD_ITEM(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000)
> +MXC_DCD_ITEM(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0)
> +MXC_DCD_ITEM(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000)
> +MXC_DCD_ITEM(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
> +dcd_data_end:
> +image_len: .word 0x100000
> +//image_len: .word _end - _start
> +#endif
> diff --git a/board/freescale/imx51/imx51.c b/board/freescale/imx51/imx51.c
> new file mode 100644
> index 0000000..f152c9a
> --- /dev/null
> +++ b/board/freescale/imx51/imx51.c
> @@ -0,0 +1,233 @@
> +/*
> + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
> + *
> + * (C) Copyright 2009 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/mx51.h>
> +#include <asm/arch/mx51_pins.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/errno.h>
> +#include <i2c.h>
> +#include "board-imx51.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static u32 system_rev;
> +u32 mx51_io_base_addr;
> +volatile u32 *esdhc_base_pointer;
> +
> +u32 get_board_rev(void)
> +{
> + return system_rev;
> +}
> +
> +static inline void setup_soc_rev(void)
> +{
> + int reg;
Add empty line after variable declarations? (makes the code more readable imo)
> + reg = __raw_readl(ROM_SI_REV);
> + switch (reg) {
> + case 0x02:
> + system_rev = 0x51000 | CHIP_REV_1_1;
> + break;
> + case 0x10:
> + if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0) {
> + system_rev = 0x51000 | CHIP_REV_2_5;
> + } else {
> + system_rev = 0x51000 | CHIP_REV_2_0;
> + }
> + break;
> + default:
> + system_rev = 0x51000 | CHIP_REV_1_0;
Add a 'break;' to the default even though it's the last one.
> + }
> +}
> +
> +static inline void set_board_rev(int rev)
> +{
> + system_rev |= (rev & 0xF) << 8;
> +}
> +
> +inline int is_soc_rev(int rev)
> +{
> + return (system_rev & 0xFF) - rev;
> +}
> +
> +int dram_init(void)
> +{
> + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
> + return 0;
> +}
> +
> +static void setup_uart(void)
> +{
> + unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
> + PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
Add empty line after variable declarations.
> + mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
> + mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
> + mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
> + mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
> + mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
> + mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
> + mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
> + mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
> +}
> +
> +void setup_nfc(void)
> +{
> + /* Enable NFC IOMUX */
> + mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT0);
> +}
Since it's very likely that setup_nfc() and setup_uart() will be used in other i.MX51 boards as well it's a good idea to
place these functions in cpu/arm_cortexa8/mx51/devices.c (or something similar).
> +
> +static void setup_expio(void)
> +{
> + u32 reg;
Add empty line after variable declarations.
> + /* CS5 setup */
> + mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0);
> + writel(0x00410089, WEIM_BASE_ADDR + 0x78 + CSGCR1);
> + writel(0x00000002, WEIM_BASE_ADDR + 0x78 + CSGCR2);
> + /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
> + writel(0x32260000, WEIM_BASE_ADDR + 0x78 + CSRCR1);
> + /* APR = 0 */
> + writel(0x00000000, WEIM_BASE_ADDR + 0x78 + CSRCR2);
> + /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0,
> + * WCSA=0, WCSN=0
> + */
> + writel(0x72080F00, WEIM_BASE_ADDR + 0x78 + CSWCR1);
> + if ((readw(CS5_BASE_ADDR + PBC_ID_AAAA) == 0xAAAA) &&
> + (readw(CS5_BASE_ADDR + PBC_ID_5555) == 0x5555)) {
> + if (is_soc_rev(CHIP_REV_2_0) < 0) {
> + reg = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
> + reg = (reg & (~0x70000)) | 0x30000;
> + writel(reg, CCM_BASE_ADDR + CLKCTL_CBCDR);
> + /* make sure divider effective */
> + while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0)
> + ;
> + writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
> + }
> + mx51_io_base_addr = CS5_BASE_ADDR;
> + } else {
> + /* CS1 */
> + writel(0x00410089, WEIM_BASE_ADDR + 0x18 + CSGCR1);
> + writel(0x00000002, WEIM_BASE_ADDR + 0x18 + CSGCR2);
> + /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
> + writel(0x32260000, WEIM_BASE_ADDR + 0x18 + CSRCR1);
> + /* APR=0 */
> + writel(0x00000000, WEIM_BASE_ADDR + 0x18 + CSRCR2);
> + /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0,
> + * WEN=0, WCSA=0, WCSN=0
> + */
> + writel(0x72080F00, WEIM_BASE_ADDR + 0x18 + CSWCR1);
> + mx51_io_base_addr = CS1_BASE_ADDR;
> + }
> +
> + /* Reset interrupt status reg */
> + writew(0x1F, mx51_io_base_addr + PBC_INT_REST);
> + writew(0x00, mx51_io_base_addr + PBC_INT_REST);
> + writew(0xFFFF, mx51_io_base_addr + PBC_INT_MASK);
> +
> + /* Reset the XUART and Ethernet controllers */
> + reg = readw(mx51_io_base_addr + PBC_SW_RESET);
> + reg |= 0x9;
> + writew(reg, mx51_io_base_addr + PBC_SW_RESET);
> + reg &= ~0x9;
> + writew(reg, mx51_io_base_addr + PBC_SW_RESET);
> +}
> +
> +#ifdef CONFIG_NET_MULTI
> +
> +#if defined(CONFIG_DRIVER_SMC911X)
> +extern int smc911x_initialize(bd_t *bis);
> +#endif
> +int board_eth_init(bd_t *bis)
> +{
> + int rc = -ENODEV;
> +
> +#if defined(CONFIG_DRIVER_SMC911X)
> + rc = smc911x_initialize(bis);
> +#endif
> +
> + return rc;
> +}
> +#endif
> +
> +int board_init(void)
> +{
> + setup_soc_rev();
> +
> + gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE; /* board id for linux */
> + /* address of boot parameters */
> + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
> +
> + setup_uart();
> + setup_nfc();
> + setup_expio();
> + return 0;
> +}
> +
> +#ifdef BOARD_LATE_INIT
> +int board_late_init(void)
> +{
> + return 0;
> +}
> +#endif
> +
> +int checkboard(void)
> +{
> + printf("Board: MX51 BABBAGE ");
> +
> + if (system_rev & CHIP_REV_2_5) {
> + printf("2.5 [");
> + } else if (system_rev & CHIP_REV_2_0) {
> + printf("2.0 [");
> + } else if (system_rev & CHIP_REV_1_1) {
> + printf("1.1 [");
> + } else {
> + printf("1.0 [");
> + }
> +
> + switch (__raw_readl(SRC_BASE_ADDR + 0x8)) {
> + case 0x0001:
> + printf("POR");
> + break;
> + case 0x0009:
> + printf("RST");
> + break;
> + case 0x0010:
> + case 0x0011:
> + printf("WDOG");
> + break;
> + default:
> + printf("unknown");
> + }
> + printf("]\n");
> + return 0;
> +}
> +
> diff --git a/board/freescale/imx51/lowlevel_init.S b/board/freescale/imx51/lowlevel_init.S
> new file mode 100644
> index 0000000..e1296f8
> --- /dev/null
> +++ b/board/freescale/imx51/lowlevel_init.S
> @@ -0,0 +1,281 @@
> +/*
> + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
> + *
> + * (C) Copyright 2009 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <config.h>
> +#include <asm/arch/mx51.h>
> +#include "board-imx51.h"
> +
> +/*
> + * return soc version
> + * 0x10: TO1
> + * 0x20: TO2
> + * 0x30: TO3
> + */
> +.macro check_soc_version ret, tmp
> +.endm
> +
> +/*
> + * L2CC Cache setup/invalidation/disable
> + */
> +.macro init_l2cc
> + /* reconfigure L2 cache aux control reg */
> + ldr r0, =0x03C000C4
> + mcr p15, 1, r0, c9, c0, 2
> +.endm /* init_l2cc */
> +
> +/* AIPS setup - Only setup MPROTx registers.
> + * The PACR default values are good.*/
> +.macro init_aips
> + /*
> + * Set all MPROTx to be non-bufferable, trusted for R/W,
> + * not forced to user-mode.
> + */
> + ldr r0, =AIPS1_BASE_ADDR
> + ldr r1, =0x77777777
> + str r1, [r0, #0x0]
> + str r1, [r0, #0x4]
> + ldr r0, =AIPS2_BASE_ADDR
> + str r1, [r0, #0x0]
> + str r1, [r0, #0x4]
> + /*
> + * Clear the on and off peripheral modules Supervisor Protect bit
> + * for SDMA to access them. Did not change the AIPS control registers
> + * (offset 0x20) access type
> + */
> +.endm /* init_aips */
> +
> +/* MAX (Multi-Layer AHB Crossbar Switch) setup */
> +.macro init_max
> +.endm /* init_max */
> +
> +/* M4IF setup */
> +.macro init_m4if
> + /* VPU and IPU given higher priority (0x4)
> + * IPU accesses with ID=0x1 given highest priority (=0xA)
> + */
> + ldr r0, =M4IF_BASE_ADDR
> +
> + ldr r1, =0x00000203
> + str r1, [r0, #0x40]
> +
> + ldr r1, =0x0
> + str r1, [r0, #0x44]
> +
> + ldr r1, =0x00120125
> + str r1, [r0, #0x9C]
> +
> + ldr r1, =0x001901A3
> + str r1, [r0, #0x48]
> +
> +/*
> + ldr r1, =0x00000a01
> + str r1, [r0, #0x48]
> + ldr r1, =0x00000404
> + str r1, [r0, #0x40]
> +*/
> +.endm /* init_m4if */
> +
> +/* To support 133MHz DDR */
> +.macro init_drive_strength
> +.endm /* init_drive_strength */
> +
> +/* CPLD on CS5 setup */
> +.macro init_debug_board
> +.endm /* init_debug_board */
Remove these two since they don't do anything?
> +
> +.macro setup_pll pll, freq
> + ldr r2, =\pll
> + ldr r1, =0x00001232
> + str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
> + mov r1, #0x2
> + str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
> +
> + str r3, [r2, #PLL_DP_OP]
> + str r3, [r2, #PLL_DP_HFS_OP]
> +
> + str r4, [r2, #PLL_DP_MFD]
> + str r4, [r2, #PLL_DP_HFS_MFD]
> +
> + str r5, [r2, #PLL_DP_MFN]
> + str r5, [r2, #PLL_DP_HFS_MFN]
> +
> + ldr r1, =0x00001232
> + str r1, [r2, #PLL_DP_CTL]
> +1: ldr r1, [r2, #PLL_DP_CTL]
> + ands r1, r1, #0x1
> + beq 1b
> +.endm
> +
> +.macro init_clock
> + ldr r0, =CCM_BASE_ADDR
> + mov r1, #0x00060000
> + str r1, [r0, #CLKCTL_CCDR]
> +
> + /* Switch ARM to step clock */
> + mov r1, #0x4
> + str r1, [r0, #CLKCTL_CCSR]
> +
> + mov r3, #DP_OP_800
> + mov r4, #DP_MFD_800
> + mov r5, #DP_MFN_800
> + setup_pll PLL1_BASE_ADDR
> + mov r3, #DP_OP_665
> + mov r4, #DP_MFD_665
> + mov r5, #DP_MFN_665
> + setup_pll PLL3_BASE_ADDR
> +
> + /* Switch peripheral to PLL 3 */
> + ldr r1, =0x0000D3C0
> + str r1, [r0, #CLKCTL_CBCMR]
> + ldr r1, =0x033B9145
> + str r1, [r0, #CLKCTL_CBCDR]
> + mov r3, #DP_OP_665
> + mov r4, #DP_MFD_665
> + mov r5, #DP_MFN_665
> + setup_pll PLL2_BASE_ADDR
> +
> + /* Switch peripheral to PLL2 */
> + ldr r1, =0x013B9145
> + str r1, [r0, #CLKCTL_CBCDR]
> + ldr r1, =0x0000E3C0
> + str r1, [r0, #CLKCTL_CBCMR]
> +
> + mov r3, #DP_OP_216
> + mov r4, #DP_MFD_216
> + mov r5, #DP_MFN_216
> + setup_pll PLL3_BASE_ADDR
> +
> + /* Set the platform clock dividers */
> + ldr r2, =ARM_BASE_ADDR
> + ldr r1, =0x00000725
> + str r1, [r2, #0x14]
> +
> + /* Switch ARM back to PLL 1 */
> + mov r1, #0
> + str r1, [r0, #CLKCTL_CCSR]
> + str r1, [r0, #CLKCTL_CACRR]
> +
> + /* Use lp_apm (24MHz) source for perclk */
> + mov r2, #0x48
> + ldr r2, [r0]
> + cmp r2, #0x10
> + ldrhs r1, =0x000020C2
> + ldrlo r1, =0x0000E3C2
> + str r1, [r0, #CLKCTL_CBCMR]
> + /* TO1.x emi = ahb, all perclk dividers are 1 since using 24MHz */
> + /* TO2.x ddr from PLL1, all perclk dividers are 1 since using 24MHz */
> + ldrhs r1, =0x59239100
> + ldrlo r1, =0x013D9100
> + strlo r1, [r0, #CLKCTL_CBCDR]
> +
> + /* use PLL2 for UART source, get 66.5MHz */
> + ldr r1, =0xA5A2A020
> + str r1, [r0, #CLKCTL_CSCMR1]
> + ldr r1, =0x00C30321
> + str r1, [r0, #CLKCTL_CSCDR1]
> +
> + /* make sure divider effective */
> +1: ldr r1, [r0, #CLKCTL_CDHIPR]
> + cmp r1, #0
> + bne 1b
> +
> + mov r1, #0x0
> + str r1, [r0, #CLKCTL_CCDR]
> +.endm
> +
> +.macro setup_wdog
> + ldr r0, =WDOG1_BASE_ADDR
> + mov r1, #0x30
> + strh r1, [r0]
> +.endm
> +
> +.section ".text.init", "x"
> +
> +.globl lowlevel_init
> +lowlevel_init:
> + /* Platform CHIP level init*/
> + ldr r0, =GPIO1_BASE_ADDR
> + ldr r1, [r0, #0x0]
> + orr r1, r1, #(1 << 23)
> + str r1, [r0, #0x0]
> + ldr r1, [r0, #0x4]
> + orr r1, r1, #(1 << 23)
> + str r1, [r0, #0x4]
What does the above code do? It seems to do something with a GPIO.
> +
> +#ifdef TURN_OFF_IMPRECISE_ABORT
> + mrs r0, cpsr
> + bic r0, r0, #0x100
> + msr cpsr, r0
> +#endif
> +
> + mrc 15, 0, r1, c1, c0, 0
> +
> +#ifndef BRANCH_PREDICTION_ENABLE
> + mrc 15, 0, r0, c1, c0, 1
> + bic r0, r0, #7
> + mcr 15, 0, r0, c1, c0, 1
> +#else
> + mrc 15, 0, r0, c1, c0, 1
> + orr r0, r0, #7
> + mcr 15, 0, r0, c1, c0, 1
> + orr r1, r1, #(1<<11)
> +#endif
> +
> +#ifdef UNALIGNED_ACCESS_ENABLE
> + orr r1, r1, #(1<<22)
> +#endif
> +
> +#ifdef LOW_INT_LATENCY_ENABLE
> + orr r1, r1, #(1<<21)
> +#endif
> + mcr 15, 0, r1, c1, c0, 0
> +
> + mov r0, #0
> +#ifdef BRANCH_PREDICTION_ENABLE
> + mcr 15, 0, r0, c15, c2, 4
> +#endif
The above #ifdef's should be documented/commented or removed if they're not needed.
> + mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
> +
> + init_l2cc
> +
> + init_aips
> +
> + init_max
> +
> + init_m4if
> +
> + init_drive_strength
> +
> + init_clock
> + init_debug_board
> + /*init_sdram*/
> +
> + /* return from mxc_nand_load */
> + /* r12 saved upper lr*/
> + mov pc, lr
> +
> +/* Board level setting value */
> +DDR_PERCHARGE_CMD: .word 0x04008008
> +DDR_REFRESH_CMD: .word 0x00008010
> +DDR_LMR1_W: .word 0x00338018
> +DDR_LMR_CMD: .word 0xB2220000
> +DDR_TIMING_W: .word 0xB02567A9
> +DDR_MISC_W: .word 0x000A0104
Parts of lowlevel_init.S uses space instead of tabs for indentation.
> diff --git a/board/freescale/imx51/u-boot.lds b/board/freescale/imx51/u-boot.lds
> new file mode 100644
> index 0000000..8cf619f
> --- /dev/null
> +++ b/board/freescale/imx51/u-boot.lds
<snip>
> diff --git a/cpu/arm_cortexa8/mx51/Makefile b/cpu/arm_cortexa8/mx51/Makefile
> new file mode 100644
> index 0000000..ee241ca
> --- /dev/null
> +++ b/cpu/arm_cortexa8/mx51/Makefile
<snip>
> diff --git a/cpu/arm_cortexa8/mx51/clock.c b/cpu/arm_cortexa8/mx51/clock.c
> new file mode 100644
> index 0000000..64f2c61
> --- /dev/null
> +++ b/cpu/arm_cortexa8/mx51/clock.c
> @@ -0,0 +1,229 @@
> +/*
> + * (C) Copyright 2007
> + * Sascha Hauer, Pengutronix
> + *
> + * (C) Copyright 2009 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/mx51.h>
> +#include <asm/errno.h>
> +#include "crm_regs.h"
> +
> +enum pll_clocks {
> +PLL1_CLK = MXC_DPLL1_BASE,
> +PLL2_CLK = MXC_DPLL2_BASE,
> +PLL3_CLK = MXC_DPLL3_BASE,
Indent these?
> +};
> +
> +enum pll_sw_clocks {
> +PLL1_SW_CLK,
> +PLL2_SW_CLK,
> +PLL3_SW_CLK,
Indent these?
> +};
> +
> +static u32 __decode_pll(enum pll_clocks pll, u32 infreq)
> +{
> + u32 mfi, mfn, mfd, pd;
> +
> + mfn = __raw_readl(pll + MXC_PLL_DP_MFN);
> + mfd = __raw_readl(pll + MXC_PLL_DP_MFD) + 1;
> + mfi = __raw_readl(pll + MXC_PLL_DP_OP);
> + pd = (mfi & 0xF) + 1;
> + mfi = (mfi >> 4) & 0xF;
> + mfi = (mfi >= 5) ? mfi : 5;
> +
> + return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
> +}
> +
> +u32 __get_mcu_main_clk(void)
> +{
> + u32 reg, freq;
Insert empty line after variable declarations for readability.
> + reg = (__raw_readl(MXC_CCM_CACRR) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
> + MXC_CCM_CACRR_ARM_PODF_OFFSET;
> + freq = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
> + return freq / (reg + 1);
> +}
> +
> +static u32 __get_periph_clk(void)
> +{
> + u32 reg;
Insert empty line after variable declarations for readability.
> + reg = __raw_readl(MXC_CCM_CBCDR);
> + if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
> + reg = __raw_readl(MXC_CCM_CBCMR);
> + switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
> + MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
> + case 0:
> + return __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
> + case 1:
> + return __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ);
> + default:
> + return 0;
> + }
> + }
> + return __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ);
> +}
> +
> +static u32 __get_ipg_clk(void)
> +{
> + u32 ahb_podf, ipg_podf;
> +
> + ahb_podf = __raw_readl(MXC_CCM_CBCDR);
> + ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
> + MXC_CCM_CBCDR_IPG_PODF_OFFSET;
> + ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
> + MXC_CCM_CBCDR_AHB_PODF_OFFSET;
> + return __get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1));
> +}
> +
> +static u32 __get_ipg_per_clk(void)
> +{
> + u32 pred1, pred2, podf;
Insert empty line after variable declarations for readability.
> + if (__raw_readl(MXC_CCM_CBCMR) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
> + return __get_ipg_clk();
> + /* Fixme: not handle what about lpm*/
> + podf = __raw_readl(MXC_CCM_CBCDR);
> + pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
> + MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
> + pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
> + MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
> + podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
> + MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
> +
> + return __get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
> +}
> +
> +static u32 __get_uart_clk(void)
> +{
> + unsigned int freq, reg, pred, podf;
Insert empty line after variable declarations for readability.
> + reg = __raw_readl(MXC_CCM_CSCMR1);
> + switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
> + MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
> + case 0x0:
> + freq = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
> + break;
> + case 0x1:
> + freq = __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ);
> + break;
> + case 0x2:
> + freq = __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ);
> + break;
> + default:
> + return 66500000;
> + }
> +
> + reg = __raw_readl(MXC_CCM_CSCDR1);
> +
> + pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
> + MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
> +
> + podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
> + MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
> + freq /= (pred + 1) * (podf + 1);
> +
> + return freq;
> +}
> +
> +/*!
> ++ * This function returns the low power audio clock.
> ++ */
> +u32 get_lp_apm(void)
> +{
> + u32 ret_val = 0;
> + u32 ccsr = __raw_readl(MXC_CCM_CCSR);
> +
> + if (((ccsr >> 9) & 1) == 0)
> + ret_val = CONFIG_MX51_HCLK_FREQ;
> + else
> + ret_val = ((32768 * 1024));
> +
> + return ret_val;
> +}
> +
> +static u32 __get_cspi_clk(void)
> +{
> + u32 ret_val = 0, pdf, pre_pdf, clk_sel;
> + u32 cscmr1 = __raw_readl(MXC_CCM_CSCMR1);
> + u32 cscdr2 = __raw_readl(MXC_CCM_CSCDR2);
> +
> + pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
> + >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
> + pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
> + >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
> + clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
> + >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
> +
> + switch (clk_sel) {
> + case 0:
> + ret_val = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ) / ((pre_pdf + 1) * (pdf + 1));
> + break;
> + case 1:
> + ret_val = __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ) / ((pre_pdf + 1) * (pdf + 1));
> + break;
> + case 2:
> + ret_val = __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ) / ((pre_pdf + 1) * (pdf + 1));
> + break;
> + default:
> + ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
> + break;
> + }
> +
> + return ret_val;
> +}
> +
> +unsigned int mxc_get_clock(enum mxc_clock clk)
> +{
> + switch (clk) {
> + case MXC_ARM_CLK:
> + return __get_mcu_main_clk();
> + case MXC_AHB_CLK:
> + break;
> + case MXC_IPG_CLK:
> + return __get_ipg_clk();
> + case MXC_IPG_PERCLK:
> + return __get_ipg_per_clk();
> + case MXC_UART_CLK:
> + return __get_uart_clk();
> + case MXC_CSPI_CLK:
> + return __get_cspi_clk();
> + case MXC_FEC_CLK:
> + return __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
> + default:
> + break;
> + }
> + return -1;
> +}
> +
> +void mxc_show_clocks(void)
> +{
> + u32 freq;
Insert empty line after variable declarations for readability.
> + freq = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
> + printf("mx51 pll1: %dMHz\n", freq / 1000000);
> + freq = __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ);
> + printf("mx51 pll2: %dMHz\n", freq / 1000000);
> + freq = __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ);
> + printf("mx51 pll3: %dMHz\n", freq / 1000000);
> + printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
> + printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
> + printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
> + printf("cspi clock : %dHz\n", mxc_get_clock(MXC_CSPI_CLK));
> +}
> diff --git a/cpu/arm_cortexa8/mx51/crm_regs.h b/cpu/arm_cortexa8/mx51/crm_regs.h
> new file mode 100644
> index 0000000..6436bed
> --- /dev/null
> +++ b/cpu/arm_cortexa8/mx51/crm_regs.h
> @@ -0,0 +1,673 @@
> +/*
> + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
> + */
> +
> +/*
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
> +#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
> +
> +#define MXC_CCM_BASE CCM_BASE_ADDR
> +#define MXC_DPLL1_BASE PLL1_BASE_ADDR
> +#define MXC_DPLL2_BASE PLL2_BASE_ADDR
> +#define MXC_DPLL3_BASE PLL3_BASE_ADDR
> +
> +/* PLL Register Offsets */
> +#define MXC_PLL_DP_CTL 0x00
> +#define MXC_PLL_DP_CONFIG 0x04
> +#define MXC_PLL_DP_OP 0x08
> +#define MXC_PLL_DP_MFD 0x0C
> +#define MXC_PLL_DP_MFN 0x10
> +#define MXC_PLL_DP_MFNMINUS 0x14
> +#define MXC_PLL_DP_MFNPLUS 0x18
> +#define MXC_PLL_DP_HFS_OP 0x1C
> +#define MXC_PLL_DP_HFS_MFD 0x20
> +#define MXC_PLL_DP_HFS_MFN 0x24
> +#define MXC_PLL_DP_MFN_TOGC 0x28
> +#define MXC_PLL_DP_DESTAT 0x2c
> +
> +/* PLL Register Bit definitions */
> +#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
> +#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
> +#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
> +#define MXC_PLL_DP_CTL_ADE 0x800
> +#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
> +#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
> +#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
> +#define MXC_PLL_DP_CTL_HFSM 0x80
> +#define MXC_PLL_DP_CTL_PRE 0x40
> +#define MXC_PLL_DP_CTL_UPEN 0x20
> +#define MXC_PLL_DP_CTL_RST 0x10
> +#define MXC_PLL_DP_CTL_RCP 0x8
> +#define MXC_PLL_DP_CTL_PLM 0x4
> +#define MXC_PLL_DP_CTL_BRM0 0x2
> +#define MXC_PLL_DP_CTL_LRF 0x1
> +
> +#define MXC_PLL_DP_CONFIG_BIST 0x8
> +#define MXC_PLL_DP_CONFIG_SJC_CE 0x4
> +#define MXC_PLL_DP_CONFIG_AREN 0x2
> +#define MXC_PLL_DP_CONFIG_LDREQ 0x1
> +
> +#define MXC_PLL_DP_OP_MFI_OFFSET 4
> +#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
> +#define MXC_PLL_DP_OP_PDF_OFFSET 0
> +#define MXC_PLL_DP_OP_PDF_MASK 0xF
> +
> +#define MXC_PLL_DP_MFD_OFFSET 0
> +#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
> +
> +#define MXC_PLL_DP_MFN_OFFSET 0x0
> +#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
> +
> +#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
> +#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
> +#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
> +#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
> +
> +#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
> +#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
> +
> +/* Register addresses of CCM*/
> +#define MXC_CCM_CCR (MXC_CCM_BASE + 0x00)
> +#define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04)
> +#define MXC_CCM_CSR (MXC_CCM_BASE + 0x08)
> +#define MXC_CCM_CCSR (MXC_CCM_BASE + 0x0C)
> +#define MXC_CCM_CACRR (MXC_CCM_BASE + 0x10)
> +#define MXC_CCM_CBCDR (MXC_CCM_BASE + 0x14)
> +#define MXC_CCM_CBCMR (MXC_CCM_BASE + 0x18)
> +#define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x1C)
> +#define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20)
> +#define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x24)
> +#define MXC_CCM_CS1CDR (MXC_CCM_BASE + 0x28)
> +#define MXC_CCM_CS2CDR (MXC_CCM_BASE + 0x2C)
> +#define MXC_CCM_CDCDR (MXC_CCM_BASE + 0x30)
> +#define MXC_CCM_CHSCDR (MXC_CCM_BASE + 0x34)
> +#define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x38)
> +#define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x3C)
> +#define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x40)
> +#define MXC_CCM_CWDR (MXC_CCM_BASE + 0x44)
> +#define MXC_CCM_CDHIPR (MXC_CCM_BASE + 0x48)
> +#define MXC_CCM_CDCR (MXC_CCM_BASE + 0x4C)
> +#define MXC_CCM_CTOR (MXC_CCM_BASE + 0x50)
> +#define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x54)
> +#define MXC_CCM_CISR (MXC_CCM_BASE + 0x58)
> +#define MXC_CCM_CIMR (MXC_CCM_BASE + 0x5C)
> +#define MXC_CCM_CCOSR (MXC_CCM_BASE + 0x60)
> +#define MXC_CCM_CGPR (MXC_CCM_BASE + 0x64)
> +#define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x68)
> +#define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x6C)
> +#define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x70)
> +#define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x74)
> +#define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x78)
> +#define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x7C)
> +#define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x80)
> +#define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x84)
> +
> +/* Define the bits in register CCR */
> +#define MXC_CCM_CCR_COSC_EN (1 << 12)
> +#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11)
> +#define MXC_CCM_CCR_CAMP2_EN (1 << 10)
> +#define MXC_CCM_CCR_CAMP1_EN (1 << 9)
> +#define MXC_CCM_CCR_FPM_EN (1 << 8)
> +#define MXC_CCM_CCR_OSCNT_OFFSET (0)
> +#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
> +
> +/* Define the bits in register CCDR */
> +#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18)
> +#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
> +#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
> +
> +/* Define the bits in register CSR */
> +#define MXC_CCM_CSR_COSR_READY (1 << 5)
> +#define MXC_CCM_CSR_LVS_VALUE (1 << 4)
> +#define MXC_CCM_CSR_CAMP2_READY (1 << 3)
> +#define MXC_CCM_CSR_CAMP1_READY (1 << 2)
> +#define MXC_CCM_CSR_FPM_READY (1 << 1)
> +#define MXC_CCM_CSR_REF_EN_B (1 << 0)
> +
> +/* Define the bits in register CCSR */
> +#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9)
> +#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7)
> +#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
> +#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5)
> +#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
> +#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3)
> +#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
> +#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
> +#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
> +#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
> +
> +/* Define the bits in register CACRR */
> +#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
> +#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
> +
> +/* Define the bits in register CBCDR */
> +#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
> +#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
> +#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22)
> +#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
> +#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
> +#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
> +#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
> +#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
> +#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13)
> +#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
> +#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
> +#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
> +#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
> +#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
> +#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
> +#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
> +#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
> +#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
> +#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
> +#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
> +
> +/* Define the bits in register CBCMR */
> +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
> +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
> +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
> +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
> +#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
> +#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
> +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8)
> +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
> +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6)
> +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
> +#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
> +#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
> +#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
> +#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
> +
> +/* Define the bits in register CSCMR1 */
> +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
> +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
> +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
> +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
> +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26)
> +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
> +#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
> +#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
> +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22)
> +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
> +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
> +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
> +#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
> +#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
> +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
> +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
> +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
> +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
> +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
> +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
> +#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
> +#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
> +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
> +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
> +#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
> +#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
> +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
> +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
> +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
> +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
> +#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
> +#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
> +
> +/* Define the bits in register CSCMR2 */
> +#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET (26)
> +#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK (0x7 << 26)
> +#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
> +#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
> +#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
> +#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
> +#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20)
> +#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20)
> +#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18)
> +#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18)
> +#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16)
> +#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16)
> +#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14)
> +#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14)
> +#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12)
> +#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12)
> +#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10)
> +#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10)
> +#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9)
> +#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6)
> +#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6)
> +#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5)
> +#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4)
> +#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
> +#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2)
> +#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
> +#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3)
> +
> +/* Define the bits in register CSCDR1 */
> +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22)
> +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
> +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
> +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
> +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
> +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
> +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
> +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
> +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11)
> +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
> +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
> +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
> +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
> +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
> +#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
> +#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
> +#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
> +#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
> +
> +/* Define the bits in register CS1CDR and CS2CDR */
> +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
> +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
> +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
> +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
> +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
> +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
> +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
> +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
> +
> +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
> +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
> +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
> +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
> +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
> +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
> +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
> +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
> +
> +/* Define the bits in register CDCDR */
> +#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28)
> +#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
> +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
> +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
> +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
> +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19)
> +#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16)
> +#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16)
> +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
> +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9)
> +#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6)
> +#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6)
> +#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3)
> +#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
> +#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0)
> +#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
> +
> +/* Define the bits in register CHSCCDR */
> +#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12)
> +#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12)
> +#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6)
> +#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6)
> +#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3)
> +#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3)
> +#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0)
> +#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7)
> +
> +/* Define the bits in register CSCDR2 */
> +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
> +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
> +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
> +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
> +#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16)
> +#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
> +#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9)
> +#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
> +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6)
> +#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
> +#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0)
> +#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F)
> +
> +/* Define the bits in register CSCDR3 */
> +#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
> +#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16)
> +#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
> +#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9)
> +#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6)
> +#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6)
> +#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0)
> +#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F)
> +
> +/* Define the bits in register CSCDR4 */
> +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16)
> +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
> +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9)
> +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
> +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6)
> +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
> +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0)
> +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
> +
> +/* Define the bits in register CDHIPR */
> +#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
> +#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6)
> +#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
> +#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4)
> +#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
> +#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2)
> +#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
> +#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
> +
> +/* Define the bits in register CDCR */
> +#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
> +#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
> +#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
> +
> +/* Define the bits in register CLPCR */
> +#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23)
> +#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22)
> +#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21)
> +#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20)
> +#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
> +#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
> +#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
> +#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
> +#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
> +#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
> +#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
> +#define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
> +#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
> +#define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
> +#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
> +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
> +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
> +#define MXC_CCM_CLPCR_LPM_OFFSET (0)
> +#define MXC_CCM_CLPCR_LPM_MASK (0x3)
> +
> +/* Define the bits in register CISR */
> +#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25)
> +#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
> +#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
> +#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
> +#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
> +#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
> +#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
> +#define MXC_CCM_CISR_COSC_READY (0x1 << 6)
> +#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5)
> +#define MXC_CCM_CISR_CKIH_READY (0x1 << 4)
> +#define MXC_CCM_CISR_FPM_READY (0x1 << 3)
> +#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2)
> +#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1)
> +#define MXC_CCM_CISR_LRF_PLL1 (0x1)
> +
> +/* Define the bits in register CIMR */
> +#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25)
> +#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
> +#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20)
> +#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19)
> +#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
> +#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
> +#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
> +#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5)
> +#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4)
> +#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3)
> +#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
> +#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
> +#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1)
> +
> +/* Define the bits in register CCOSR */
> +#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
> +#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
> +#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
> +#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
> +#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
> +#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
> +#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4)
> +#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
> +#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0)
> +#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF)
> +
> +/* Define the bits in registers CGPR */
> +#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4)
> +#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3)
> +#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0)
> +#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7)
> +
> +/* Define the bits in registers CCGRx */
> +#define MXC_CCM_CCGR_CG_MASK 0x3
> +
> +#define MXC_CCM_CCGR0_CG15_OFFSET 30
> +#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30)
> +#define MXC_CCM_CCGR0_CG14_OFFSET 28
> +#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28)
> +#define MXC_CCM_CCGR0_CG13_OFFSET 26
> +#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26)
> +#define MXC_CCM_CCGR0_CG12_OFFSET 24
> +#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24)
> +#define MXC_CCM_CCGR0_CG11_OFFSET 22
> +#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22)
> +#define MXC_CCM_CCGR0_CG10_OFFSET 20
> +#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20)
> +#define MXC_CCM_CCGR0_CG9_OFFSET 18
> +#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18)
> +#define MXC_CCM_CCGR0_CG8_OFFSET 16
> +#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16)
> +#define MXC_CCM_CCGR0_CG7_OFFSET 14
> +#define MXC_CCM_CCGR0_CG6_OFFSET 12
> +#define MXC_CCM_CCGR0_CG5_OFFSET 10
> +#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10)
> +#define MXC_CCM_CCGR0_CG4_OFFSET 8
> +#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8)
> +#define MXC_CCM_CCGR0_CG3_OFFSET 6
> +#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6)
> +#define MXC_CCM_CCGR0_CG2_OFFSET 4
> +#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4)
> +#define MXC_CCM_CCGR0_CG1_OFFSET 2
> +#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2)
> +#define MXC_CCM_CCGR0_CG0_OFFSET 0
> +#define MXC_CCM_CCGR0_CG0_MASK 0x3
> +
> +#define MXC_CCM_CCGR1_CG15_OFFSET 30
> +#define MXC_CCM_CCGR1_CG14_OFFSET 28
> +#define MXC_CCM_CCGR1_CG13_OFFSET 26
> +#define MXC_CCM_CCGR1_CG12_OFFSET 24
> +#define MXC_CCM_CCGR1_CG11_OFFSET 22
> +#define MXC_CCM_CCGR1_CG10_OFFSET 20
> +#define MXC_CCM_CCGR1_CG9_OFFSET 18
> +#define MXC_CCM_CCGR1_CG8_OFFSET 16
> +#define MXC_CCM_CCGR1_CG7_OFFSET 14
> +#define MXC_CCM_CCGR1_CG6_OFFSET 12
> +#define MXC_CCM_CCGR1_CG5_OFFSET 10
> +#define MXC_CCM_CCGR1_CG4_OFFSET 8
> +#define MXC_CCM_CCGR1_CG3_OFFSET 6
> +#define MXC_CCM_CCGR1_CG2_OFFSET 4
> +#define MXC_CCM_CCGR1_CG1_OFFSET 2
> +#define MXC_CCM_CCGR1_CG0_OFFSET 0
> +
> +#define MXC_CCM_CCGR2_CG15_OFFSET 30
> +#define MXC_CCM_CCGR2_CG14_OFFSET 28
> +#define MXC_CCM_CCGR2_CG13_OFFSET 26
> +#define MXC_CCM_CCGR2_CG12_OFFSET 24
> +#define MXC_CCM_CCGR2_CG11_OFFSET 22
> +#define MXC_CCM_CCGR2_CG10_OFFSET 20
> +#define MXC_CCM_CCGR2_CG9_OFFSET 18
> +#define MXC_CCM_CCGR2_CG8_OFFSET 16
> +#define MXC_CCM_CCGR2_CG7_OFFSET 14
> +#define MXC_CCM_CCGR2_CG6_OFFSET 12
> +#define MXC_CCM_CCGR2_CG5_OFFSET 10
> +#define MXC_CCM_CCGR2_CG4_OFFSET 8
> +#define MXC_CCM_CCGR2_CG3_OFFSET 6
> +#define MXC_CCM_CCGR2_CG2_OFFSET 4
> +#define MXC_CCM_CCGR2_CG1_OFFSET 2
> +#define MXC_CCM_CCGR2_CG0_OFFSET 0
> +
> +#define MXC_CCM_CCGR3_CG15_OFFSET 30
> +#define MXC_CCM_CCGR3_CG14_OFFSET 28
> +#define MXC_CCM_CCGR3_CG13_OFFSET 26
> +#define MXC_CCM_CCGR3_CG12_OFFSET 24
> +#define MXC_CCM_CCGR3_CG11_OFFSET 22
> +#define MXC_CCM_CCGR3_CG10_OFFSET 20
> +#define MXC_CCM_CCGR3_CG9_OFFSET 18
> +#define MXC_CCM_CCGR3_CG8_OFFSET 16
> +#define MXC_CCM_CCGR3_CG7_OFFSET 14
> +#define MXC_CCM_CCGR3_CG6_OFFSET 12
> +#define MXC_CCM_CCGR3_CG5_OFFSET 10
> +#define MXC_CCM_CCGR3_CG4_OFFSET 8
> +#define MXC_CCM_CCGR3_CG3_OFFSET 6
> +#define MXC_CCM_CCGR3_CG2_OFFSET 4
> +#define MXC_CCM_CCGR3_CG1_OFFSET 2
> +#define MXC_CCM_CCGR3_CG0_OFFSET 0
> +
> +#define MXC_CCM_CCGR4_CG15_OFFSET 30
> +#define MXC_CCM_CCGR4_CG14_OFFSET 28
> +#define MXC_CCM_CCGR4_CG13_OFFSET 26
> +#define MXC_CCM_CCGR4_CG12_OFFSET 24
> +#define MXC_CCM_CCGR4_CG11_OFFSET 22
> +#define MXC_CCM_CCGR4_CG10_OFFSET 20
> +#define MXC_CCM_CCGR4_CG9_OFFSET 18
> +#define MXC_CCM_CCGR4_CG8_OFFSET 16
> +#define MXC_CCM_CCGR4_CG7_OFFSET 14
> +#define MXC_CCM_CCGR4_CG6_OFFSET 12
> +#define MXC_CCM_CCGR4_CG5_OFFSET 10
> +#define MXC_CCM_CCGR4_CG4_OFFSET 8
> +#define MXC_CCM_CCGR4_CG3_OFFSET 6
> +#define MXC_CCM_CCGR4_CG2_OFFSET 4
> +#define MXC_CCM_CCGR4_CG1_OFFSET 2
> +#define MXC_CCM_CCGR4_CG0_OFFSET 0
> +
> +#define MXC_CCM_CCGR5_CG15_OFFSET 30
> +#define MXC_CCM_CCGR5_CG14_OFFSET 28
> +#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28)
> +#define MXC_CCM_CCGR5_CG13_OFFSET 26
> +#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26)
> +#define MXC_CCM_CCGR5_CG12_OFFSET 24
> +#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24)
> +#define MXC_CCM_CCGR5_CG11_OFFSET 22
> +#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22)
> +#define MXC_CCM_CCGR5_CG10_OFFSET 20
> +#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20)
> +#define MXC_CCM_CCGR5_CG9_OFFSET 18
> +#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18)
> +#define MXC_CCM_CCGR5_CG8_OFFSET 16
> +#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16)
> +#define MXC_CCM_CCGR5_CG7_OFFSET 14
> +#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14)
> +#define MXC_CCM_CCGR5_CG6_OFFSET 12
> +#define MXC_CCM_CCGR5_CG5_OFFSET 10
> +#define MXC_CCM_CCGR5_CG4_OFFSET 8
> +#define MXC_CCM_CCGR5_CG3_OFFSET 6
> +#define MXC_CCM_CCGR5_CG2_OFFSET 4
> +#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4)
> +#define MXC_CCM_CCGR5_CG1_OFFSET 2
> +#define MXC_CCM_CCGR5_CG0_OFFSET 0
> +
> +#define MXC_CCM_CCGR6_CG4_OFFSET 8
> +#define MXC_CCM_CCGR6_CG4_MASK (0x3 << 8)
> +#define MXC_CCM_CCGR6_CG3_OFFSET 6
> +#define MXC_CCM_CCGR6_CG2_OFFSET 4
> +#define MXC_CCM_CCGR6_CG1_OFFSET 2
> +#define MXC_CCM_CCGR6_CG0_OFFSET 0
> +
> +#define MXC_CORTEXA8_BASE ARM_BASE_ADDR
> +#define MXC_GPC_BASE GPC_BASE_ADDR
> +#define MXC_DPTC_LP_BASE (GPC_BASE_ADDR + 0x80)
> +#define MXC_DPTC_GP_BASE (GPC_BASE_ADDR + 0x100)
> +#define MXC_DVFS_CORE_BASE (GPC_BASE_ADDR + 0x180)
> +#define MXC_DPTC_PER_BASE (GPC_BASE_ADDR + 0x1C0)
> +#define MXC_PGC_IPU_BASE (GPC_BASE_ADDR + 0x220)
> +#define MXC_PGC_VPU_BASE (GPC_BASE_ADDR + 0x240)
> +#define MXC_PGC_GPU_BASE (GPC_BASE_ADDR + 0x260)
> +#define MXC_SRPG_NEON_BASE (GPC_BASE_ADDR + 0x280)
> +#define MXC_SRPG_ARM_BASE (GPC_BASE_ADDR + 0x2A0)
> +#define MXC_SRPG_EMPGC0_BASE (GPC_BASE_ADDR + 0x2C0)
> +#define MXC_SRPG_EMPGC1_BASE (GPC_BASE_ADDR + 0x2D0)
> +#define MXC_SRPG_MEGAMIX_BASE (GPC_BASE_ADDR + 0x2E0)
> +#define MXC_SRPG_EMI_BASE (GPC_BASE_ADDR + 0x300)
> +
> +/* CORTEXA8 platform */
> +#define MXC_CORTEXA8_PLAT_PVID (MXC_CORTEXA8_BASE + 0x0)
> +#define MXC_CORTEXA8_PLAT_GPC (MXC_CORTEXA8_BASE + 0x4)
> +#define MXC_CORTEXA8_PLAT_PIC (MXC_CORTEXA8_BASE + 0x8)
> +#define MXC_CORTEXA8_PLAT_LPC (MXC_CORTEXA8_BASE + 0xC)
> +#define MXC_CORTEXA8_PLAT_NEON_LPC (MXC_CORTEXA8_BASE + 0x10)
> +#define MXC_CORTEXA8_PLAT_ICGC (MXC_CORTEXA8_BASE + 0x14)
> +#define MXC_CORTEXA8_PLAT_AMC (MXC_CORTEXA8_BASE + 0x18)
> +#define MXC_CORTEXA8_PLAT_NMC (MXC_CORTEXA8_BASE + 0x20)
> +#define MXC_CORTEXA8_PLAT_NMS (MXC_CORTEXA8_BASE + 0x24)
> +
> +/* DVFS CORE */
> +#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
> +#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04)
> +#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08)
> +#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C)
> +#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10)
> +#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14)
> +#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18)
> +#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C)
> +#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20)
> +#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24)
> +#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28)
> +#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C)
> +#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30)
> +#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34)
> +#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38)
> +#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
> +#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
> +
> +/* GPC */
> +#define MXC_GPC_CNTR (MXC_GPC_BASE + 0x0)
> +#define MXC_GPC_PGR (MXC_GPC_BASE + 0x4)
> +#define MXC_GPC_VCR (MXC_GPC_BASE + 0x8)
> +#define MXC_GPC_ALL_PU (MXC_GPC_BASE + 0xC)
> +#define MXC_GPC_NEON (MXC_GPC_BASE + 0x10)
> +#define MXC_GPC_PGR_ARMPG_OFFSET 8
> +#define MXC_GPC_PGR_ARMPG_MASK (3 << 8)
> +
> +/* PGC */
> +#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0)
> +#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC)
> +#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0)
> +#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC)
> +#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0)
> +#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC)
> +
> +#define MXC_PGCR_PCR 1
> +#define MXC_SRPGCR_PCR 1
> +#define MXC_EMPGCR_PCR 1
> +#define MXC_PGSR_PSR 1
> +
> +
> +#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
> +#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
> +
> +/* SRPG */
> +#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0)
> +#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4)
> +#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8)
> +
> +#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0)
> +#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4)
> +#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8)
> +
> +#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
> +#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
> +#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
> +
> +#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
> +#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
> +#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
> +
> +#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0)
> +#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4)
> +#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8)
> +
> +#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
> +#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
> +#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
> +
Are all of the above #defines needed/expected to be needed by U-boot?
> +#ifndef __ASSEMBLE__
> +extern unsigned int __get_mcu_main_clk(void);
> +extern void mxc_show_clocks(void);
> +#endif
> +#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
> diff --git a/cpu/arm_cortexa8/mx51/interrupts.c b/cpu/arm_cortexa8/mx51/interrupts.c
> new file mode 100644
> index 0000000..c0d70ac
> --- /dev/null
> +++ b/cpu/arm_cortexa8/mx51/interrupts.c
<snip>
> diff --git a/cpu/arm_cortexa8/mx51/iomux.c b/cpu/arm_cortexa8/mx51/iomux.c
> new file mode 100644
> index 0000000..80082aa
> --- /dev/null
> +++ b/cpu/arm_cortexa8/mx51/iomux.c
<snip>
> diff --git a/cpu/arm_cortexa8/mx51/serial.c b/cpu/arm_cortexa8/mx51/serial.c
> new file mode 100644
> index 0000000..580ac13
> --- /dev/null
> +++ b/cpu/arm_cortexa8/mx51/serial.c
I haven't looked in the details of the serial driver, but would it be possible to use drivers/serial/serial_mxc.c
instead? It looks very similar.
> diff --git a/cpu/arm_cortexa8/mx51/soc.c b/cpu/arm_cortexa8/mx51/soc.c
> new file mode 100644
> index 0000000..cd8ce9d
> --- /dev/null
> +++ b/cpu/arm_cortexa8/mx51/soc.c
<snip>
> diff --git a/cpu/arm_cortexa8/mx51/timer.c b/cpu/arm_cortexa8/mx51/timer.c
> new file mode 100644
> index 0000000..5201768
> --- /dev/null
> +++ b/cpu/arm_cortexa8/mx51/timer.c
<snip>
> diff --git a/include/asm-arm/arch-mx51/iomux.h b/include/asm-arm/arch-mx51/iomux.h
> new file mode 100644
> index 0000000..fa02984
> --- /dev/null
> +++ b/include/asm-arm/arch-mx51/iomux.h
<snip>
> diff --git a/include/asm-arm/arch-mx51/mx51.h b/include/asm-arm/arch-mx51/mx51.h
> new file mode 100644
> index 0000000..4532a10
> --- /dev/null
> +++ b/include/asm-arm/arch-mx51/mx51.h
> @@ -0,0 +1,416 @@
> +/*
> + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
> + */
> +
> +/*
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#ifndef __ASM_ARCH_MXC_MX51_H__
> +#define __ASM_ARCH_MXC_MX51_H__
> +
> +/*
> + * IRAM
> + */
> +#define IRAM_BASE_ADDR 0x1FFE8000 /* internal ram */
> +/*
> + * Graphics Memory of GPU
> + */
> +#define GPU_BASE_ADDR 0x20000000
> +#define GPU_CTRL_BASE_ADDR 0x30000000
> +#define IPU_CTRL_BASE_ADDR 0x40000000
> +/*
> + * Debug
> + */
> +#define DEBUG_BASE_ADDR 0x60000000
> +#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000)
> +#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000)
> +#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000)
> +#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000)
> +#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000)
> +#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000)
> +#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
> +#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
> +
> +/*
> + * SPBA global module enabled #0
> + */
> +#define SPBA0_BASE_ADDR 0x70000000
> +
> +#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
> +#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
> +#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
> +#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
> +#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
> +#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
> +#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
> +#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
> +#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
> +#define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000)
> +#define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000)
> +#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
> +
> +/*
> + * AIPS 1
> + */
> +#define AIPS1_BASE_ADDR 0x73F00000
> +
> +#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
> +#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
> +#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
> +#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
> +#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
> +#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
> +#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
> +#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
> +#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
> +#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
> +#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
> +#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
> +#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
> +#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
> +#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
> +#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
> +#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000)
> +#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
> +#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
> +#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
> +
> +/*
> + * AIPS 2
> + */
> +#define AIPS2_BASE_ADDR 0x83F00000
> +
> +#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
> +#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
> +#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
> +#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
> +#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
> +#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
> +#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
> +#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
> +#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
> +#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
> +#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
> +#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
> +#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
> +#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
> +#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
> +#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
> +#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
> +#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
> +#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
> +#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
> +#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
> +#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
> +#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000)
> +#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
> +#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
> +#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
> +#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
> +#define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
> +#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
> +#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
> +#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
> +#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
> +
> +#define TZIC_BASE_ADDR 0x8FFFC000
> +
> +/*
> + * Memory regions and CS
> + */
> +#define CSD0_BASE_ADDR 0x90000000
> +#define CSD1_BASE_ADDR 0xA0000000
> +#define CS0_BASE_ADDR 0xB0000000
> +#define CS1_BASE_ADDR 0xB8000000
> +#define CS2_BASE_ADDR 0xC0000000
> +#define CS3_BASE_ADDR 0xC8000000
> +#define CS4_BASE_ADDR 0xCC000000
> +#define CS5_BASE_ADDR 0xCE000000
> +
> +/*
> + * NFC
> + */
> +#define NFC_BASE_ADDR_AXI 0xCFFF0000 /* NAND flash AXI */
> +
> +/*!
> + * defines for SPBA modules
> + */
> +#define SPBA_SDHC1 0x04
> +#define SPBA_SDHC2 0x08
> +#define SPBA_UART3 0x0C
> +#define SPBA_CSPI1 0x10
> +#define SPBA_SSI2 0x14
> +#define SPBA_SDHC3 0x20
> +#define SPBA_SDHC4 0x24
> +#define SPBA_SPDIF 0x28
> +#define SPBA_ATA 0x30
> +#define SPBA_SLIM 0x34
> +#define SPBA_HSI2C 0x38
> +#define SPBA_CTRL 0x3C
> +
> +/*
> + * Interrupt numbers
> + */
> +#define MXC_INT_BASE 0
> +#define MXC_INT_RESV0 0
> +#define MXC_INT_MMC_SDHC1 1
> +#define MXC_INT_MMC_SDHC2 2
> +#define MXC_INT_MMC_SDHC3 3
> +#define MXC_INT_MMC_SDHC4 4
> +#define MXC_INT_RESV5 5
> +#define MXC_INT_SDMA 6
> +#define MXC_INT_IOMUX 7
> +#define MXC_INT_NFC 8
> +#define MXC_INT_VPU 9
> +#define MXC_INT_IPU_ERR 10
> +#define MXC_INT_IPU_SYN 11
> +#define MXC_INT_GPU 12
> +#define MXC_INT_RESV13 13
> +#define MXC_INT_USB_H1 14
> +#define MXC_INT_EMI 15
> +#define MXC_INT_USB_H2 16
> +#define MXC_INT_USB_H3 17
> +#define MXC_INT_USB_OTG 18
> +#define MXC_INT_SAHARA_H0 19
> +#define MXC_INT_SAHARA_H1 20
> +#define MXC_INT_SCC_SMN 21
> +#define MXC_INT_SCC_STZ 22
> +#define MXC_INT_SCC_SCM 23
> +#define MXC_INT_SRTC_NTZ 24
> +#define MXC_INT_SRTC_TZ 25
> +#define MXC_INT_RTIC 26
> +#define MXC_INT_CSU 27
> +#define MXC_INT_SLIM_B 28
> +#define MXC_INT_SSI1 29
> +#define MXC_INT_SSI2 30
> +#define MXC_INT_UART1 31
> +#define MXC_INT_UART2 32
> +#define MXC_INT_UART3 33
> +#define MXC_INT_RESV34 34
> +#define MXC_INT_RESV35 35
> +#define MXC_INT_CSPI1 36
> +#define MXC_INT_CSPI2 37
> +#define MXC_INT_CSPI 38
> +#define MXC_INT_GPT 39
> +#define MXC_INT_EPIT1 40
> +#define MXC_INT_EPIT2 41
> +#define MXC_INT_GPIO1_INT7 42
> +#define MXC_INT_GPIO1_INT6 43
> +#define MXC_INT_GPIO1_INT5 44
> +#define MXC_INT_GPIO1_INT4 45
> +#define MXC_INT_GPIO1_INT3 46
> +#define MXC_INT_GPIO1_INT2 47
> +#define MXC_INT_GPIO1_INT1 48
> +#define MXC_INT_GPIO1_INT0 49
> +#define MXC_INT_GPIO1_LOW 50
> +#define MXC_INT_GPIO1_HIGH 51
> +#define MXC_INT_GPIO2_LOW 52
> +#define MXC_INT_GPIO2_HIGH 53
> +#define MXC_INT_GPIO3_LOW 54
> +#define MXC_INT_GPIO3_HIGH 55
> +#define MXC_INT_GPIO4_LOW 56
> +#define MXC_INT_GPIO4_HIGH 57
> +#define MXC_INT_WDOG1 58
> +#define MXC_INT_WDOG2 59
> +#define MXC_INT_KPP 60
> +#define MXC_INT_PWM1 61
> +#define MXC_INT_I2C1 62
> +#define MXC_INT_I2C2 63
> +#define MXC_INT_HS_I2C 64
> +#define MXC_INT_RESV65 65
> +#define MXC_INT_RESV66 66
> +#define MXC_INT_SIM_IPB 67
> +#define MXC_INT_SIM_DAT 68
> +#define MXC_INT_IIM 69
> +#define MXC_INT_ATA 70
> +#define MXC_INT_CCM1 71
> +#define MXC_INT_CCM2 72
> +#define MXC_INT_GPC1 73
> +#define MXC_INT_GPC2 74
> +#define MXC_INT_SRC 75
> +#define MXC_INT_NM 76
> +#define MXC_INT_PMU 77
> +#define MXC_INT_CTI_IRQ 78
> +#define MXC_INT_CTI1_TG0 79
> +#define MXC_INT_CTI1_TG1 80
> +#define MXC_INT_MCG_ERR 81
> +#define MXC_INT_MCG_TMR 82
> +#define MXC_INT_MCG_FUNC 83
> +#define MXC_INT_RESV84 84
> +#define MXC_INT_RESV85 85
> +#define MXC_INT_RESV86 86
> +#define MXC_INT_FEC 87
> +#define MXC_INT_OWIRE 88
> +#define MXC_INT_CTI1_TG2 89
> +#define MXC_INT_SJC 90
> +#define MXC_INT_SPDIF 91
> +#define MXC_INT_TVE 92
> +#define MXC_INT_FIRI 93
> +#define MXC_INT_PWM2 94
> +#define MXC_INT_SLIM_EXP 95
> +#define MXC_INT_SSI3 96
> +#define MXC_INT_RESV97 97
> +#define MXC_INT_CTI1_TG3 98
> +#define MXC_INT_SMC_RX 99
> +#define MXC_INT_VPU_IDLE 100
> +#define MXC_INT_RESV101 101
> +#define MXC_INT_GPU_IDLE 102
> +
> +#define MXC_MAX_INT_LINES 128
> +
> +#define MXC_GPIO_INT_BASE (MXC_MAX_INT_LINES)
> +
> +/*!
> + * Number of GPIO port as defined in the IC Spec
> + */
> +#define GPIO_PORT_NUM 4
> +/*!
> + * Number of GPIO pins per port
> + */
> +#define GPIO_NUM_PIN 32
> +
> +#define MXC_GPIO_SPLIT_IRQ_2
> +
> +#define IIM_SREV 0x24
> +#define ROM_SI_REV 0x48
> +
> +#define NFC_BUF_SIZE 0x1000
> +
> +/* WEIM registers */
> +#define CSGCR1 0x00
> +#define CSGCR2 0x04
> +#define CSRCR1 0x08
> +#define CSRCR2 0x0C
> +#define CSWCR1 0x10
> +
> +/* M4IF */
> +#define M4IF_FBPM0 0x40
> +#define M4IF_FIDBP 0x48
> +
> +/* ESDCTL */
> +#define ESDCTL_ESDCTL0 0x00
> +#define ESDCTL_ESDCFG0 0x04
> +#define ESDCTL_ESDCTL1 0x08
> +#define ESDCTL_ESDCFG1 0x0C
> +#define ESDCTL_ESDMISC 0x10
> +#define ESDCTL_ESDSCR 0x14
> +#define ESDCTL_ESDCDLY1 0x20
> +#define ESDCTL_ESDCDLY2 0x24
> +#define ESDCTL_ESDCDLY3 0x28
> +#define ESDCTL_ESDCDLY4 0x2C
> +#define ESDCTL_ESDCDLY5 0x30
> +#define ESDCTL_ESDCDLYGD 0x34
> +
> +/* CCM */
> +#define CLKCTL_CCR 0x00
> +#define CLKCTL_CCDR 0x04
> +#define CLKCTL_CSR 0x08
> +#define CLKCTL_CCSR 0x0C
> +#define CLKCTL_CACRR 0x10
> +#define CLKCTL_CBCDR 0x14
> +#define CLKCTL_CBCMR 0x18
> +#define CLKCTL_CSCMR1 0x1C
> +#define CLKCTL_CSCMR2 0x20
> +#define CLKCTL_CSCDR1 0x24
> +#define CLKCTL_CS1CDR 0x28
> +#define CLKCTL_CS2CDR 0x2C
> +#define CLKCTL_CDCDR 0x30
> +#define CLKCTL_CHSCCDR 0x34
> +#define CLKCTL_CSCDR2 0x38
> +#define CLKCTL_CSCDR3 0x3C
> +#define CLKCTL_CSCDR4 0x40
> +#define CLKCTL_CWDR 0x44
> +#define CLKCTL_CDHIPR 0x48
> +#define CLKCTL_CDCR 0x4C
> +#define CLKCTL_CTOR 0x50
> +#define CLKCTL_CLPCR 0x54
> +#define CLKCTL_CISR 0x58
> +#define CLKCTL_CIMR 0x5C
> +#define CLKCTL_CCOSR 0x60
> +#define CLKCTL_CGPR 0x64
> +#define CLKCTL_CCGR0 0x68
> +#define CLKCTL_CCGR1 0x6C
> +#define CLKCTL_CCGR2 0x70
> +#define CLKCTL_CCGR3 0x74
> +#define CLKCTL_CCGR4 0x78
> +#define CLKCTL_CCGR5 0x7C
> +#define CLKCTL_CCGR6 0x80
> +#define CLKCTL_CMEOR 0x84
> +
> +/* DPLL */
> +#define PLL_DP_CTL 0x00
> +#define PLL_DP_CONFIG 0x04
> +#define PLL_DP_OP 0x08
> +#define PLL_DP_MFD 0x0C
> +#define PLL_DP_MFN 0x10
> +#define PLL_DP_MFNMINUS 0x14
> +#define PLL_DP_MFNPLUS 0x18
> +#define PLL_DP_HFS_OP 0x1C
> +#define PLL_DP_HFS_MFD 0x20
> +#define PLL_DP_HFS_MFN 0x24
> +#define PLL_DP_TOGC 0x28
> +#define PLL_DP_DESTAT 0x2C
> +
> +/* Assuming 24MHz input clock with doubler ON */
> +/* MFI PDF */
> +#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
> +#define DP_MFD_850 (48 - 1)
> +#define DP_MFN_850 41
> +
> +#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
> +#define DP_MFD_800 (3 - 1)
> +#define DP_MFN_800 1
> +
> +#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
> +#define DP_MFD_700 (24 - 1)
> +#define DP_MFN_700 7
> +
> +#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
> +#define DP_MFD_665 (96 - 1)
> +#define DP_MFN_665 89
> +
> +#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
> +#define DP_MFD_532 (24 - 1)
> +#define DP_MFN_532 13
> +
> +#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
> +#define DP_MFD_400 (3 - 1)
> +#define DP_MFN_400 1
> +
> +#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
> +#define DP_MFD_216 (4 - 1)
> +#define DP_MFN_216 3
> +
> +#define CHIP_REV_1_0 0x10
> +#define CHIP_REV_1_1 0x11
> +#define CHIP_REV_2_0 0x20
> +#define CHIP_REV_2_5 0x120
> +
> +#define BOARD_REV_1_0 0x0
> +#define BOARD_REV_2_0 0x1
> +
> +#ifndef __ASSEMBLER__
> +
> +enum mxc_clock {
> +MXC_ARM_CLK = 0,
> +MXC_AHB_CLK,
> +MXC_IPG_CLK,
> +MXC_IPG_PERCLK,
> +MXC_UART_CLK,
> +MXC_CSPI_CLK,
> +MXC_FEC_CLK,
Indent this.
> +};
I don't think everything in this file is needed by U-Boot, e.g. the interrupt definitions.
> +
> +extern unsigned int mxc_get_clock(enum mxc_clock clk);
> +extern unsigned int get_board_rev(void);
> +extern int is_soc_rev(int rev);
> +
> +#endif /* __ASSEMBLER__*/
> +
> +#endif /* __ASM_ARCH_MXC_MX51_H__ */
> diff --git a/include/asm-arm/arch-mx51/mx51_pins.h b/include/asm-arm/arch-mx51/mx51_pins.h
> new file mode 100644
> index 0000000..63fdd8c
> --- /dev/null
> +++ b/include/asm-arm/arch-mx51/mx51_pins.h
<snip>
> diff --git a/include/configs/imx51.h b/include/configs/imx51.h
> new file mode 100644
> index 0000000..f0def4e
> --- /dev/null
> +++ b/include/configs/imx51.h
> @@ -0,0 +1,177 @@
> +/*
> + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
> + *
> + * (C) Copyright 2009 Freescale Semiconductor, Inc.
> + *
> + * Configuration settings for the MX51-3Stack Freescale board.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#include <asm/arch/mx51.h>
> +
> + /* High Level Configuration Options */
> +#define CONFIG_ARMV7 1 /* This is armv7 Cortex-A8 CPU core */
> +#define CONFIG_L2_OFF
> +
> +#define CONFIG_MXC 1
> +#define CONFIG_MX51_BBG 1 /* in a mx51 */
Can't see that this is used anywhere.
> +#define CONFIG_FLASH_HEADER 1
> +#define CONFIG_FLASH_HEADER_OFFSET 0x400
> +#define CONFIG_FLASH_HEADER_BARKER 0xB1
Looks like a new config option that needs documentation.
> +
> +#define CONFIG_SKIP_RELOCATE_UBOOT
> +
> +#define CONFIG_MX51_HCLK_FREQ 24000000
> +#define CONFIG_MX51_CLK32 32768
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_DISPLAY_BOARDINFO
> +
> +#define BOARD_LATE_INIT
> +/*
> + * Disabled for now due to build problems under Debian and a significant
> + * increase in the final file size: 144260 vs. 109536 Bytes.
> + */
What is disabled?
> +
> +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
> +#define CONFIG_REVISION_TAG 1
> +#define CONFIG_SETUP_MEMORY_TAGS 1
> +#define CONFIG_INITRD_TAG 1
> +
> +/*
> + * Size of malloc() pool
> + */
> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
> +/* size in bytes reserved for initial data */
> +#define CONFIG_SYS_GBL_DATA_SIZE 128
> +
> +#define CONFIG_DOS_PARTITION 1
> +/*
> + * Hardware drivers
> + */
> +#define CONFIG_SERIAL UART1_BASE_ADDR
> +
> +/* allow to overwrite serial and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +#define CONFIG_CONS_INDEX 1
> +#define CONFIG_BAUDRATE 115200
> +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
> +
> +/***********************************************************
> + * Command definition
> + ***********************************************************/
> +
> +#undef CONFIG_CMD_IMLS
> +
> +#define CONFIG_BOOTDELAY 3
> +
> +#define CONFIG_PRIME "FEC0"
> +
> +#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "netdev=eth0\0" \
> + "ethprime=FEC0\0" \
> + "uboot_addr=0xa0000000\0" \
> + "uboot=u-boot.bin\0" \
> + "kernel=uImage\0" \
> + "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
> + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
> + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
> + "bootcmd=run bootcmd_net\0" \
> + "bootcmd_net=run bootargs_base bootargs_nfs; " \
> + "tftpboot ${loadaddr} ${kernel}; bootm\0" \
> +
> +/*
> + * The MX51 3stack board seems to have a hardware "peculiarity" confirmed under
> + * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
> + * controller inverted. The controller is capable of detecting and correcting
> + * this, but it needs 4 network packets for that. Which means, at startup, you
> + * will not receive answers to the first 4 packest, unless there have been some
> + * broadcasts on the network, or your board is on a hub. Reducing the ARP
> + * timeout from default 5 seconds to 200ms we speed up the initial TFTP
> + * transfer, should the user wish one, significantly.
> + */
> +#define CONFIG_ARP_TIMEOUT 200UL
> +
> +/*
> + * Miscellaneous configurable options
> + */
> +#define CONFIG_SYS_LONGHELP /* undef to save memory */
> +#define CONFIG_SYS_PROMPT "BBG U-Boot > "
> +#define CONFIG_AUTO_COMPLETE
> +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
> +/* Print Buffer Size */
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
> +
> +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
Is there a RAM/SDRAM on address 0?
> +#define CONFIG_SYS_MEMTEST_END 0x10000
> +
> +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
> +
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +
> +#define CONFIG_SYS_HZ CONFIG_MX51_CLK32/* use 32kHz clock as source */
CONFIG_SYS_HZ should be 1000 on all boards if I remember correctly.
Regards, Magnus
next prev parent reply other threads:[~2009-09-21 17:55 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-09-20 17:28 [U-Boot] [PATCH] imx51:Add support basic boot code of freescale imx51 bbg board gareatech at gmail.com
2009-09-21 17:55 ` Magnus Lilja [this message]
2009-09-21 20:58 ` Fabio Estevam
[not found] ` <2f495dc80909221219n2f6f303dw478871aede988a7a@mail.gmail.com>
2009-09-22 19:52 ` Magnus Lilja
2009-09-22 20:28 ` Fred Fan
2009-09-22 20:04 ` Magnus Lilja
2009-09-22 20:29 ` Fred Fan
-- strict thread matches above, loose matches on Subject: below --
2009-09-23 14:47 Fred Fan
2009-09-23 21:47 ` Wolfgang Denk
2009-12-01 16:44 ` Fred Fan
2009-12-01 21:15 ` Wolfgang Denk
2009-12-04 11:16 ` Stefano Babic
2009-12-14 2:28 ` Fred Fan
2009-12-29 22:41 ` stefano babic
2009-09-24 4:35 ` Prafulla Wadaskar
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