[U-Boot] [PATCH-ARM 3/3] Add Support for the SBC2440-II Board

[kevin.morfitt at fearnside-systems.co.uk <kevin.morfitt@fearnside-systems.co.uk>]

This patch adds support for the Embest SBC2440-II Board.

Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have
any s3c2400 or s3c2410 boards but need this patch applying before I can submit
patches for the SBC2440-II Board. Also, ran MAKEALL for all ARM9 targets and no
new warnings or errors were found.

Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
---
 MAINTAINERS                            |    4 +
 MAKEALL                                |    1 +
 Makefile                               |    3 +
 board/embest/sbc2440ii/Makefile        |   55 +++++++
 board/embest/sbc2440ii/config.mk       |   25 +++
 board/embest/sbc2440ii/lowlevel_init.S |  219 +++++++++++++++++++++++++++
 board/embest/sbc2440ii/sbc2440ii.c     |  122 +++++++++++++++
 cpu/arm920t/s3c24x0/timer.c            |    1 +
 include/configs/sbc2440ii.h            |  254 ++++++++++++++++++++++++++++++++
 9 files changed, 684 insertions(+), 0 deletions(-)
 create mode 100644 board/embest/sbc2440ii/Makefile
 create mode 100644 board/embest/sbc2440ii/config.mk
 create mode 100644 board/embest/sbc2440ii/lowlevel_init.S
 create mode 100644 board/embest/sbc2440ii/sbc2440ii.c
 create mode 100644 include/configs/sbc2440ii.h

diff --git a/MAINTAINERS b/MAINTAINERS
index d70a9d2..65f8dfe 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -638,6 +638,10 @@ Nishanth Menon <nm@ti.com>
 	omap3_sdp3430	ARM CORTEX-A8 (OMAP3xx SoC)
 	omap3_zoom1	ARM CORTEX-A8 (OMAP3xx SoC)
 
+Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
+
+	sbc2440ii	ARM920T
+
 David M?ller <d.mueller@elsoft.ch>
 
 	smdk2410	ARM920T
diff --git a/MAKEALL b/MAKEALL
index 5492d8f..c84b23e 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -552,6 +552,7 @@ LIST_ARM9="			\
 	openrd_base		\
 	rd6281a			\
 	sbc2410x		\
+	sbc2440ii		\
 	scb9328			\
 	sheevaplug		\
 	smdk2400		\
diff --git a/Makefile b/Makefile
index b91b1c0..a6619e5 100644
--- a/Makefile
+++ b/Makefile
@@ -3020,6 +3020,9 @@ rd6281a_config: unconfig
 sbc2410x_config: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t sbc2410x NULL s3c24x0
 
+sbc2440ii_config: unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm920t sbc2440ii embest s3c24x0
+
 scb9328_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t scb9328 NULL imx
 
diff --git a/board/embest/sbc2440ii/Makefile b/board/embest/sbc2440ii/Makefile
new file mode 100644
index 0000000..26237a2
--- /dev/null
+++ b/board/embest/sbc2440ii/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Modified for EMBEST SBC2440-II board with S3C2440 (ARM920T) cpu by:
+# (C) Copyright 2009
+# Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt@fearnside-systems.co.uk>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB  = $(obj)lib$(BOARD).a
+
+COBJS   := sbc2440ii.o
+SOBJS   := lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/embest/sbc2440ii/config.mk b/board/embest/sbc2440ii/config.mk
new file mode 100644
index 0000000..def11d8
--- /dev/null
+++ b/board/embest/sbc2440ii/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu
+#
+# see http://www.samsung.com/ for more information on SAMSUNG
+#
+# Modified for EMBEST SBC2440-II board with S3C2440 (ARM920T) cpu by:
+# (C) Copyright 2009
+# Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt@fearnside-systems.co.uk>
+
+#
+# SBC2440-II has 1 bank of 64 MB DRAM
+#
+# 3000'0000 to 3800'0000
+#
+# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
+#
+# we load ourself to 33F8'0000
+#
+# download area is 3000'0000
+
+TEXT_BASE = 0x33F80000
diff --git a/board/embest/sbc2440ii/lowlevel_init.S b/board/embest/sbc2440ii/lowlevel_init.S
new file mode 100644
index 0000000..95f49f8
--- /dev/null
+++ b/board/embest/sbc2440ii/lowlevel_init.S
@@ -0,0 +1,219 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw at its.tudelft.nl) and
+ *                     Jan-Derk Bakker (J.D.Bakker at its.tudelft.nl)
+ *
+ * Modified for the Samsung SMDK2410 by
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * Modified for the friendly-arm SBC-2410X by
+ * (C) Copyright 2005
+ * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
+ *
+ * Modified for the Embest SBC2440-II by
+ * (C) Copyright 2009
+ * Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt@fearnside-systems.co.uk>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+/*
+ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
+ *
+ * Copyright (C) 2002 Samsung Electronics SW.LEE  <hitchcar@sec.samsung.com>
+ */
+
+#define BWSCON		0x48000000
+
+#define DW8		(0x0)
+#define DW16		(0x1)
+#define DW32		(0x2)
+#define WAIT		(0x1 << 2)
+#define UBLB		(0x1 << 3)
+
+#define B1_BWSCON	(DW16)
+#define B2_BWSCON	(DW16)
+#define B3_BWSCON	(DW16 + WAIT + UBLB)
+#define B4_BWSCON	(DW16)
+#define B5_BWSCON	(DW16)
+#define B6_BWSCON	(DW32)
+#define B7_BWSCON	(DW32)
+#define BWSCON_VAL	((B1_BWSCON <<  4) + (B2_BWSCON <<  8) + \
+			(B3_BWSCON << 12) + (B4_BWSCON << 16) + \
+			(B5_BWSCON << 20) + (B6_BWSCON << 24) + \
+			(B7_BWSCON << 28))
+
+#define B0_TACS		0x0
+#define B0_TCOS		0x0
+#define B0_TACC		0x7
+#define B0_TCOH		0x0
+#define B0_TAH		0x0
+#define B0_TACP		0x0
+#define B0_PMC		0x0
+#define BANKCON0_VAL	((B0_TACS << 13) + (B0_TCOS << 11) + (B0_TACC <<  8) + \
+			(B0_TCOH <<  6) + (B0_TAH  <<  4) + (B0_TACP <<  2) + \
+			B0_PMC)
+
+#define B1_TACS		0x0
+#define B1_TCOS		0x0
+#define B1_TACC		0x7
+#define B1_TCOH		0x0
+#define B1_TAH		0x0
+#define B1_TACP		0x0
+#define B1_PMC		0x0
+#define BANKCON1_VAL	((B1_TACS << 13) + (B1_TCOS << 11) + (B1_TACC <<  8) + \
+			(B1_TCOH <<   6) + (B1_TAH  <<  4) + (B1_TACP <<  2) + \
+			B1_PMC)
+
+#define B2_TACS		0x0
+#define B2_TCOS		0x0
+#define B2_TACC		0x7
+#define B2_TCOH		0x0
+#define B2_TAH		0x0
+#define B2_TACP		0x0
+#define B2_PMC		0x0
+#define BANKCON2_VAL	((B2_TACS << 13) + (B2_TCOS << 11) + (B2_TACC << 8) + \
+			(B2_TCOH <<  6) + (B2_TAH  <<  4) + (B2_TACP << 2) + \
+			B2_PMC)
+
+#define B3_TACS		0x0	/* 0clk */
+#define B3_TCOS		0x3	/* 4clk */
+#define B3_TACC		0x7	/* 14clk */
+#define B3_TCOH		0x1	/* 1clk */
+#define B3_TAH		0x3	/* 4clk */
+#define B3_TACP		0x3	/* 6clk */
+#define B3_PMC		0x0	/* 16data */
+#define BANKCON3_VAL	((B3_TACS << 13) + (B3_TCOS << 11) + (B3_TACC << 8) + \
+			(B3_TCOH <<  6) + (B3_TAH  <<  4) + (B3_TACP << 2) + \
+			B3_PMC)
+
+#define B4_TACS		0x0
+#define B4_TCOS		0x0
+#define B4_TACC		0x7
+#define B4_TCOH		0x0
+#define B4_TAH		0x0
+#define B4_TACP		0x0
+#define B4_PMC		0x0
+#define BANKCON4_VAL	((B4_TACS << 13) + (B4_TCOS << 11) + (B4_TACC << 8) + \
+			(B4_TCOH <<  6) + (B4_TAH  <<  4) + (B4_TACP << 2) + \
+			B4_PMC)
+
+#define B5_TACS		0x0
+#define B5_TCOS		0x0
+#define B5_TACC		0x7
+#define B5_TCOH		0x0
+#define B5_TAH		0x0
+#define B5_TACP		0x0
+#define B5_PMC		0x0
+#define BANKCON5_VAL	((B5_TACS << 13) + (B5_TCOS << 11) + (B5_TACC << 8) + \
+			(B5_TCOH <<  6) + (B5_TAH  <<  4) + (B5_TACP << 2) + \
+			B5_PMC)
+
+#define B6_MT		0x3	/* SDRAM */
+#define B6_TRCD		0x2
+#define B6_SCAN		0x1	/* 9bit */
+#define BANKCON6_VAL	((B6_MT << 15) + (B6_TRCD << 2) + B6_SCAN)
+
+#define B7_MT		0x3	/* SDRAM */
+#define B7_TRCD		0x2	/* 4clk */
+#define B7_SCAN		0x1	/* 9bit */
+#define BANKCON7_VAL	((B7_MT << 15) + (B7_TRCD << 2) + B7_SCAN)
+
+/* REFRESH parameter */
+#define REFEN		0x1	/* Refresh enable */
+#define TREFMD		0x0	/* CBR(CAS before RAS)/Auto refresh */
+#define TRP		0x0	/* 2clk */
+#define TRC		0x3	/* 7clk */
+#define TCHR		0x2	/* 3clk */
+#define REFCNT		1259
+#define REFRESH_VAL	((REFEN << 23) + (TREFMD << 22) + (TRP << 20) + \
+			(TRC   << 18) + (TCHR   << 16) + REFCNT)
+
+/* BANKSIZE parameter */
+#define BURST_EN	1	/* Enable burst mode */
+#define SCKE_EN		1	/* Enable SDRAM power-down mode */
+#define SCLK_EN		1	/* SCLK is active only during the access */
+#define BK67MAP		2	/* 128M/128M */
+#define BANKSIZE_VAL	((BURST_EN << 7) + (SCKE_EN << 5) + \
+			(SCLK_EN  << 4) + BK67MAP)
+
+/* MRSRB6 parameter */
+#define WBL6		0	/* Burst */
+#define TM6		0	/* Modem register set */
+#define CL6		3	/* Latency is 3 clocks */
+#define BT6		0	/* Sequential */
+#define BL6		0
+#define MRSRB6_VAL	((WBL6 << 9) + (TM6 << 7) + (CL6 << 4) + \
+			(BT6  << 3) + BL6)
+
+/* MRSRB7 parameter */
+#define WBL7		0	/* Burst */
+#define TM7		0	/* Modem register set */
+#define CL7		3	/* Latency is 3 clocks */
+#define BT7		0	/* Sequential */
+#define BL7		0
+#define MRSRB7_VAL	((WBL7 << 9) + (TM7 << 7) + (CL7 << 4) + \
+			(BT7 << 3) + BL7)
+
+/**************************************/
+
+_TEXT_BASE:
+	.word TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+	/* memory control configuration */
+	/* make r0 relative the current location so that it */
+	/* reads SMRDATA out of FLASH rather than memory ! */
+	ldr	r0, =SMRDATA
+	ldr	r1, _TEXT_BASE
+	sub	r0, r0, r1
+	ldr	r1, =BWSCON /* Bus Width Status Controller */
+	add	r2, r0, #13*4
+0:
+	ldr	r3, [r0], #4
+	str	r3, [r1], #4
+	cmp	r2, r0
+	bne	0b
+
+	/* everything is fine now */
+	mov	pc, lr
+
+	.ltorg
+/* the literal pools origin */
+
+SMRDATA:
+	.word	BWSCON_VAL
+	.word	BANKCON0_VAL
+	.word	BANKCON1_VAL
+	.word	BANKCON2_VAL
+	.word	BANKCON3_VAL
+	.word	BANKCON4_VAL
+	.word	BANKCON5_VAL
+	.word	BANKCON6_VAL
+	.word	BANKCON7_VAL
+	.word	REFRESH_VAL
+	.word	BANKSIZE_VAL
+	.word	MRSRB6_VAL
+	.word	MRSRB7_VAL
diff --git a/board/embest/sbc2440ii/sbc2440ii.c b/board/embest/sbc2440ii/sbc2440ii.c
new file mode 100644
index 0000000..7c793e9
--- /dev/null
+++ b/board/embest/sbc2440ii/sbc2440ii.c
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2005
+ * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
+ *
+ * Modified for the Embest SBC2440-II by
+ * (C) Copyright 2009
+ * Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt@fearnside-systems.co.uk>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <s3c2440.h>
+#include <asm/io.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+static inline void pll_settle_delay(unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+			  "subs %0, %1, #1\n" "bne 1b" :
+			  "=r" (loops) : "0"(loops));
+}
+
+int board_init(void)
+{
+	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+	struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
+
+	/* to reduce PLL lock time, adjust the LOCKTIME register */
+	writel(0xFFFFFFFF, &clk_power->LOCKTIME);
+
+	/* configure UPLL */
+	writel((CONFIG_SYS_U_MDIV << 12) + (CONFIG_SYS_U_PDIV << 4) +
+	       CONFIG_SYS_U_SDIV, &clk_power->UPLLCON);
+
+	/* some delay between UPLL and MPLL */
+	pll_settle_delay(8000);
+
+	/* configure MPLL */
+	writel((CONFIG_SYS_M_MDIV << 12) + (CONFIG_SYS_M_PDIV << 4) +
+	       CONFIG_SYS_M_SDIV, &clk_power->MPLLCON);
+
+	/* configure the GPIO */
+	writel(CONFIG_SYS_GPACON,   &gpio->GPACON);
+	writel(CONFIG_SYS_GPBCON,   &gpio->GPBCON);
+	writel(CONFIG_SYS_GPBUP,    &gpio->GPBUP);
+	writel(CONFIG_SYS_GPBDAT,   &gpio->GPBDAT);
+	writel(CONFIG_SYS_GPCCON,   &gpio->GPCCON);
+	writel(CONFIG_SYS_GPCUP,    &gpio->GPCUP);
+	writel(CONFIG_SYS_GPDCON,   &gpio->GPDCON);
+	writel(CONFIG_SYS_GPDUP,    &gpio->GPDUP);
+	writel(CONFIG_SYS_GPECON,   &gpio->GPECON);
+	writel(CONFIG_SYS_GPEUP,    &gpio->GPEUP);
+	writel(CONFIG_SYS_GPFCON,   &gpio->GPFCON);
+	writel(CONFIG_SYS_GPFUP,    &gpio->GPFUP);
+	writel(CONFIG_SYS_GPGCON,   &gpio->GPGCON);
+	writel(CONFIG_SYS_GPGUP,    &gpio->GPGUP);
+	writel(CONFIG_SYS_GPHCON,   &gpio->GPHCON);
+	writel(CONFIG_SYS_GPHUP,    &gpio->GPHUP);
+	writel(CONFIG_SYS_GPJCON,   &gpio->GPJCON);
+	writel(CONFIG_SYS_GPJUP,    &gpio->GPJUP);
+	writel(CONFIG_SYS_EXTINT0,  &gpio->EXTINT0);
+	writel(CONFIG_SYS_EXTINT1,  &gpio->EXTINT1);
+	writel(CONFIG_SYS_EXTINT2,  &gpio->EXTINT2);
+	writel(CONFIG_SYS_EINTMASK, &gpio->EINTMASK);
+
+	/* arch number of SBC2440-II Board */
+	gd->bd->bi_arch_number = MACH_TYPE_SBC2440II;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_CS8900
+	rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/cpu/arm920t/s3c24x0/timer.c b/cpu/arm920t/s3c24x0/timer.c
index 2ee1518..bbe4c07 100644
--- a/cpu/arm920t/s3c24x0/timer.c
+++ b/cpu/arm920t/s3c24x0/timer.c
@@ -180,6 +180,7 @@ ulong get_tbclk(void)
 #if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB)
 	tbclk = timer_load_val * 100;
 #elif defined(CONFIG_SBC2410X)  || \
+      defined(CONFIG_SBC2440II) || \
       defined(CONFIG_SMDK2410)  || \
       defined(CONFIG_VCMA9)
 	tbclk = CONFIG_SYS_HZ;
diff --git a/include/configs/sbc2440ii.h b/include/configs/sbc2440ii.h
new file mode 100644
index 0000000..7ac36cf
--- /dev/null
+++ b/include/configs/sbc2440ii.h
@@ -0,0 +1,254 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Gary Jennejohn <gj@denx.de>
+ * David Mueller <d.mueller@elsoft.ch>
+ *
+ * Modified for the friendly-arm SBC-2410X by
+ * (C) Copyright 2005
+ * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
+ *
+ * Modified for the Embest SBC2440-II by
+ * (C) Copyright 2009
+ * Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt@fearnside-systems.co.uk>
+ *
+ * Configuation settings for the friendly-arm SBC-2410X board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_IDENT_STRING	" for Embest SBC2440-II"
+
+/* If we are developing, we might want to start armboot from ram
+   so we MUST NOT initialize critical regs like mem-timing ... */
+#undef CONFIG_SKIP_LOWLEVEL_INIT	/* undef for developing */
+
+/* High Level Configuration Options (easy to change) */
+#define CONFIG_ARM920T		1 /* This is an ARM920T Core		*/
+#define CONFIG_S3C24X0		1 /* in a SAMSUNG S3C24X0 type of SoC	*/
+#define CONFIG_S3C2440		1 /* specifically, a SAMSUNG S3C2440 SoC*/
+#define CONFIG_SBC2440II	1 /* on an Embest SBC-2440-II Board	*/
+#define CONFIG_DO_ARCH_PRE_LOWLEVEL_INIT
+
+/* input clock of PLL - the SBC2440-II has 12MHz input clock */
+#define CONFIG_SYS_CLK_FREQ	12000000
+
+/* The PLL values for MPLL = 400MHz, UPLL = 48MHz
+   The clock frequency ratios are set to 1:4:8 ie:
+	PCLK = 50MHz
+	HCLK = 100MHz
+	FCLK = 400MHz
+ */
+/* The MPLL values. */
+#define CONFIG_SYS_M_MDIV	0x5C
+#define CONFIG_SYS_M_PDIV	1
+#define CONFIG_SYS_M_SDIV	1
+
+/* The UPLL values. */
+#define CONFIG_SYS_U_MDIV	0x38
+#define CONFIG_SYS_U_PDIV	2
+#define CONFIG_SYS_U_SDIV	2
+
+/* We don't need the MMU or interrupts. */
+#undef USE_920T_MMU
+#undef CONFIG_USE_IRQ
+
+/* The GPIO configuration */
+#define CONFIG_SYS_GPACON	0x007FFFFF
+#define CONFIG_SYS_GPBCON	0x00055555
+#define CONFIG_SYS_GPBUP	0x000007FF
+#define CONFIG_SYS_GPBDAT	0x000001C0	/* Switch on LED1. */
+#define CONFIG_SYS_GPCCON	0xAAAAAAAA
+#define CONFIG_SYS_GPCUP	0x0000FFFF
+#define CONFIG_SYS_GPDCON	0xAAAAAAAA
+#define CONFIG_SYS_GPDUP	0x0000FFFF
+#define CONFIG_SYS_GPECON	0xAAAAA800
+#define CONFIG_SYS_GPEUP	0x00001FFF
+#define CONFIG_SYS_GPFCON	0x000055AA
+#define CONFIG_SYS_GPFUP	0x000000FF
+#define CONFIG_SYS_GPGCON	0xFD95FFBA
+#define CONFIG_SYS_GPGUP	0x0000FFFF
+#define CONFIG_SYS_GPHCON	0x0002FAAA
+#define CONFIG_SYS_GPHUP	0x000007FF
+#define CONFIG_SYS_GPJCON	0x02FAAAAA
+#define CONFIG_SYS_GPJUP	0x00001FFF
+#define CONFIG_SYS_EXTINT0	0x22222222
+#define CONFIG_SYS_EXTINT1	0x22222222
+#define CONFIG_SYS_EXTINT2	0x22222222
+#define CONFIG_SYS_EINTMASK	0x00FFFFF0
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_CS8900		1 /* we have a CS8900 on-board */
+#define CONFIG_CS8900_BASE	0x19000300
+#define CONFIG_CS8900_BUS16	1 /* the Linux driver does accesses as shorts */
+
+/* Serial console configuration */
+#define CONFIG_S3C24X0_SERIAL
+#define CONFIG_SERIAL1	1	/* we use SERIAL 1 on SBC2440-II */
+#define CONFIG_BAUDRATE	115200
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* RTC */
+#define CONFIG_RTC_S3C24X0	1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Command line configuration. */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+#define CONFIG_JFFS2_NAND
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_JFFS2
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT	"nand0=sbc2440-II-nand"
+#define MTDPARTS_DEFAULT \
+	"mtdparts=sbc2440-II-nand:2m(kernel),62m(rootfs)"
+#define CONFIG_EXTRA_ENV_SETTINGS	"autostart=yes"
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS \
+"noinitrd root=/dev/mtdblock1 rootfstype=jffs2 init=/linuxrc console=ttySAC0"
+#define CONFIG_LOADADDR		30008000
+#define CONFIG_BOOTCOMMAND	"nboot 30008000 0 0"
+
+/* kgdb settings */
+#if defined(CONFIG_CMD_KGDB)
+	#define CONFIG_KGDB_BAUDRATE	115200
+	#define CONFIG_KGDB_SER_INDEX	1
+#endif
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP	/* undef to save memory  */
+#define CONFIG_SYS_PROMPT	"[ SBC2440-II ]# "
+#define CONFIG_SYS_CBSIZE	256
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_MEMTEST_START	0x30000000
+#define CONFIG_SYS_MEMTEST_END		0x33F00000
+#undef CONFIG_SYS_CLKS_IN_HZ	/* everything, incl board info, in Hz */
+#define CONFIG_SYS_HZ	1000
+
+/* Stack sizes */
+#define CONFIG_STACKSIZE		(128*1024)  /* regular stack */
+#ifdef CONFIG_USE_IRQ
+	#define CONFIG_STACKSIZE_IRQ	(4*1024)    /* IRQ stack */
+	#define CONFIG_STACKSIZE_FIQ	(4*1024)    /* FIQ stack */
+#endif
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS	1          /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x30000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
+#define CONFIG_SYS_FLASH_BASE	PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LOAD_ADDR	0x33000000  /* default load address */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/* FLASH and environment and organization */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SIZE		0x10000 /* Total Size of Environment Sector */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* max number of memory banks */
+#define PHYS_FLASH_SIZE			0x00200000 /* 2MB */
+#define CONFIG_SYS_MAX_FLASH_SECT	(35)
+#define CONFIG_ENV_ADDR \
+	(CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE - CONFIG_ENV_SIZE)
+
+/* FLASH driver setup */
+#define CONFIG_SYS_FLASH_CFI			1
+#define CONFIG_FLASH_CFI_DRIVER			1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(20*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(20*CONFIG_SYS_HZ)
+
+/* NAND flash settings */
+#if defined(CONFIG_CMD_NAND)
+	#define CONFIG_NAND_S3C2410
+	#define CONFIG_SYS_NAND_BASE		0x4e00000c
+	#define CONFIG_SYS_MAX_NAND_DEVICE	1
+	#define SECTORSIZE			512
+	#define CONFIG_S3C2410_NAND_HWECC
+	#define CONFIG_SYS_NAND_LARGEPAGE
+	#define CONFIG_SYS_NAND_TACLS	0
+	#define CONFIG_SYS_NAND_TWRPH0	3
+	#define CONFIG_SYS_NAND_TWRPH1	1
+#endif
+
+/* Kernel boot argument config. */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_TAG
+
+/* USB settings */
+#define CONFIG_USB_STORAGE			1
+#define CONFIG_CMD_USB				1
+#define CONFIG_USB_OHCI_NEW			1
+#define CONFIG_DOS_PARTITION			1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x49000000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"sbc2440-II"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	1
+#define CONFIG_USB_STORAGE			1
+#define CONFIG_CMD_FAT				1
+
+/*-----------------------------------------------------------------------
+ * Enable network
+ */
+#define CONFIG_NET_MULTI
+
+/* Other settings. */
+#define CONFIG_SYS_64BIT_VSPRINTF
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_CMDLINE_EDITING
+#ifdef CONFIG_CMDLINE_EDITING
+	#undef CONFIG_AUTO_COMPLETE
+#else
+	#define CONFIG_AUTO_COMPLETE
+#endif
+
+#endif /* __CONFIG_H */
-- 
1.6.0.6