From: kevin.morfitt at fearnside-systems.co.uk <kevin.morfitt@fearnside-systems.co.uk>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH ARM v2] Clean-up of s3c24x0 header files
Date: Wed, 04 Nov 2009 08:49:31 +0000 [thread overview]
Message-ID: <4AF1401B.2080701@fearnside-systems.co.uk> (raw)
Cleans up the s3c24x0 header files:
s4c24x0.h: removes the use of 'volatile' from the S3C24X0_REG8,
S3C24X0_REG16 and S3C24X0_REG32 register typedef's. Registers are always
accessed using the IO accessor functions which cast the register address
as 'volatile' anyway so it isn't required here.
s3c2400.h and s3c2410.h: insert a blank line between the static inline
functions
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
---
v2 changes: remove the S3C24X0_REG8, S3C24X0_REG16 and S3C24X0_REG32
register typedef's from s3c24x0.h, s3c2400.h, s3c2410.h and vcma9.h
board/mpl/vcma9/vcma9.h | 14 +-
include/asm-arm/arch-s3c24x0/s3c2400.h | 16 +
include/asm-arm/arch-s3c24x0/s3c2410.h | 17 +
include/asm-arm/arch-s3c24x0/s3c24x0.h | 904 ++++++++++++++++----------------
4 files changed, 490 insertions(+), 461 deletions(-)
diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h
index 9f32808..2c4305c 100644
--- a/board/mpl/vcma9/vcma9.h
+++ b/board/mpl/vcma9/vcma9.h
@@ -118,13 +118,13 @@ static inline u32 NF_Read_ECC(void)
/* VCMA9 PLD regsiters */
typedef struct {
- S3C24X0_REG8 ID;
- S3C24X0_REG8 NIC;
- S3C24X0_REG8 CAN;
- S3C24X0_REG8 MISC;
- S3C24X0_REG8 GPCD;
- S3C24X0_REG8 BOARD;
- S3C24X0_REG8 SDRAM;
+ u8 ID;
+ u8 NIC;
+ u8 CAN;
+ u8 MISC;
+ u8 GPCD;
+ u8 BOARD;
+ u8 SDRAM;
} /*__attribute__((__packed__))*/ VCMA9_PLD;
#define VCMA9_PLD_BASE 0x2C000100
diff --git a/include/asm-arm/arch-s3c24x0/s3c2400.h b/include/asm-arm/arch-s3c24x0/s3c2400.h
index 26bd4e4..2678be1 100644
--- a/include/asm-arm/arch-s3c24x0/s3c2400.h
+++ b/include/asm-arm/arch-s3c24x0/s3c2400.h
@@ -67,67 +67,83 @@ static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
{
return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
}
+
static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
{
return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
}
+
static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
{
return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
}
+
static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
{
return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
}
+
static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
{
return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
}
+
static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
{
return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
}
+
static inline struct s3c24x0_uart
*s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
{
return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
}
+
static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
{
return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
}
+
static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
{
return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
}
+
static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
{
return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
}
+
static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
{
return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
}
+
static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
{
return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
}
+
static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
{
return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
}
+
static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
{
return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
}
+
static inline struct s3c2400_adc *s3c2400_get_base_adc(void)
{
return (struct s3c2400_adc *)S3C24X0_ADC_BASE;
}
+
static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
{
return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
}
+
static inline struct s3c2400_mmc *s3c2400_get_base_mmc(void)
{
return (struct s3c2400_mmc *)S3C2400_MMC_BASE;
diff --git a/include/asm-arm/arch-s3c24x0/s3c2410.h b/include/asm-arm/arch-s3c24x0/s3c2410.h
index be2e76e..0543fe1 100644
--- a/include/asm-arm/arch-s3c24x0/s3c2410.h
+++ b/include/asm-arm/arch-s3c24x0/s3c2410.h
@@ -73,71 +73,88 @@ static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
{
return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
}
+
static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
{
return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
}
+
static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
{
return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
}
+
static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
{
return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
}
+
static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
{
return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
}
+
static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
{
return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
}
+
static inline struct s3c2410_nand *s3c2410_get_base_nand(void)
{
return (struct s3c2410_nand *)S3C2410_NAND_BASE;
}
+
static inline struct s3c24x0_uart
*s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
{
return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
}
+
static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
{
return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
}
+
static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
{
return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
}
+
static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
{
return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
}
+
static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
{
return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
}
+
static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
{
return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
}
+
static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
{
return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
}
+
static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
{
return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
}
+
static inline struct s3c2410_adc *s3c2410_get_base_adc(void)
{
return (struct s3c2410_adc *)S3C2410_ADC_BASE;
}
+
static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
{
return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
}
+
static inline struct s3c2410_sdi *s3c2410_get_base_sdi(void)
{
return (struct s3c2410_sdi *)S3C2410_SDI_BASE;
diff --git a/include/asm-arm/arch-s3c24x0/s3c24x0.h b/include/asm-arm/arch-s3c24x0/s3c24x0.h
index 56a551a..15f53dd 100644
--- a/include/asm-arm/arch-s3c24x0/s3c24x0.h
+++ b/include/asm-arm/arch-s3c24x0/s3c24x0.h
@@ -31,84 +31,80 @@
#ifndef __S3C24X0_H__
#define __S3C24X0_H__
-typedef volatile u8 S3C24X0_REG8;
-typedef volatile u16 S3C24X0_REG16;
-typedef volatile u32 S3C24X0_REG32;
-
/* Memory controller (see manual chapter 5) */
struct s3c24x0_memctl {
- S3C24X0_REG32 BWSCON;
- S3C24X0_REG32 BANKCON[8];
- S3C24X0_REG32 REFRESH;
- S3C24X0_REG32 BANKSIZE;
- S3C24X0_REG32 MRSRB6;
- S3C24X0_REG32 MRSRB7;
+ u32 BWSCON;
+ u32 BANKCON[8];
+ u32 REFRESH;
+ u32 BANKSIZE;
+ u32 MRSRB6;
+ u32 MRSRB7;
};
/* USB HOST (see manual chapter 12) */
struct s3c24x0_usb_host {
- S3C24X0_REG32 HcRevision;
- S3C24X0_REG32 HcControl;
- S3C24X0_REG32 HcCommonStatus;
- S3C24X0_REG32 HcInterruptStatus;
- S3C24X0_REG32 HcInterruptEnable;
- S3C24X0_REG32 HcInterruptDisable;
- S3C24X0_REG32 HcHCCA;
- S3C24X0_REG32 HcPeriodCuttendED;
- S3C24X0_REG32 HcControlHeadED;
- S3C24X0_REG32 HcControlCurrentED;
- S3C24X0_REG32 HcBulkHeadED;
- S3C24X0_REG32 HcBuldCurrentED;
- S3C24X0_REG32 HcDoneHead;
- S3C24X0_REG32 HcRmInterval;
- S3C24X0_REG32 HcFmRemaining;
- S3C24X0_REG32 HcFmNumber;
- S3C24X0_REG32 HcPeriodicStart;
- S3C24X0_REG32 HcLSThreshold;
- S3C24X0_REG32 HcRhDescriptorA;
- S3C24X0_REG32 HcRhDescriptorB;
- S3C24X0_REG32 HcRhStatus;
- S3C24X0_REG32 HcRhPortStatus1;
- S3C24X0_REG32 HcRhPortStatus2;
+ u32 HcRevision;
+ u32 HcControl;
+ u32 HcCommonStatus;
+ u32 HcInterruptStatus;
+ u32 HcInterruptEnable;
+ u32 HcInterruptDisable;
+ u32 HcHCCA;
+ u32 HcPeriodCuttendED;
+ u32 HcControlHeadED;
+ u32 HcControlCurrentED;
+ u32 HcBulkHeadED;
+ u32 HcBuldCurrentED;
+ u32 HcDoneHead;
+ u32 HcRmInterval;
+ u32 HcFmRemaining;
+ u32 HcFmNumber;
+ u32 HcPeriodicStart;
+ u32 HcLSThreshold;
+ u32 HcRhDescriptorA;
+ u32 HcRhDescriptorB;
+ u32 HcRhStatus;
+ u32 HcRhPortStatus1;
+ u32 HcRhPortStatus2;
};
/* INTERRUPT (see manual chapter 14) */
struct s3c24x0_interrupt {
- S3C24X0_REG32 SRCPND;
- S3C24X0_REG32 INTMOD;
- S3C24X0_REG32 INTMSK;
- S3C24X0_REG32 PRIORITY;
- S3C24X0_REG32 INTPND;
- S3C24X0_REG32 INTOFFSET;
+ u32 SRCPND;
+ u32 INTMOD;
+ u32 INTMSK;
+ u32 PRIORITY;
+ u32 INTPND;
+ u32 INTOFFSET;
#ifdef CONFIG_S3C2410
- S3C24X0_REG32 SUBSRCPND;
- S3C24X0_REG32 INTSUBMSK;
+ u32 SUBSRCPND;
+ u32 INTSUBMSK;
#endif
};
/* DMAS (see manual chapter 8) */
struct s3c24x0_dma {
- S3C24X0_REG32 DISRC;
+ u32 DISRC;
#ifdef CONFIG_S3C2410
- S3C24X0_REG32 DISRCC;
+ u32 DISRCC;
#endif
- S3C24X0_REG32 DIDST;
+ u32 DIDST;
#ifdef CONFIG_S3C2410
- S3C24X0_REG32 DIDSTC;
+ u32 DIDSTC;
#endif
- S3C24X0_REG32 DCON;
- S3C24X0_REG32 DSTAT;
- S3C24X0_REG32 DCSRC;
- S3C24X0_REG32 DCDST;
- S3C24X0_REG32 DMASKTRIG;
+ u32 DCON;
+ u32 DSTAT;
+ u32 DCSRC;
+ u32 DCDST;
+ u32 DMASKTRIG;
#ifdef CONFIG_S3C2400
- S3C24X0_REG32 res[1];
+ u32 res[1];
#endif
#ifdef CONFIG_S3C2410
- S3C24X0_REG32 res[7];
+ u32 res[7];
#endif
};
@@ -120,201 +116,201 @@ struct s3c24x0_dmas {
/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
/* (see S3C2410 manual chapter 7) */
struct s3c24x0_clock_power {
- S3C24X0_REG32 LOCKTIME;
- S3C24X0_REG32 MPLLCON;
- S3C24X0_REG32 UPLLCON;
- S3C24X0_REG32 CLKCON;
- S3C24X0_REG32 CLKSLOW;
- S3C24X0_REG32 CLKDIVN;
+ u32 LOCKTIME;
+ u32 MPLLCON;
+ u32 UPLLCON;
+ u32 CLKCON;
+ u32 CLKSLOW;
+ u32 CLKDIVN;
};
/* LCD CONTROLLER (see manual chapter 15) */
struct s3c24x0_lcd {
- S3C24X0_REG32 LCDCON1;
- S3C24X0_REG32 LCDCON2;
- S3C24X0_REG32 LCDCON3;
- S3C24X0_REG32 LCDCON4;
- S3C24X0_REG32 LCDCON5;
- S3C24X0_REG32 LCDSADDR1;
- S3C24X0_REG32 LCDSADDR2;
- S3C24X0_REG32 LCDSADDR3;
- S3C24X0_REG32 REDLUT;
- S3C24X0_REG32 GREENLUT;
- S3C24X0_REG32 BLUELUT;
- S3C24X0_REG32 res[8];
- S3C24X0_REG32 DITHMODE;
- S3C24X0_REG32 TPAL;
+ u32 LCDCON1;
+ u32 LCDCON2;
+ u32 LCDCON3;
+ u32 LCDCON4;
+ u32 LCDCON5;
+ u32 LCDSADDR1;
+ u32 LCDSADDR2;
+ u32 LCDSADDR3;
+ u32 REDLUT;
+ u32 GREENLUT;
+ u32 BLUELUT;
+ u32 res[8];
+ u32 DITHMODE;
+ u32 TPAL;
#ifdef CONFIG_S3C2410
- S3C24X0_REG32 LCDINTPND;
- S3C24X0_REG32 LCDSRCPND;
- S3C24X0_REG32 LCDINTMSK;
- S3C24X0_REG32 LPCSEL;
+ u32 LCDINTPND;
+ u32 LCDSRCPND;
+ u32 LCDINTMSK;
+ u32 LPCSEL;
#endif
};
/* NAND FLASH (see S3C2410 manual chapter 6) */
struct s3c2410_nand {
- S3C24X0_REG32 NFCONF;
- S3C24X0_REG32 NFCMD;
- S3C24X0_REG32 NFADDR;
- S3C24X0_REG32 NFDATA;
- S3C24X0_REG32 NFSTAT;
- S3C24X0_REG32 NFECC;
+ u32 NFCONF;
+ u32 NFCMD;
+ u32 NFADDR;
+ u32 NFDATA;
+ u32 NFSTAT;
+ u32 NFECC;
};
/* UART (see manual chapter 11) */
struct s3c24x0_uart {
- S3C24X0_REG32 ULCON;
- S3C24X0_REG32 UCON;
- S3C24X0_REG32 UFCON;
- S3C24X0_REG32 UMCON;
- S3C24X0_REG32 UTRSTAT;
- S3C24X0_REG32 UERSTAT;
- S3C24X0_REG32 UFSTAT;
- S3C24X0_REG32 UMSTAT;
+ u32 ULCON;
+ u32 UCON;
+ u32 UFCON;
+ u32 UMCON;
+ u32 UTRSTAT;
+ u32 UERSTAT;
+ u32 UFSTAT;
+ u32 UMSTAT;
#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 UTXH;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 URXH;
+ u8 res1[3];
+ u8 UTXH;
+ u8 res2[3];
+ u8 URXH;
#else /* Little Endian */
- S3C24X0_REG8 UTXH;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 URXH;
- S3C24X0_REG8 res2[3];
+ u8 UTXH;
+ u8 res1[3];
+ u8 URXH;
+ u8 res2[3];
#endif
- S3C24X0_REG32 UBRDIV;
+ u32 UBRDIV;
};
/* PWM TIMER (see manual chapter 10) */
struct s3c24x0_timer {
- S3C24X0_REG32 TCNTB;
- S3C24X0_REG32 TCMPB;
- S3C24X0_REG32 TCNTO;
+ u32 TCNTB;
+ u32 TCMPB;
+ u32 TCNTO;
};
struct s3c24x0_timers {
- S3C24X0_REG32 TCFG0;
- S3C24X0_REG32 TCFG1;
- S3C24X0_REG32 TCON;
+ u32 TCFG0;
+ u32 TCFG1;
+ u32 TCON;
struct s3c24x0_timer ch[4];
- S3C24X0_REG32 TCNTB4;
- S3C24X0_REG32 TCNTO4;
+ u32 TCNTB4;
+ u32 TCNTO4;
};
/* USB DEVICE (see manual chapter 13) */
struct s3c24x0_usb_dev_fifos {
#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res[3];
- S3C24X0_REG8 EP_FIFO_REG;
+ u8 res[3];
+ u8 EP_FIFO_REG;
#else /* little endian */
- S3C24X0_REG8 EP_FIFO_REG;
- S3C24X0_REG8 res[3];
+ u8 EP_FIFO_REG;
+ u8 res[3];
#endif
};
struct s3c24x0_usb_dev_dmas {
#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 EP_DMA_CON;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 EP_DMA_UNIT;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 EP_DMA_FIFO;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 EP_DMA_TTC_L;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 EP_DMA_TTC_M;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 EP_DMA_TTC_H;
+ u8 res1[3];
+ u8 EP_DMA_CON;
+ u8 res2[3];
+ u8 EP_DMA_UNIT;
+ u8 res3[3];
+ u8 EP_DMA_FIFO;
+ u8 res4[3];
+ u8 EP_DMA_TTC_L;
+ u8 res5[3];
+ u8 EP_DMA_TTC_M;
+ u8 res6[3];
+ u8 EP_DMA_TTC_H;
#else /* little endian */
- S3C24X0_REG8 EP_DMA_CON;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 EP_DMA_UNIT;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 EP_DMA_FIFO;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 EP_DMA_TTC_L;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 EP_DMA_TTC_M;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 EP_DMA_TTC_H;
- S3C24X0_REG8 res6[3];
+ u8 EP_DMA_CON;
+ u8 res1[3];
+ u8 EP_DMA_UNIT;
+ u8 res2[3];
+ u8 EP_DMA_FIFO;
+ u8 res3[3];
+ u8 EP_DMA_TTC_L;
+ u8 res4[3];
+ u8 EP_DMA_TTC_M;
+ u8 res5[3];
+ u8 EP_DMA_TTC_H;
+ u8 res6[3];
#endif
};
struct s3c24x0_usb_device {
#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 FUNC_ADDR_REG;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 PWR_REG;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 EP_INT_REG;
- S3C24X0_REG8 res4[15];
- S3C24X0_REG8 USB_INT_REG;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 EP_INT_EN_REG;
- S3C24X0_REG8 res6[15];
- S3C24X0_REG8 USB_INT_EN_REG;
- S3C24X0_REG8 res7[3];
- S3C24X0_REG8 FRAME_NUM1_REG;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG8 FRAME_NUM2_REG;
- S3C24X0_REG8 res9[3];
- S3C24X0_REG8 INDEX_REG;
- S3C24X0_REG8 res10[7];
- S3C24X0_REG8 MAXP_REG;
- S3C24X0_REG8 res11[3];
- S3C24X0_REG8 EP0_CSR_IN_CSR1_REG;
- S3C24X0_REG8 res12[3];
- S3C24X0_REG8 IN_CSR2_REG;
- S3C24X0_REG8 res13[7];
- S3C24X0_REG8 OUT_CSR1_REG;
- S3C24X0_REG8 res14[3];
- S3C24X0_REG8 OUT_CSR2_REG;
- S3C24X0_REG8 res15[3];
- S3C24X0_REG8 OUT_FIFO_CNT1_REG;
- S3C24X0_REG8 res16[3];
- S3C24X0_REG8 OUT_FIFO_CNT2_REG;
+ u8 res1[3];
+ u8 FUNC_ADDR_REG;
+ u8 res2[3];
+ u8 PWR_REG;
+ u8 res3[3];
+ u8 EP_INT_REG;
+ u8 res4[15];
+ u8 USB_INT_REG;
+ u8 res5[3];
+ u8 EP_INT_EN_REG;
+ u8 res6[15];
+ u8 USB_INT_EN_REG;
+ u8 res7[3];
+ u8 FRAME_NUM1_REG;
+ u8 res8[3];
+ u8 FRAME_NUM2_REG;
+ u8 res9[3];
+ u8 INDEX_REG;
+ u8 res10[7];
+ u8 MAXP_REG;
+ u8 res11[3];
+ u8 EP0_CSR_IN_CSR1_REG;
+ u8 res12[3];
+ u8 IN_CSR2_REG;
+ u8 res13[7];
+ u8 OUT_CSR1_REG;
+ u8 res14[3];
+ u8 OUT_CSR2_REG;
+ u8 res15[3];
+ u8 OUT_FIFO_CNT1_REG;
+ u8 res16[3];
+ u8 OUT_FIFO_CNT2_REG;
#else /* little endian */
- S3C24X0_REG8 FUNC_ADDR_REG;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 PWR_REG;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 EP_INT_REG;
- S3C24X0_REG8 res3[15];
- S3C24X0_REG8 USB_INT_REG;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 EP_INT_EN_REG;
- S3C24X0_REG8 res5[15];
- S3C24X0_REG8 USB_INT_EN_REG;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 FRAME_NUM1_REG;
- S3C24X0_REG8 res7[3];
- S3C24X0_REG8 FRAME_NUM2_REG;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG8 INDEX_REG;
- S3C24X0_REG8 res9[7];
- S3C24X0_REG8 MAXP_REG;
- S3C24X0_REG8 res10[7];
- S3C24X0_REG8 EP0_CSR_IN_CSR1_REG;
- S3C24X0_REG8 res11[3];
- S3C24X0_REG8 IN_CSR2_REG;
- S3C24X0_REG8 res12[3];
- S3C24X0_REG8 OUT_CSR1_REG;
- S3C24X0_REG8 res13[7];
- S3C24X0_REG8 OUT_CSR2_REG;
- S3C24X0_REG8 res14[3];
- S3C24X0_REG8 OUT_FIFO_CNT1_REG;
- S3C24X0_REG8 res15[3];
- S3C24X0_REG8 OUT_FIFO_CNT2_REG;
- S3C24X0_REG8 res16[3];
+ u8 FUNC_ADDR_REG;
+ u8 res1[3];
+ u8 PWR_REG;
+ u8 res2[3];
+ u8 EP_INT_REG;
+ u8 res3[15];
+ u8 USB_INT_REG;
+ u8 res4[3];
+ u8 EP_INT_EN_REG;
+ u8 res5[15];
+ u8 USB_INT_EN_REG;
+ u8 res6[3];
+ u8 FRAME_NUM1_REG;
+ u8 res7[3];
+ u8 FRAME_NUM2_REG;
+ u8 res8[3];
+ u8 INDEX_REG;
+ u8 res9[7];
+ u8 MAXP_REG;
+ u8 res10[7];
+ u8 EP0_CSR_IN_CSR1_REG;
+ u8 res11[3];
+ u8 IN_CSR2_REG;
+ u8 res12[3];
+ u8 OUT_CSR1_REG;
+ u8 res13[7];
+ u8 OUT_CSR2_REG;
+ u8 res14[3];
+ u8 OUT_FIFO_CNT1_REG;
+ u8 res15[3];
+ u8 OUT_FIFO_CNT2_REG;
+ u8 res16[3];
#endif /* __BIG_ENDIAN */
struct s3c24x0_usb_dev_fifos fifo[5];
struct s3c24x0_usb_dev_dmas dma[5];
@@ -323,45 +319,45 @@ struct s3c24x0_usb_device {
/* WATCH DOG TIMER (see manual chapter 18) */
struct s3c24x0_watchdog {
- S3C24X0_REG32 WTCON;
- S3C24X0_REG32 WTDAT;
- S3C24X0_REG32 WTCNT;
+ u32 WTCON;
+ u32 WTDAT;
+ u32 WTCNT;
};
/* IIC (see manual chapter 20) */
struct s3c24x0_i2c {
- S3C24X0_REG32 IICCON;
- S3C24X0_REG32 IICSTAT;
- S3C24X0_REG32 IICADD;
- S3C24X0_REG32 IICDS;
+ u32 IICCON;
+ u32 IICSTAT;
+ u32 IICADD;
+ u32 IICDS;
};
/* IIS (see manual chapter 21) */
struct s3c24x0_i2s {
#ifdef __BIG_ENDIAN
- S3C24X0_REG16 res1;
- S3C24X0_REG16 IISCON;
- S3C24X0_REG16 res2;
- S3C24X0_REG16 IISMOD;
- S3C24X0_REG16 res3;
- S3C24X0_REG16 IISPSR;
- S3C24X0_REG16 res4;
- S3C24X0_REG16 IISFCON;
- S3C24X0_REG16 res5;
- S3C24X0_REG16 IISFIFO;
+ u16 res1;
+ u16 IISCON;
+ u16 res2;
+ u16 IISMOD;
+ u16 res3;
+ u16 IISPSR;
+ u16 res4;
+ u16 IISFCON;
+ u16 res5;
+ u16 IISFIFO;
#else /* little endian */
- S3C24X0_REG16 IISCON;
- S3C24X0_REG16 res1;
- S3C24X0_REG16 IISMOD;
- S3C24X0_REG16 res2;
- S3C24X0_REG16 IISPSR;
- S3C24X0_REG16 res3;
- S3C24X0_REG16 IISFCON;
- S3C24X0_REG16 res4;
- S3C24X0_REG16 IISFIFO;
- S3C24X0_REG16 res5;
+ u16 IISCON;
+ u16 res1;
+ u16 IISMOD;
+ u16 res2;
+ u16 IISPSR;
+ u16 res3;
+ u16 IISFCON;
+ u16 res4;
+ u16 IISFIFO;
+ u16 res5;
#endif
};
@@ -369,87 +365,87 @@ struct s3c24x0_i2s {
/* I/O PORT (see manual chapter 9) */
struct s3c24x0_gpio {
#ifdef CONFIG_S3C2400
- S3C24X0_REG32 PACON;
- S3C24X0_REG32 PADAT;
+ u32 PACON;
+ u32 PADAT;
- S3C24X0_REG32 PBCON;
- S3C24X0_REG32 PBDAT;
- S3C24X0_REG32 PBUP;
+ u32 PBCON;
+ u32 PBDAT;
+ u32 PBUP;
- S3C24X0_REG32 PCCON;
- S3C24X0_REG32 PCDAT;
- S3C24X0_REG32 PCUP;
+ u32 PCCON;
+ u32 PCDAT;
+ u32 PCUP;
- S3C24X0_REG32 PDCON;
- S3C24X0_REG32 PDDAT;
- S3C24X0_REG32 PDUP;
+ u32 PDCON;
+ u32 PDDAT;
+ u32 PDUP;
- S3C24X0_REG32 PECON;
- S3C24X0_REG32 PEDAT;
- S3C24X0_REG32 PEUP;
+ u32 PECON;
+ u32 PEDAT;
+ u32 PEUP;
- S3C24X0_REG32 PFCON;
- S3C24X0_REG32 PFDAT;
- S3C24X0_REG32 PFUP;
+ u32 PFCON;
+ u32 PFDAT;
+ u32 PFUP;
- S3C24X0_REG32 PGCON;
- S3C24X0_REG32 PGDAT;
- S3C24X0_REG32 PGUP;
+ u32 PGCON;
+ u32 PGDAT;
+ u32 PGUP;
- S3C24X0_REG32 OPENCR;
+ u32 OPENCR;
- S3C24X0_REG32 MISCCR;
- S3C24X0_REG32 EXTINT;
+ u32 MISCCR;
+ u32 EXTINT;
#endif
#ifdef CONFIG_S3C2410
- S3C24X0_REG32 GPACON;
- S3C24X0_REG32 GPADAT;
- S3C24X0_REG32 res1[2];
- S3C24X0_REG32 GPBCON;
- S3C24X0_REG32 GPBDAT;
- S3C24X0_REG32 GPBUP;
- S3C24X0_REG32 res2;
- S3C24X0_REG32 GPCCON;
- S3C24X0_REG32 GPCDAT;
- S3C24X0_REG32 GPCUP;
- S3C24X0_REG32 res3;
- S3C24X0_REG32 GPDCON;
- S3C24X0_REG32 GPDDAT;
- S3C24X0_REG32 GPDUP;
- S3C24X0_REG32 res4;
- S3C24X0_REG32 GPECON;
- S3C24X0_REG32 GPEDAT;
- S3C24X0_REG32 GPEUP;
- S3C24X0_REG32 res5;
- S3C24X0_REG32 GPFCON;
- S3C24X0_REG32 GPFDAT;
- S3C24X0_REG32 GPFUP;
- S3C24X0_REG32 res6;
- S3C24X0_REG32 GPGCON;
- S3C24X0_REG32 GPGDAT;
- S3C24X0_REG32 GPGUP;
- S3C24X0_REG32 res7;
- S3C24X0_REG32 GPHCON;
- S3C24X0_REG32 GPHDAT;
- S3C24X0_REG32 GPHUP;
- S3C24X0_REG32 res8;
-
- S3C24X0_REG32 MISCCR;
- S3C24X0_REG32 DCLKCON;
- S3C24X0_REG32 EXTINT0;
- S3C24X0_REG32 EXTINT1;
- S3C24X0_REG32 EXTINT2;
- S3C24X0_REG32 EINTFLT0;
- S3C24X0_REG32 EINTFLT1;
- S3C24X0_REG32 EINTFLT2;
- S3C24X0_REG32 EINTFLT3;
- S3C24X0_REG32 EINTMASK;
- S3C24X0_REG32 EINTPEND;
- S3C24X0_REG32 GSTATUS0;
- S3C24X0_REG32 GSTATUS1;
- S3C24X0_REG32 GSTATUS2;
- S3C24X0_REG32 GSTATUS3;
- S3C24X0_REG32 GSTATUS4;
+ u32 GPACON;
+ u32 GPADAT;
+ u32 res1[2];
+ u32 GPBCON;
+ u32 GPBDAT;
+ u32 GPBUP;
+ u32 res2;
+ u32 GPCCON;
+ u32 GPCDAT;
+ u32 GPCUP;
+ u32 res3;
+ u32 GPDCON;
+ u32 GPDDAT;
+ u32 GPDUP;
+ u32 res4;
+ u32 GPECON;
+ u32 GPEDAT;
+ u32 GPEUP;
+ u32 res5;
+ u32 GPFCON;
+ u32 GPFDAT;
+ u32 GPFUP;
+ u32 res6;
+ u32 GPGCON;
+ u32 GPGDAT;
+ u32 GPGUP;
+ u32 res7;
+ u32 GPHCON;
+ u32 GPHDAT;
+ u32 GPHUP;
+ u32 res8;
+
+ u32 MISCCR;
+ u32 DCLKCON;
+ u32 EXTINT0;
+ u32 EXTINT1;
+ u32 EXTINT2;
+ u32 EINTFLT0;
+ u32 EINTFLT1;
+ u32 EINTFLT2;
+ u32 EINTFLT3;
+ u32 EINTMASK;
+ u32 EINTPEND;
+ u32 GSTATUS0;
+ u32 GSTATUS1;
+ u32 GSTATUS2;
+ u32 GSTATUS3;
+ u32 GSTATUS4;
#endif
};
@@ -457,112 +453,112 @@ struct s3c24x0_gpio {
/* RTC (see manual chapter 17) */
struct s3c24x0_rtc {
#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res1[67];
- S3C24X0_REG8 RTCCON;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 TICNT;
- S3C24X0_REG8 res3[11];
- S3C24X0_REG8 RTCALM;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 ALMSEC;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 ALMMIN;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 ALMHOUR;
- S3C24X0_REG8 res7[3];
- S3C24X0_REG8 ALMDATE;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG8 ALMMON;
- S3C24X0_REG8 res9[3];
- S3C24X0_REG8 ALMYEAR;
- S3C24X0_REG8 res10[3];
- S3C24X0_REG8 RTCRST;
- S3C24X0_REG8 res11[3];
- S3C24X0_REG8 BCDSEC;
- S3C24X0_REG8 res12[3];
- S3C24X0_REG8 BCDMIN;
- S3C24X0_REG8 res13[3];
- S3C24X0_REG8 BCDHOUR;
- S3C24X0_REG8 res14[3];
- S3C24X0_REG8 BCDDATE;
- S3C24X0_REG8 res15[3];
- S3C24X0_REG8 BCDDAY;
- S3C24X0_REG8 res16[3];
- S3C24X0_REG8 BCDMON;
- S3C24X0_REG8 res17[3];
- S3C24X0_REG8 BCDYEAR;
+ u8 res1[67];
+ u8 RTCCON;
+ u8 res2[3];
+ u8 TICNT;
+ u8 res3[11];
+ u8 RTCALM;
+ u8 res4[3];
+ u8 ALMSEC;
+ u8 res5[3];
+ u8 ALMMIN;
+ u8 res6[3];
+ u8 ALMHOUR;
+ u8 res7[3];
+ u8 ALMDATE;
+ u8 res8[3];
+ u8 ALMMON;
+ u8 res9[3];
+ u8 ALMYEAR;
+ u8 res10[3];
+ u8 RTCRST;
+ u8 res11[3];
+ u8 BCDSEC;
+ u8 res12[3];
+ u8 BCDMIN;
+ u8 res13[3];
+ u8 BCDHOUR;
+ u8 res14[3];
+ u8 BCDDATE;
+ u8 res15[3];
+ u8 BCDDAY;
+ u8 res16[3];
+ u8 BCDMON;
+ u8 res17[3];
+ u8 BCDYEAR;
#else /* little endian */
- S3C24X0_REG8 res0[64];
- S3C24X0_REG8 RTCCON;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 TICNT;
- S3C24X0_REG8 res2[11];
- S3C24X0_REG8 RTCALM;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 ALMSEC;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 ALMMIN;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 ALMHOUR;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 ALMDATE;
- S3C24X0_REG8 res7[3];
- S3C24X0_REG8 ALMMON;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG8 ALMYEAR;
- S3C24X0_REG8 res9[3];
- S3C24X0_REG8 RTCRST;
- S3C24X0_REG8 res10[3];
- S3C24X0_REG8 BCDSEC;
- S3C24X0_REG8 res11[3];
- S3C24X0_REG8 BCDMIN;
- S3C24X0_REG8 res12[3];
- S3C24X0_REG8 BCDHOUR;
- S3C24X0_REG8 res13[3];
- S3C24X0_REG8 BCDDATE;
- S3C24X0_REG8 res14[3];
- S3C24X0_REG8 BCDDAY;
- S3C24X0_REG8 res15[3];
- S3C24X0_REG8 BCDMON;
- S3C24X0_REG8 res16[3];
- S3C24X0_REG8 BCDYEAR;
- S3C24X0_REG8 res17[3];
+ u8 res0[64];
+ u8 RTCCON;
+ u8 res1[3];
+ u8 TICNT;
+ u8 res2[11];
+ u8 RTCALM;
+ u8 res3[3];
+ u8 ALMSEC;
+ u8 res4[3];
+ u8 ALMMIN;
+ u8 res5[3];
+ u8 ALMHOUR;
+ u8 res6[3];
+ u8 ALMDATE;
+ u8 res7[3];
+ u8 ALMMON;
+ u8 res8[3];
+ u8 ALMYEAR;
+ u8 res9[3];
+ u8 RTCRST;
+ u8 res10[3];
+ u8 BCDSEC;
+ u8 res11[3];
+ u8 BCDMIN;
+ u8 res12[3];
+ u8 BCDHOUR;
+ u8 res13[3];
+ u8 BCDDATE;
+ u8 res14[3];
+ u8 BCDDAY;
+ u8 res15[3];
+ u8 BCDMON;
+ u8 res16[3];
+ u8 BCDYEAR;
+ u8 res17[3];
#endif
};
/* ADC (see manual chapter 16) */
struct s3c2400_adc {
- S3C24X0_REG32 ADCCON;
- S3C24X0_REG32 ADCDAT;
+ u32 ADCCON;
+ u32 ADCDAT;
};
/* ADC (see manual chapter 16) */
struct s3c2410_adc {
- S3C24X0_REG32 ADCCON;
- S3C24X0_REG32 ADCTSC;
- S3C24X0_REG32 ADCDLY;
- S3C24X0_REG32 ADCDAT0;
- S3C24X0_REG32 ADCDAT1;
+ u32 ADCCON;
+ u32 ADCTSC;
+ u32 ADCDLY;
+ u32 ADCDAT0;
+ u32 ADCDAT1;
};
/* SPI (see manual chapter 22) */
struct s3c24x0_spi_channel {
- S3C24X0_REG8 SPCON;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 SPSTA;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 SPPIN;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 SPPRE;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 SPTDAT;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 SPRDAT;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 res7[16];
+ u8 SPCON;
+ u8 res1[3];
+ u8 SPSTA;
+ u8 res2[3];
+ u8 SPPIN;
+ u8 res3[3];
+ u8 SPPRE;
+ u8 res4[3];
+ u8 SPTDAT;
+ u8 res5[3];
+ u8 SPRDAT;
+ u8 res6[3];
+ u8 res7[16];
};
struct s3c24x0_spi {
@@ -573,84 +569,84 @@ struct s3c24x0_spi {
/* MMC INTERFACE (see S3C2400 manual chapter 19) */
struct s3c2400_mmc {
#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 MMCON;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 MMCRR;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 MMFCON;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 MMSTA;
- S3C24X0_REG16 res5;
- S3C24X0_REG16 MMFSTA;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 MMPRE;
- S3C24X0_REG16 res7;
- S3C24X0_REG16 MMLEN;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG8 MMCR7;
- S3C24X0_REG32 MMRSP[4];
- S3C24X0_REG8 res9[3];
- S3C24X0_REG8 MMCMD0;
- S3C24X0_REG32 MMCMD1;
- S3C24X0_REG16 res10;
- S3C24X0_REG16 MMCR16;
- S3C24X0_REG8 res11[3];
- S3C24X0_REG8 MMDAT;
+ u8 res1[3];
+ u8 MMCON;
+ u8 res2[3];
+ u8 MMCRR;
+ u8 res3[3];
+ u8 MMFCON;
+ u8 res4[3];
+ u8 MMSTA;
+ u16 res5;
+ u16 MMFSTA;
+ u8 res6[3];
+ u8 MMPRE;
+ u16 res7;
+ u16 MMLEN;
+ u8 res8[3];
+ u8 MMCR7;
+ u32 MMRSP[4];
+ u8 res9[3];
+ u8 MMCMD0;
+ u32 MMCMD1;
+ u16 res10;
+ u16 MMCR16;
+ u8 res11[3];
+ u8 MMDAT;
#else
- S3C24X0_REG8 MMCON;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 MMCRR;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 MMFCON;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 MMSTA;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG16 MMFSTA;
- S3C24X0_REG16 res5;
- S3C24X0_REG8 MMPRE;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG16 MMLEN;
- S3C24X0_REG16 res7;
- S3C24X0_REG8 MMCR7;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG32 MMRSP[4];
- S3C24X0_REG8 MMCMD0;
- S3C24X0_REG8 res9[3];
- S3C24X0_REG32 MMCMD1;
- S3C24X0_REG16 MMCR16;
- S3C24X0_REG16 res10;
- S3C24X0_REG8 MMDAT;
- S3C24X0_REG8 res11[3];
+ u8 MMCON;
+ u8 res1[3];
+ u8 MMCRR;
+ u8 res2[3];
+ u8 MMFCON;
+ u8 res3[3];
+ u8 MMSTA;
+ u8 res4[3];
+ u16 MMFSTA;
+ u16 res5;
+ u8 MMPRE;
+ u8 res6[3];
+ u16 MMLEN;
+ u16 res7;
+ u8 MMCR7;
+ u8 res8[3];
+ u32 MMRSP[4];
+ u8 MMCMD0;
+ u8 res9[3];
+ u32 MMCMD1;
+ u16 MMCR16;
+ u16 res10;
+ u8 MMDAT;
+ u8 res11[3];
#endif
};
/* SD INTERFACE (see S3C2410 manual chapter 19) */
struct s3c2410_sdi {
- S3C24X0_REG32 SDICON;
- S3C24X0_REG32 SDIPRE;
- S3C24X0_REG32 SDICARG;
- S3C24X0_REG32 SDICCON;
- S3C24X0_REG32 SDICSTA;
- S3C24X0_REG32 SDIRSP0;
- S3C24X0_REG32 SDIRSP1;
- S3C24X0_REG32 SDIRSP2;
- S3C24X0_REG32 SDIRSP3;
- S3C24X0_REG32 SDIDTIMER;
- S3C24X0_REG32 SDIBSIZE;
- S3C24X0_REG32 SDIDCON;
- S3C24X0_REG32 SDIDCNT;
- S3C24X0_REG32 SDIDSTA;
- S3C24X0_REG32 SDIFSTA;
+ u32 SDICON;
+ u32 SDIPRE;
+ u32 SDICARG;
+ u32 SDICCON;
+ u32 SDICSTA;
+ u32 SDIRSP0;
+ u32 SDIRSP1;
+ u32 SDIRSP2;
+ u32 SDIRSP3;
+ u32 SDIDTIMER;
+ u32 SDIBSIZE;
+ u32 SDIDCON;
+ u32 SDIDCNT;
+ u32 SDIDSTA;
+ u32 SDIFSTA;
#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res[3];
- S3C24X0_REG8 SDIDAT;
+ u8 res[3];
+ u8 SDIDAT;
#else
- S3C24X0_REG8 SDIDAT;
- S3C24X0_REG8 res[3];
+ u8 SDIDAT;
+ u8 res[3];
#endif
- S3C24X0_REG32 SDIIMSK;
+ u32 SDIIMSK;
};
#endif /*__S3C24X0_H__*/
--
1.6.0.6
next reply other threads:[~2009-11-04 8:49 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-11-04 8:49 kevin.morfitt at fearnside-systems.co.uk [this message]
2009-11-10 2:15 ` [U-Boot] [PATCH ARM v2] Clean-up of s3c24x0 header files Minkyu Kang
2009-11-10 13:06 ` [U-Boot] [PATCH ARM] Add a unified s3c24x0 header file kevin.morfitt at fearnside-systems.co.uk
2009-11-13 7:20 ` Minkyu Kang
2009-11-13 8:54 ` kevin.morfitt at fearnside-systems.co.uk
2009-11-13 9:26 ` Minkyu Kang
2009-11-13 9:36 ` kevin.morfitt at fearnside-systems.co.uk
2009-11-16 7:40 ` Minkyu Kang
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