Re: [Qemu-devel] [PATCH 01/11] S/390 CPU fake emulation

[Carsten Otte <carsteno@de.ibm.com>]

Blue Swirl wrote:
> The translation block (TB) refers to a block of host instructions,
> translated from some block of target instructions under some
> assumptions. The assumptions used when translating (for example, user
> vs supervisor mode in the CPU state) are recorded to TB flags. If the
> CPU state changes, the old TBs with different flags will not be used
> and new TBs will be generated.
Thanks for the explanation, Alex did explain it too on irc.

> Actually Sparc64 address spaces and ASIs are very similar. There are
> nucleus, primary and secondary address spaces (not fully implemented
> yet in QEMU). Instructions can encode the ASI or %asi register can be
> used. Some ASIs are restricted for supervisor or hypervisor modes.
> Sparc32 ASIs are simpler (physical address space extension to 36 bits,
> basically) and for supervisor only.
Oh, I though we were the only odd bird on this one.

> For S/390, I think the TB flags do not need to contain the address
> space control registers if the generated instructions fetch the state
> from CPU state and do not rely on translation time information. If the
> address spaces do not change very often, it may alternatively be
> possible to rely on the CPU state during translation, but then it must
> be ensured that all generated TBs are always flushed when the
> registers change.
Yes, that would work as far as I can tell. The registers change whenever 
$guest decides to schedule a different task, but not on every syscall.

cheers,
Carsten