From: David Daney <ddaney@caviumnetworks.com>
To: Ralf Baechle <ralf@linux-mips.org>,
linux-mips <linux-mips@linux-mips.org>
Subject: [PATCH 0/2] Rearrange MIPS barriers and optimize for Octeon.
Date: Fri, 08 Jan 2010 17:16:29 -0800 [thread overview]
Message-ID: <4B47D8ED.1020006@caviumnetworks.com> (raw)
Locking/atomic performance on Octeon can be improved by using
optimized barrier instructions. The first patch in this set
rearranges and simplifies (at least in my mind) the existing barriers.
Then the second patch adds Octeon specific barriers.
I will reply with the two patches.
David Daney (2):
MIPS: New macro smp_mb__before_llsc.
MIPS: Octeon: Use optimized memory barrier primitives.
arch/mips/Kconfig | 1 -
arch/mips/include/asm/atomic.h | 16 ++++++------
arch/mips/include/asm/barrier.h | 52
+++++++++++++++++++++++++++-----------
arch/mips/include/asm/bitops.h | 8 +++---
arch/mips/include/asm/cmpxchg.h | 10 +++---
arch/mips/include/asm/spinlock.h | 4 +-
arch/mips/include/asm/system.h | 4 +++
7 files changed, 60 insertions(+), 35 deletions(-)
next reply other threads:[~2010-01-09 1:16 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-01-09 1:16 David Daney [this message]
2010-01-09 1:17 ` [PATCH 1/2] MIPS: New macro smp_mb__before_llsc David Daney
2010-01-13 12:32 ` Ralf Baechle
2010-01-09 1:17 ` [PATCH 2/2] MIPS: Octeon: Use optimized memory barrier primitives David Daney
2010-01-13 12:33 ` Ralf Baechle
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