From: Eric Dumazet <eric.dumazet@gmail.com>
To: James Kosin <JKosin@intcomgrp.com>
Cc: linux-kernel@vger.kernel.org, Linux Netdev List <netdev@vger.kernel.org>
Subject: Re: arm: Optimization for ethernet MAC handling at91_ether.c
Date: Tue, 12 Jan 2010 20:24:43 +0100 [thread overview]
Message-ID: <4B4CCC7B.8040609@gmail.com> (raw)
In-Reply-To: <3DBBD805E3BA064A87F551C0E8BD36740289741C@MAILSRV.intcomgrp.com>
Le 12/01/2010 20:03, James Kosin a écrit :
>
> Scratch that. The interrupt doesn't queue up or send another packet directly. So, it wouldn't help on performance here. But, may in other implementations that queue/transmit packets in the ISR. At least in the case where the transmitter is limited to one.
>
It could, at least on SMP. tx completion wakes a blocked sender, while
this cpu continue with RX handling (possibly expensive)
But even on UP, doing tx completion before rx handling allows
a better reuse of skb just freed (and partly present in cpu cache, if available).
Start of IRQ
1) tx completion
-> free a skb
2) rx handling:
-> allocate an skb, kmalloc() reuses previous one, still in cpu cache.
End of IRQ
next prev parent reply other threads:[~2010-01-12 19:24 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-01-12 15:39 arm: Optimization for ethernet MAC handling at91_ether.c James Kosin
2010-01-12 16:35 ` Eric Dumazet
2010-01-12 17:51 ` James Kosin
2010-01-12 18:08 ` Eric Dumazet
2010-01-12 18:42 ` James Kosin
2010-01-12 19:03 ` James Kosin
2010-01-12 19:24 ` Eric Dumazet [this message]
2010-01-12 19:39 ` James Kosin
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