From mboxrd@z Thu Jan 1 00:00:00 1970 From: Brian Walker Date: Sat, 16 Jan 2010 11:27:40 -0500 Subject: [ath9k-devel] trouble with DWA-552 and ath9k In-Reply-To: <19277.32410.462158.258222@gargle.gargle.HOWL> References: <4B2A5FA8.8060905@charter.net> <19242.62265.487757.695747@gargle.gargle.HOWL> <4B2AFC5D.1060001@charter.net> <19243.2224.974537.876295@gargle.gargle.HOWL> <4B39058A.6080108@charter.net> <1262033354.3002.11.camel@mj> <4B391DCB.6010500@charter.net> <1262035725.3002.23.camel@mj> <4B393739.9000601@charter.net> <20091229100250.xle1s7oai8ow08k8-cebfxv@webmail.spamcop.net> <4B3A8F7B.2050106@charter.net> <20091230011624.zygif55zaco8000s-cebfxv@webmail.spamcop.net> <4B436D94.4050304@charter.net> <19270.46529.788691.185819@gargle.gargle.HOWL> <4B489D63.9030305@charter.net> <19273.25018.877385.529083@gargle.gargle.HOWL> <4B4D1F4F.7090106@charter.net> <19277.32410.462158.258222@gargle.gargle.HOWL> Message-ID: <4B51E8FC.9030304@charter.net> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: ath9k-devel@lists.ath9k.org On 01/13/2010 03:04 AM, Sujith wrote: > Brian Walker wrote: > >> Ok! Now I have some debugging information. Here are the ath9k lines from >> dmesg right after boot: >> >> ath9k 0000:00:0a.0: PCI INT A -> Link[LNKC] -> GSI 5 (level, low) -> IRQ 5 >> ath: UNDEFINED -> AWAKE >> ath: serialize_regmode is 0 >> ath: Eeprom VER: 14, REV: 18 >> ath: EEPROM regdomain: 0x10 >> ath: EEPROM indicates we should expect a direct regpair map >> ath: Country alpha2 being used: CO >> ath: Regpair used: 0x10 >> ath: tx DMA: 512 buffers 1 desc/buf >> ath: tx DMA map: f4ca0000 (76320) -> 0 (76320) >> ath: beacon DMA: 4 buffers 1 desc/buf >> ath: beacon DMA map: f4c5d000 (576) -> 0 (576) >> ath: cachelsz 32 rxbufsize 3872 >> ath: rx DMA: 512 buffers 1 desc/buf >> ath: rx DMA map: f4ce0000 (76320) -> 0 (76320) >> phy0: Selected rate control algorithm 'ath9k_rate_control' >> Registered led device: ath9k-phy0::radio >> Registered led device: ath9k-phy0::assoc >> Registered led device: ath9k-phy0::tx >> phy0: Atheros AR9280 Rev:2 mem=0xfa5a0000, irq=5 >> cfg80211: Calling CRDA for country: CO >> cfg80211: Regulatory domain changed to country: CO >> (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp) >> (2402000 KHz - 2472000 KHz @ 40000 KHz), (300 mBi, 2700 mBm) >> (5170000 KHz - 5250000 KHz @ 20000 KHz), (300 mBi, 1700 mBm) >> (5250000 KHz - 5330000 KHz @ 20000 KHz), (300 mBi, 2300 mBm) >> (5735000 KHz - 5835000 KHz @ 20000 KHz), (300 mBi, 3000 mBm) >> cfg80211: Calling CRDA for country: US >> cfg80211: Regulatory domain changed to country: US >> (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp) >> (2402000 KHz - 2472000 KHz @ 40000 KHz), (300 mBi, 2700 mBm) >> (5170000 KHz - 5250000 KHz @ 40000 KHz), (300 mBi, 1700 mBm) >> (5250000 KHz - 5330000 KHz @ 40000 KHz), (300 mBi, 2000 mBm) >> (5490000 KHz - 5600000 KHz @ 40000 KHz), (300 mBi, 2000 mBm) >> (5650000 KHz - 5710000 KHz @ 40000 KHz), (300 mBi, 2000 mBm) >> (5735000 KHz - 5835000 KHz @ 40000 KHz), (300 mBi, 3000 mBm) >> > Initialization is apparently okay - no errors here. > > >> Here is dmesg after doing an "ifconfig wlan0 up": >> >> ath: Starting driver with initial channel: 2412 MHz >> ath: ah->misc_mode 0x4 >> ath: Attach a VIF of type: 2 >> ath: BSS Changed PREAMBLE 0 >> ath: BSS Changed CTS PROT 0 >> ath: Marking phy0 as idle >> ath: timeout (100000 us) on reg 0x7000: 0xffffffff& 0x00000003 != 0x00000000 >> ath: RTC stuck in MAC reset >> ath: Chip reset failed >> > The first HW reset fails as the contents of RTC_RC is weird. > Which probably means that the earlier initialization messed up somewhere, > corrupting the RTC register space - this would be my immediate guess. > > Will take a look. Thanks for the debug log. > > Sujith > Any update? I'd be glad to do further debugging with any code changes. Brian