From: Jens Scharsig <js_at_ng@scharsoft.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 6/9 V3] update at91sam9263ek board to new SoC access
Date: Sat, 23 Jan 2010 12:03:36 +0100 [thread overview]
Message-ID: <4B5AD788.1050304@scharsoft.de> (raw)
* convert at91sam9263ek board to use c stucture SoC access
* demonstates how to use new SoC
Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
---
board/atmel/at91sam9263ek/at91sam9263ek.c | 147 +++++++++++++++--------------
board/atmel/at91sam9263ek/led.c | 9 +-
include/configs/at91sam9263ek.h | 83 ++++++++---------
3 files changed, 119 insertions(+), 120 deletions(-)
diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c
index 0b7065b..43a1aab 100644
--- a/board/atmel/at91sam9263ek/at91sam9263ek.c
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -25,13 +25,13 @@
#include <common.h>
#include <asm/sizes.h>
#include <asm/arch/at91sam9263.h>
-#include <asm/arch/at91sam9263_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <asm/arch/hardware.h>
#include <lcd.h>
@@ -52,33 +52,39 @@ DECLARE_GLOBAL_DATA_PTR;
static void at91sam9263ek_nand_hw_init(void)
{
unsigned long csa;
+ at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE;
+ at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ /* Enable CS3 */
+ csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+ writel(csa, &matrix->csa[0]);
/* Enable CS3 */
- csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
- at91_sys_write(AT91_MATRIX_EBI0CSA,
- csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
/* Configure SMC CS3 for NAND/SmartMedia */
- at91_sys_write(AT91_SMC_SETUP(3),
- AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
- AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
- at91_sys_write(AT91_SMC_PULSE(3),
- AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
- AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
- at91_sys_write(AT91_SMC_CYCLE(3),
- AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
- at91_sys_write(AT91_SMC_MODE(3),
- AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
- AT91_SMC_EXNWMODE_DISABLE |
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
- AT91_SMC_DBW_16 |
+ AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
- AT91_SMC_DBW_8 |
+ AT91_SMC_MODE_DBW_8 |
#endif
- AT91_SMC_TDF_(2));
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[3].mode);
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
- 1 << AT91SAM9263_ID_PIOCDE);
+ writel(1 << AT91SAM9263_ID_PIOA | 1 << AT91SAM9263_ID_PIOCDE,
+ &pmc->pcer);
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
@@ -91,10 +97,12 @@ static void at91sam9263ek_nand_hw_init(void)
#ifdef CONFIG_MACB
static void at91sam9263ek_macb_hw_init(void)
{
- unsigned long rstc;
-
+ unsigned long erstl;
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+ at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE;
/* Enable clock */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
+ writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
/*
* Disable pull-up on:
@@ -104,35 +112,27 @@ static void at91sam9263ek_macb_hw_init(void)
*
* PHY has internal pull-down
*/
- writel(pin_to_mask(AT91_PIN_PC25),
- pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
- writel(pin_to_mask(AT91_PIN_PE25) |
- pin_to_mask(AT91_PIN_PE26),
- pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
- rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
+ writel(AT91_PIN_TO_MASK(25), &pio->pioc.pudr);
+ writel(AT91_PIN_TO_MASK(25) | AT91_PIN_TO_MASK(26), &pio->pioe.pudr);
- /* Need to reset PHY -> 500ms reset */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (AT91_RSTC_ERSTL & (0x0D << 8)) |
- AT91_RSTC_URSTEN);
+ erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+ /* Need to reset PHY -> 500ms reset */
+ writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
+ AT91_RSTC_MR_URSTEN, &rstc->mr);
+ writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
/* Wait for end hardware reset */
- while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
+ while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
+ ;
/* Restore NRST value */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (rstc) |
- AT91_RSTC_URSTEN);
+ writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
/* Re-enable pull-up */
- writel(pin_to_mask(AT91_PIN_PC25),
- pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
- writel(pin_to_mask(AT91_PIN_PE25) |
- pin_to_mask(AT91_PIN_PE26),
- pin_to_controller(AT91_PIN_PE0) + PIO_PUER);
+ writel(AT91_PIN_TO_MASK(25), &pio->pioc.puer);
+ writel(AT91_PIN_TO_MASK(25) | AT91_PIN_TO_MASK(26), &pio->pioe.puer);
at91_macb_hw_init();
}
@@ -158,41 +158,42 @@ vidinfo_t panel_info = {
void lcd_enable(void)
{
- at91_set_gpio_value(AT91_PIN_PA30, 1); /* power up */
+ at91_set_gpio_value(AT91_PORTPIN(A, 30), 1); /* power up */
}
void lcd_disable(void)
{
- at91_set_gpio_value(AT91_PIN_PA30, 0); /* power down */
+ at91_set_gpio_value(AT91_PORTPIN(A, 30), 0); /* power down */
}
static void at91sam9263ek_lcd_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
- at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
- at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
- at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
- at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
- at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
- at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
- at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
- at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
- at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
- at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
- at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
- at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
- at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
- at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
- at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
- at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
- at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
- at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
- at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
- at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
- at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
-
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
-
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PORTPIN(C, 1), 0); /* LCDHSYNC */
+ at91_set_a_periph(AT91_PORTPIN(C, 2), 0); /* LCDDOTCK */
+ at91_set_a_periph(AT91_PORTPIN(C, 3), 0); /* LCDDEN */
+ at91_set_b_periph(AT91_PORTPIN(B, 9), 0); /* LCDCC */
+ at91_set_a_periph(AT91_PORTPIN(C, 6), 0); /* LCDD2 */
+ at91_set_a_periph(AT91_PORTPIN(C, 7), 0); /* LCDD3 */
+ at91_set_a_periph(AT91_PORTPIN(C, 8), 0); /* LCDD4 */
+ at91_set_a_periph(AT91_PORTPIN(C, 9), 0); /* LCDD5 */
+ at91_set_a_periph(AT91_PORTPIN(C, 10), 0); /* LCDD6 */
+ at91_set_a_periph(AT91_PORTPIN(C, 11), 0); /* LCDD7 */
+ at91_set_a_periph(AT91_PORTPIN(C, 14), 0); /* LCDD10 */
+ at91_set_a_periph(AT91_PORTPIN(C, 15), 0); /* LCDD11 */
+ at91_set_a_periph(AT91_PORTPIN(C, 16), 0); /* LCDD12 */
+ at91_set_b_periph(AT91_PORTPIN(C, 12), 0); /* LCDD13 */
+ at91_set_a_periph(AT91_PORTPIN(C, 18), 0); /* LCDD14 */
+ at91_set_a_periph(AT91_PORTPIN(C, 19), 0); /* LCDD15 */
+ at91_set_a_periph(AT91_PORTPIN(C, 22), 0); /* LCDD18 */
+ at91_set_a_periph(AT91_PORTPIN(C, 23), 0); /* LCDD19 */
+ at91_set_a_periph(AT91_PORTPIN(C, 24), 0); /* LCDD20 */
+ at91_set_b_periph(AT91_PORTPIN(C, 17), 0); /* LCDD21 */
+ at91_set_a_periph(AT91_PORTPIN(C, 26), 0); /* LCDD22 */
+ at91_set_a_periph(AT91_PORTPIN(C, 27), 0); /* LCDD23 */
+
+ writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer);
gd->fb_base = AT91SAM9263_SRAM0_BASE;
}
@@ -258,7 +259,7 @@ int board_init(void)
at91sam9263ek_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
- at91_set_gpio_output(AT91_PIN_PE20, 1); /* select spi0 clock */
+ at91_set_gpio_output(AT91_PORTPIN(E, 20), 1); /* select spi0 clock */
at91_spi0_hw_init(1 << 0);
#endif
#ifdef CONFIG_MACB
@@ -297,7 +298,7 @@ int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_MACB
- rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
+ rc = macb_eth_initialize(0, (void *) AT91_EMAC_BASE, 0x00);
#endif
return rc;
}
diff --git a/board/atmel/at91sam9263ek/led.c b/board/atmel/at91sam9263ek/led.c
index 82c5388..e5817df 100644
--- a/board/atmel/at91sam9263ek/led.c
+++ b/board/atmel/at91sam9263ek/led.c
@@ -23,16 +23,19 @@
*/
#include <common.h>
-#include <asm/arch/at91sam9263.h>
+#include <asm/arch/hardware.h>
#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
void coloured_LED_init(void)
{
/* Enable clock */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOB |
- 1 << AT91SAM9263_ID_PIOCDE);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ writel(1 << AT91SAM9263_ID_PIOB | 1 << AT91SAM9263_ID_PIOCDE,
+ &pmc->pcer);
at91_set_gpio_output(CONFIG_RED_LED, 1);
at91_set_gpio_output(CONFIG_GREEN_LED, 1);
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index dc010f2..68e8310 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -27,8 +27,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_AT91_LEGACY
-
/* ARM asynchronous clock */
#define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
#define CONFIG_SYS_HZ 1000
@@ -73,9 +71,9 @@
/* LED */
#define CONFIG_AT91_LED
-#define CONFIG_RED_LED AT91_PIN_PB7 /* this is the power led */
-#define CONFIG_GREEN_LED AT91_PIN_PB8 /* this is the user1 led */
-#define CONFIG_YELLOW_LED AT91_PIN_PC29 /* this is the user2 led */
+#define CONFIG_RED_LED AT91_PORTPIN(B, 7) /* the power led */
+#define CONFIG_GREEN_LED AT91_PORTPIN(B, 8) /* the user1 led */
+#define CONFIG_YELLOW_LED AT91_PORTPIN(C, 29) /* the user2 led */
#define CONFIG_BOOTDELAY 3
@@ -151,39 +149,36 @@
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define MASTER_PLL_MUL 171
#define MASTER_PLL_DIV 14
+#define MASTER_PLL_OUT 3
/* clocks */
#define CONFIG_SYS_MOR_VAL \
- (AT91_PMC_MOSCEN | \
- (255 << 8)) /* Main Oscillator Start-up Time */
-#define CONFIG_SYS_PLLAR_VAL \
- (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
- AT91_PMC_OUT | \
- AT91_PMC_PLLCOUNT | /* PLL Counter */ \
- (2 << 28) | /* PLL Clock Frequency Range */ \
- ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
+ (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
+#define CONFIG_SYS_PLLAR_VAL \
+ (AT91_PMC_PLLAR_29 | \
+ AT91_PMC_PLLxR_OUT(MASTER_PLL_OUT) | \
+ AT91_PMC_PLLxR_PLLCOUNT(63) | \
+ AT91_PMC_PLLxR_MUL(MASTER_PLL_MUL - 1) | \
+ AT91_PMC_PLLxR_DIV(MASTER_PLL_DIV))
/* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_CSS_SLOW | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
+ (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
+ AT91_PMC_MCKR_MDIV_2)
+
/* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_CSS_PLLA | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
+ (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
+ AT91_PMC_MCKR_MDIV_2)
/* define PDC[31:16] as DATA[31:16] */
#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
/* no pull-up for D[31:16] */
#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
-#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
- (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \
- AT91_MATRIX_EBI0_CS1A_SDRAMC)
+#define CONFIG_SYS_MATRIX_EBICSA_VAL \
+ (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
+ AT91_MATRIX_CSA_EBI_CS1A)
/* SDRAM */
/* SDRAMC_MR Mode register */
@@ -225,33 +220,32 @@
#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC0_SETUP0_VAL \
- (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
- AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
-#define CONFIG_SYS_SMC0_PULSE0_VAL \
- (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
- AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
+#define CONFIG_SYS_SMC0_SETUP0_VAL \
+ (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
+ AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
+#define CONFIG_SYS_SMC0_PULSE0_VAL \
+ (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
+ AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
#define CONFIG_SYS_SMC0_CYCLE0_VAL \
- (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
+ (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
#define CONFIG_SYS_SMC0_MODE0_VAL \
- (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
- AT91_SMC_DBW_16 | \
- AT91_SMC_TDFMODE | \
- AT91_SMC_TDF_(6))
+ (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
+ AT91_SMC_MODE_DBW_16 | \
+ AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
/* user reset enable */
#define CONFIG_SYS_RSTC_RMR_VAL \
(AT91_RSTC_KEY | \
- AT91_RSTC_PROCRST | \
- AT91_RSTC_RSTTYP_WAKEUP | \
- AT91_RSTC_RSTTYP_WATCHDOG)
+ AT91_RSTC_MR_URSTEN | \
+ AT91_RSTC_MR_ERSTL(15))
/* Disable Watchdog */
#define CONFIG_SYS_WDTC_WDMR_VAL \
- (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
- AT91_WDT_WDV | \
- AT91_WDT_WDDIS | \
- AT91_WDT_WDD)
+ (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
+ AT91_WDT_MR_WDV(0xfff) | \
+ AT91_WDT_MR_WDDIS | \
+ AT91_WDT_MR_WDD(0xfff))
+
#endif
#else
@@ -268,9 +262,10 @@
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PORTPIN(D, 15)
+#define CONFIG_SYS_NAND_READY_PIN AT91_PORTPIN(A, 22)
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* Ethernet */
next reply other threads:[~2010-01-23 11:03 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-01-23 11:03 Jens Scharsig [this message]
2010-01-31 1:25 ` [U-Boot] [PATCH 6/9 V3] update at91sam9263ek board to new SoC access Tom
2010-01-31 12:12 ` Jens Scharsig
2010-02-03 21:47 ` [U-Boot] [PATCH 6/9 V4] " Jens Scharsig
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=4B5AD788.1050304@scharsoft.de \
--to=js_at_ng@scharsoft.de \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.