[U-Boot] [PATCH 3/3] Add support for EDB93xx boards

[Tom <Tom.Rix@windriver.com>]

Matthias Kaehlcke wrote:
> Added support for the following EDB93xx boards:
> 
> EDB9301
> EDB9302
> EDB9302A
> EDB9307
> EDB9307A
> EDB93012
> EDB9315
> EDB9315A
> 
> Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
> ---
>  MAINTAINERS                  |   10 ++
>  MAKEALL                      |    8 ++
>  Makefile                     |   10 ++
>  board/edb93xx/Makefile       |   50 ++++++++
>  board/edb93xx/config.mk      |   33 +++++
>  board/edb93xx/early_udelay.h |   34 +++++
>  board/edb93xx/edb93xx.c      |  109 +++++++++++++++++
>  board/edb93xx/flash_cfg.c    |   38 ++++++
>  board/edb93xx/pll_cfg.c      |   58 +++++++++
>  board/edb93xx/pll_cfg.h      |   72 +++++++++++
>  board/edb93xx/sdram_cfg.c    |  117 ++++++++++++++++++
>  board/edb93xx/sdram_cfg.h    |  144 ++++++++++++++++++++++
>  include/configs/edb93xx.h    |  273 ++++++++++++++++++++++++++++++++++++++++++
>  13 files changed, 956 insertions(+), 0 deletions(-)
>  create mode 100644 board/edb93xx/Makefile
>  create mode 100644 board/edb93xx/config.mk
>  create mode 100644 board/edb93xx/early_udelay.h
>  create mode 100644 board/edb93xx/edb93xx.c
>  create mode 100644 board/edb93xx/flash_cfg.c
>  create mode 100644 board/edb93xx/pll_cfg.c
>  create mode 100644 board/edb93xx/pll_cfg.h
>  create mode 100644 board/edb93xx/sdram_cfg.c
>  create mode 100644 board/edb93xx/sdram_cfg.h
>  create mode 100644 include/configs/edb93xx.h
> 
<snip>
> --- a/MAKEALL
> +++ b/MAKEALL
> @@ -554,6 +554,14 @@ LIST_ARM9="			\
>  	cp946es			\
>  	cp966			\
>  	da830evm		\
> +	edb9301			\
> +	edb9302			\
> +	edb9302a		\
> +	edb9307			\
> +	edb9307a 		\
ws trailing space

> +	edb9312			\
> +	edb9315			\
> +	edb9315a		\

<snip>

> +
> +int dram_init(void)
> +{
> +	unsigned int *src, *dst;
> +	int i;
> +
> +	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
> +		const ulong bank_size = get_ram_size((long *)bank_addr[i],
> +						MAX_BANK_SIZE);
> +		if (bank_size) {
> +			gd->bd->bi_dram[i].start = bank_addr[i];
> +			gd->bd->bi_dram[i].size = bank_size;
> +		}
> +	}
> +
> +	/* copy exception vectors */
> +	src = (unsigned int *)_armboot_start;
> +
> +#ifdef CONFIG_EDB93XX_SDCS3
> +	dst = (unsigned int *)0x00000000;
> +#else
> +	dst = (unsigned int *)0xc0000000;
> +#endif

This could be reduced to
dst = (unsigned int *)PHYS_SDRAM_1;

> +	memcpy(dst, src, 16 * sizeof(unsigned int));
> +
> +	return 0;
> +}

<snip>

> --- /dev/null
> +++ b/board/edb93xx/pll_cfg.h
> @@ -0,0 +1,72 @@
> +/*
> + * PLL register values for Cirrus edb93xx boards
> + *
> + * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <config.h>
> +#include <asm/arch/ep93xx.h>
> +
> +#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \
> +	defined(CONFIG_EDB9302A)
> +/*
> + * fclk_div: 2, nbyp1: 1, hclk_div: 5, pclk_div: 2
> + * pll1_x1: 294912000.000000, pll1_x2ip: 36864000.000000,
> + * pll1_x2: 331776000.000000, pll1_out: 331776000.000000
> + */
> +#define CLKSET1_VAL	(7 << SYSCON_CLKSET_PLL_X2IPD_SHIFT |      \
> +			8 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT |	   \
> +			19 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT |	   \
> +			1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT |	   \
> +			3 << SYSCON_CLKSET1_HCLK_DIV_SHIFT |	   \
> +			SYSCON_CLKSET1_NBYP1 |			   \
> +			1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)

ws trailing spaces
Other macros have similar issues

> +#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) ||\
> +	defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) ||\
> +	defined(CONFIG_EDB9315A)
> +/*
> + * fclk_div: 2, nbyp1: 1, hclk_div: 4, pclk_div: 2
> + * pll1_x1: 3096576000.000000, pll1_x2ip: 129024000.000000,
> + * pll1_x2: 3999744000.000000, pll1_out: 1999872000.000000
> + */

<snip>

> +static void setup_refresh_timer(void)
> +{
> +	struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
> +
> +	/* Load refresh timer with 10 to issue refresh every 10 cycles */
> +	writel(0x0a, &sdram->refrshtimr);
> +
> +	/*
> +	 * Wait at least 80 clock cycles to provide 8 refresh cycles
> +	 * to all SDRAMs
> +	 */
> +	early_udelay(1);
> +
> +	/*
> +	 * Program refresh timer with normal value
> +	 * We need 8192 refresh cycles every 64ms
> +	 * at 15ns (HCLK >= 66MHz) per cycle:
> +	 * 64ms / 8192 = 7.8125us
> +	 * 7.8125us / 15ns = 520 (0x208)
> +	 */
Good comment!

> +	/*
> +	 * TODO: redboot uses 0x1e0 for the slowest possible device
> +	 * but i don't understand how this value is calculated
> +	 */
> +	writel(0x208, &sdram->refrshtimr);
> +}
> +
> +static void program_mode_registers(void)
> +{
> +	PROGRAM_MODE_REG(0);
> +
It looks like all this macros is doing is reading memory.
Is this correct ?
If so, please add a comment


> +#if (CONFIG_NR_DRAM_BANKS >= 2)
> +	PROGRAM_MODE_REG(1);
> +#endif
> +
> +#if (CONFIG_NR_DRAM_BANKS >= 3)
> +	PROGRAM_MODE_REG(2);
> +#endif
> +
> +#if (CONFIG_NR_DRAM_BANKS == 4)
> +	PROGRAM_MODE_REG(3);
> +#endif
> +}
<snip>

> +#define CONFIG_SYS_MEMTEST_START	0xc0100000
> +#define CONFIG_SYS_MEMTEST_END		0xc1e00000
> +#endif
> +
> +#if defined(CONFIG_EDB93XX_SDCS3)
> +#define CONFIG_SYS_LOAD_ADDR	0x01000000	/* Default load address	*/
> +#elif defined(CONFIG_EDB93XX_SDCS0)
> +#define CONFIG_SYS_LOAD_ADDR	0xc1000000	/* Default load address	*/
> +#endif

This could be reduced to
+#define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x01000000)	/* Default load address	*/

Tom