Re: [PATCH 3/4] MIPS: Add TLBP to uasm.

[Sergei Shtylyov <sshtylyov@mvista.com>]

Hello.

David Daney wrote:

> The soon to follow Read Inhibit/eXecute Inhibit patch needs TLBP
>   

  But you're adding TLBR support, not TLBP?

> support in uasm.
>
> Signed-off-by: David Daney <ddaney@caviumnetworks.com>
> ---
>  arch/mips/include/asm/uasm.h |    1 +
>  arch/mips/mm/uasm.c          |    5 ++++-
>  2 files changed, 5 insertions(+), 1 deletions(-)
>
> diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
> index 3d153ed..b18588b 100644
> --- a/arch/mips/include/asm/uasm.h
> +++ b/arch/mips/include/asm/uasm.h
> @@ -95,6 +95,7 @@ Ip_u2u1u3(_srl);
>  Ip_u3u1u2(_subu);
>  Ip_u2s3u1(_sw);
>  Ip_0(_tlbp);
> +Ip_0(_tlbr);
>  Ip_0(_tlbwi);
>  Ip_0(_tlbwr);
>  Ip_u3u1u2(_xor);
> diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
> index e3ca0f7..8f4f14d 100644
> --- a/arch/mips/mm/uasm.c
> +++ b/arch/mips/mm/uasm.c
> @@ -63,7 +63,8 @@ enum opcode {
>  	insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
>  	insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
>  	insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
> -	insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, insn_dins
> +	insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,
> +	insn_dins
>  };
>  
>  struct insn {
> @@ -128,6 +129,7 @@ static struct insn insn_table[] __cpuinitdata = {
>  	{ insn_subu,  M(spec_op, 0, 0, 0, 0, subu_op),  RS | RT | RD },
>  	{ insn_sw,  M(sw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
>  	{ insn_tlbp,  M(cop0_op, cop_op, 0, 0, 0, tlbp_op),  0 },
> +	{ insn_tlbr,  M(cop0_op, cop_op, 0, 0, 0, tlbr_op),  0 },
>  	{ insn_tlbwi,  M(cop0_op, cop_op, 0, 0, 0, tlbwi_op),  0 },
>  	{ insn_tlbwr,  M(cop0_op, cop_op, 0, 0, 0, tlbwr_op),  0 },
>  	{ insn_xor,  M(spec_op, 0, 0, 0, 0, xor_op),  RS | RT | RD },
> @@ -381,6 +383,7 @@ I_u2u1u3(_srl)
>  I_u3u1u2(_subu)
>  I_u2s3u1(_sw)
>  I_0(_tlbp)
> +I_0(_tlbr)
>  I_0(_tlbwi)
>  I_0(_tlbwr)
>  I_u3u1u2(_xor)
>   

WBR, Sergei