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From: David Daney <ddaney@caviumnetworks.com>
To: Ralf Baechle <ralf@linux-mips.org>,
	linux-mips <linux-mips@linux-mips.org>
Subject: [PATCH 0/6] MIPS Read Inhibit/eXecute Inhibit support (v2).
Date: Wed, 10 Feb 2010 15:08:33 -0800	[thread overview]
Message-ID: <4B733C71.8030304@caviumnetworks.com> (raw)

This patch set adds execute and read inhibit support.  By default glibc
based tool chains will create mappings for data areas of a program and
shared libraries with PROT_EXEC cleared.  With this patch applied, a
SIGSEGV is correctly sent if an attempt is made to execute from data
areas.

The first three patch just make a few tweaks in preperation for the
main body of the patch in 4/6.  The last two turn on the feature for
some Octeon CPUs.

I will reply with the six patches.

David Daney (6):
   MIPS: Use 64-bit stores to c0_entrylo on 64-bit kernels.
   MIPS: Add accessor functions and bit definitions for c0_PageGrain
   MIPS: Add TLBR and ROTR to uasm.
   MIPS: Implement Read Inhibit/eXecute Inhibit
   MIPS: Give Octeon+ CPUs their own cputype.
   MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUs

  arch/mips/include/asm/cpu-features.h               |    3 +
  arch/mips/include/asm/cpu.h                        |    2 +-
  .../asm/mach-cavium-octeon/cpu-feature-overrides.h |    3 +
  arch/mips/include/asm/mipsregs.h                   |   11 ++
  arch/mips/include/asm/pgtable-32.h                 |    4 +-
  arch/mips/include/asm/pgtable-64.h                 |    4 +-
  arch/mips/include/asm/pgtable-bits.h               |  105 ++++++++++--
  arch/mips/include/asm/pgtable.h                    |   26 ++-
  arch/mips/include/asm/uasm.h                       |    4 +
  arch/mips/kernel/cpu-probe.c                       |    6 +-
  arch/mips/mm/c-octeon.c                            |    7 +-
  arch/mips/mm/cache.c                               |   53 ++++--
  arch/mips/mm/fault.c                               |   27 +++-
  arch/mips/mm/init.c                                |    2 +-
  arch/mips/mm/tlb-r4k.c                             |   19 ++-
  arch/mips/mm/tlbex.c                               |  183 
++++++++++++++++----
  arch/mips/mm/uasm.c                                |    9 +-
  17 files changed, 375 insertions(+), 93 deletions(-)

             reply	other threads:[~2010-02-10 23:08 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-02-10 23:08 David Daney [this message]
2010-02-10 23:12 ` [PATCH 1/6] MIPS: Use 64-bit stores to c0_entrylo on 64-bit kernels David Daney
2010-02-10 23:12 ` [PATCH 2/6] MIPS: Add accessor functions and bit definitions for c0_PageGrain David Daney
2010-02-10 23:12 ` [PATCH 3/6] MIPS: Add TLBR and ROTR to uasm David Daney
2010-02-10 23:12 ` [PATCH 4/6] MIPS: Implement Read Inhibit/eXecute Inhibit David Daney
2010-02-14 20:16   ` Manuel Lauss
2010-02-15  1:17     ` David Daney
2010-02-15  2:08       ` David Daney
2010-02-15 17:34         ` Manuel Lauss
2010-02-15 17:38           ` David Daney
2010-02-10 23:12 ` [PATCH 5/6] MIPS: Give Octeon+ CPUs their own cputype David Daney
2010-02-10 23:12 ` [PATCH 6/6] MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUs David Daney
2010-02-10 23:56 ` [PATCH 0/6] MIPS Read Inhibit/eXecute Inhibit support (v2) Ralf Baechle
2010-02-11  0:53   ` David Daney

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