From mboxrd@z Thu Jan 1 00:00:00 1970 From: Wei Huang Subject: Re: AMD extended migration CPU masks: why only on CPU 0? Date: Fri, 19 Feb 2010 14:27:12 -0600 Message-ID: <4B7EF420.1010200@amd.com> References: <20100216174352.GJ368@whitby.uk.xensource.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="------------090600070402060902030101" Return-path: In-Reply-To: <20100216174352.GJ368@whitby.uk.xensource.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Tim Deegan Cc: "xen-devel@lists.xensource.com" List-Id: xen-devel@lists.xenproject.org --------------090600070402060902030101 Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit Tim, The (extended) CPUID mask MSRs are associated with each core. They need to be updated on each core if migration happens across CPUs. Changset 18402 does update the MSRs for each core. But printk() only happens on core 0. If you move printk() statements below wrmsr(), you will see it been called on each core. It is hard to justify which way is better. I attach the patch anyway, in case Keir or you want it for xen-unstable. Signed-off-by: Wei Huang Best, -Wei Tim Deegan wrote: > Hi Travis, > > In c/s 18402, the CPUID masks are only set once, on CPU 0. Can you > explain why this doesn't have to happen on every core, or at least every > socket? The white paper doesn't discuss it. > > Cheers, > > Tim. > > --------------090600070402060902030101 Content-Type: text/x-patch; name="amd_cpu_feature_mask_printk.patch" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="amd_cpu_feature_mask_printk.patch" diff -r 83a6621b91bf xen/arch/x86/cpu/amd.c --- a/xen/arch/x86/cpu/amd.c Wed Feb 10 09:20:56 2010 +0000 +++ b/xen/arch/x86/cpu/amd.c Fri Feb 19 14:22:04 2010 -0600 @@ -131,10 +131,6 @@ } status = set_mask; - printk("Writing CPUID feature mask ECX:EDX -> %08Xh:%08Xh\n", - feat_ecx, feat_edx); - printk("Writing CPUID extended feature mask ECX:EDX -> %08Xh:%08Xh\n", - extfeat_ecx, extfeat_edx); setmask: /* FIXME check if processor supports CPUID masking */ @@ -146,6 +142,10 @@ wrmsr_amd(MSR_K8_FEATURE_MASK, feat_edx, feat_ecx); wrmsr_amd(MSR_K8_EXT_FEATURE_MASK, extfeat_edx, extfeat_ecx); } + printk("Writing CPUID feature mask ECX:EDX -> %08Xh:%08Xh\n", + feat_ecx, feat_edx); + printk("Writing CPUID extended feature mask ECX:EDX -> %08Xh:%08Xh\n", + extfeat_ecx, extfeat_edx); } /* --------------090600070402060902030101 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel --------------090600070402060902030101--