From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Hellstrom Subject: Re: [RFC] drm/ttm: add pool wc/uc page allocator Date: Wed, 03 Mar 2010 14:23:23 +0100 Message-ID: <4B8E62CB.5060407@shipmail.org> References: <1267392603-8915-1-git-send-email-suokkos@gmail.com> <548cdfc21003011432o3c6103dbj3e9d29d8f42609c3@mail.gmail.com> <1267527383.5157.10892.camel@thor.local> <4B8CFB1B.1020806@shipmail.org> <548cdfc21003030413h9594bb1hb543d998844fdd1e@mail.gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.sourceforge.net To: Luca Barbieri Cc: Jerome Glisse , =?ISO-8859-1?Q?Michel_D=E4nzer?= , dri-devel@lists.sourceforge.net List-Id: dri-devel@lists.freedesktop.org Luca Barbieri wrote: > While this is almost surely a good idea, note that userspace caching > and suballocation substantially improves Mesa performance even on PCIe > systems. > This is mostly due to the unavoidable overhead of kernel calls and > pagetable modifications, > as well as the avoidable linear search the > kernel currently does to find an empty space in virtual address space, > ^^^ Luca, I've never seen this show up high on a profile (yet). Do you see that with Nouveau? I used to have an rb-tree implementation of drm_mm_xxx lying around, but I didn't use it because I didn't have a case where it showed up? > as well as the additional pagefaults. > > Userspace caching and suballocation mean that you just have to compute > a pointer, which you cannot beat with any kernel-space solution. This > is also the way glibc allocates normal memory with malloc(), for the > same reason. > ------------------------------------------------------------------------------ Download Intel® Parallel Studio Eval Try the new software tools for yourself. Speed compiling, find bugs proactively, and fine-tune applications for parallel performance. See why Intel Parallel Studio got high marks during beta. http://p.sf.net/sfu/intel-sw-dev --