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Date: Thu, 25 Mar 2010 09:29:18 -0700
From: Richard Henderson <rth@twiddle.net>
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Subject: Re: [Qemu-devel] [PATCH 09/10] target-alpha:
	Implement	load-locked/store-conditional properly.
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To: Nathan Froyd <froydnj@codesourcery.com>
Cc: qemu-devel@nongnu.org, aurelien@aurel32.net

On 03/25/2010 09:06 AM, Nathan Froyd wrote:
>> Mips doesn't even pretend to be atomic.
> 
> It pretends just as much as ppc and arm.  See translate.c:OP_ST_ATOMIC.

No it doesn't.  Look at HELPER_ST_ATOMIC:

        tmp = do_##ld_insn(arg2, mem_idx);                                    \
        if (tmp == env->llval) {                                              \
            do_##st_insn(arg2, arg1, mem_idx);                                \
            return 1;                                                         \

> (The remaining cases are tricky things, like cross-process locks.)  I
> think--though Paul would remember better than I--that the stop-the-world
> approach might have been taken due to a desire to continue compiling
> with gcc < 4.1.  I don't know how much of a desdirata that still is.

Even that wouldn't be an issue if we move the cmpxchg into TCG.

I'll put this at the end of the enhancement queue...


r~