[U-Boot] [PATCH 4/4] s5p6442: Add support SMDK6442 board

[Joonyoung Shim <jy0922.shim@samsung.com>]

This patch adds the new board SMDK6442 that uses s5p6442 SoC.

Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
---
 MAKEALL                                |    1 +
 Makefile                               |    3 +
 board/samsung/smdk6442/Makefile        |   55 +++++++
 board/samsung/smdk6442/config.mk       |    6 +
 board/samsung/smdk6442/lowlevel_init.S |  202 ++++++++++++++++++++++++++
 board/samsung/smdk6442/mem_setup.S     |  175 +++++++++++++++++++++++
 board/samsung/smdk6442/onenand.c       |   41 ++++++
 board/samsung/smdk6442/smdk6442.c      |   54 +++++++
 include/configs/smdk6442.h             |  242 ++++++++++++++++++++++++++++++++
 9 files changed, 779 insertions(+), 0 deletions(-)
 create mode 100644 board/samsung/smdk6442/Makefile
 create mode 100644 board/samsung/smdk6442/config.mk
 create mode 100644 board/samsung/smdk6442/lowlevel_init.S
 create mode 100644 board/samsung/smdk6442/mem_setup.S
 create mode 100644 board/samsung/smdk6442/onenand.c
 create mode 100644 board/samsung/smdk6442/smdk6442.c
 create mode 100644 include/configs/smdk6442.h

diff --git a/MAKEALL b/MAKEALL
index beacb5f..e3a0b49 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -626,6 +626,7 @@ LIST_ARM11="			\
 	mx31pdk_nand		\
 	qong			\
 	smdk6400		\
+	smdk6442		\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index d801e25..eeebb13 100644
--- a/Makefile
+++ b/Makefile
@@ -3329,6 +3329,9 @@ smdk6400_config	:	unconfig
 	fi
 	@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
 
+smdk6442_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm1176 smdk6442 samsung s5p64xx
+
 #========================================================================
 # i386
 #========================================================================
diff --git a/board/samsung/smdk6442/Makefile b/board/samsung/smdk6442/Makefile
new file mode 100644
index 0000000..9700ffb
--- /dev/null
+++ b/board/samsung/smdk6442/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	:= smdk6442.o
+COBJS-$(CONFIG_SAMSUNG_ONENAND)	+= onenand.o
+SOBJS	:= lowlevel_init.o
+
+SRCS    := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(SOBJS) $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(SOBJS) $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/samsung/smdk6442/config.mk b/board/samsung/smdk6442/config.mk
new file mode 100644
index 0000000..9c39c8a
--- /dev/null
+++ b/board/samsung/smdk6442/config.mk
@@ -0,0 +1,6 @@
+#
+# Copyright (C) 2010 Samsung Elecgtronics
+# Minkyu Kang <mk7.kang@samsung.com>
+#
+
+TEXT_BASE = 0x34800000
diff --git a/board/samsung/smdk6442/lowlevel_init.S b/board/samsung/smdk6442/lowlevel_init.S
new file mode 100644
index 0000000..3b8e368
--- /dev/null
+++ b/board/samsung/smdk6442/lowlevel_init.S
@@ -0,0 +1,202 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/power.h>
+
+/*
+ * Register usages:
+ *
+ * r5 has zero always
+ */
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+	.globl lowlevel_init
+lowlevel_init:
+	mov	r9, lr
+
+	/* r5 has always zero */
+	mov	r5, #0
+
+	ldr	r8, =S5P6442_GPIO_BASE			@0xE0200000
+
+	/* IO retension release */
+	ldr	r0, =S5P6442_OTHERS			@0xE010E000
+	ldr	r1, [r0]
+	ldr	r2, =(1 << 31)				@IO_RET_REL
+	orr	r1, r1, r2
+	str	r1, [r0]
+
+#ifndef CONFIG_ONENAND_IPL
+	/* Disable Watchdog */
+	ldr	r0, =S5P6442_WATCHDOG_BASE		@0xEA200000
+	orr	r0, r0, #0x0
+	str	r5, [r0]
+
+	/* setting SRAM */
+	ldr	r0, =S5P6442_SROMC_BASE			@0xE7000000
+	ldr	r1, =0x9
+	str	r1, [r0]
+#endif
+
+	/* S5P6442 has 3 groups of interrupt sources */
+	ldr	r0, =S5P6442_VIC0_BASE			@0xE4000000
+	add	r1, r0, #0x00100000
+	add	r2, r0, #0x00200000
+
+	/* Disable all interrupts (VIC0, VIC1 and VIC2) */
+	mvn	r3, #0x0
+	str	r3, [r0, #0x14]				@INTENCLEAR
+	str	r3, [r1, #0x14]				@INTENCLEAR
+	str	r3, [r2, #0x14]				@INTENCLEAR
+
+#ifndef CONFIG_ONENAND_IPL
+	/* Set all interrupts as IRQ */
+	str	r5, [r0, #0xc]				@INTSELECT
+	str	r5, [r1, #0xc]				@INTSELECT
+	str	r5, [r2, #0xc]				@INTSELECT
+
+	/* Pending Interrupt Clear */
+	str	r5, [r0, #0xf00]			@INTADDRESS
+	str	r5, [r1, #0xf00]			@INTADDRESS
+	str	r5, [r2, #0xf00]			@INTADDRESS
+#endif
+
+#ifndef CONFIG_ONENAND_IPL
+	/* for UART */
+	bl uart_asm_init
+#endif
+
+#ifdef CONFIG_ONENAND_IPL
+	/* init system clock */
+	bl	system_clock_init
+
+	bl	mem_ctrl_asm_init
+
+	/* OneNAND Sync Read Support at S5PC110 only
+	 * RM[15]       : Sync Read
+	 * BRWL[14:12]  : 7 CLK
+	 * BL[11:9]     : Continuous
+	 * VHF[3]       : Very High Frequency Enable (Over 83MHz)
+	 * HF[2]        : High Frequency Enable (Over 66MHz)
+	 */
+	ldr	r1, =0xE00C
+
+	ldr	r0, =0xB001E442
+	strh	r1, [r0]
+
+	ldr	r0, =0xB0600000
+	str	r1, [r0, #0x100]			@ ONENAND_IF_CTRL
+
+	/* Wakeup support. Don't know if it's going to be used, untested. */
+	ldr	r0, =S5P6442_RST_STAT
+	ldr	r1, [r0]
+	bic	r1, r1, #0xfffffff7
+	cmp	r1, #0x8
+	beq	wakeup_reset
+#endif
+
+1:
+	mov	lr, r9
+	mov	pc, lr
+
+#ifdef CONFIG_ONENAND_IPL
+wakeup_reset:
+
+	/* Clear wakeup status register */
+	ldr	r0, =S5P6442_WAKEUP_STAT
+	ldr	r1, [r0]
+	str	r1, [r0]
+
+	/* Load return address and jump to kernel */
+	ldr	r0, =S5P6442_INFORM0
+
+	/* r1 = physical address of s5p6442_cpu_resume function */
+	ldr	r1, [r0]
+
+	/* Jump to kernel (sleep.S) */
+	mov	pc, r1
+	nop
+	nop
+#endif
+
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+system_clock_init:
+	ldr	r8, =S5P64XX_CLOCK_BASE		@ 0xE0100000
+
+	/* Set Lock Time */
+	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
+	str	r1, [r8, #0x000]		@ APLL_LOCK
+	str	r1, [r8, #0x008]		@ MPLL_LOCK
+	str	r1, [r8, #0x010]		@ EPLL_LOCK
+	str	r1, [r8, #0x020]		@ VPLL_LOCK
+
+	/* APLL_CON */
+	ldr	r1, =0x829b0c01		@ SDIV 1, PDIV 0xc, MDIV 0x29b
+	str	r1, [r8, #0x100]
+	/* MPLL_CON */
+	ldr	r1, =0x810a0303		@ SDIV 3, PDIV 3, MDIV 0x10a
+	str	r1, [r8, #0x108]
+	/* EPLL_CON */
+	ldr	r1, =0x80600303		@ SDIV 3, PDIV 3, MDIV 0x60
+	str	r1, [r8, #0x110]
+	/* VPLL_CON */
+	ldr	r1, =0x806c0303		@ SDIV 3, PDIV 3, MDIV 0x6c
+	str	r1, [r8, #0x120]
+
+	/* Set Source Clock */
+	ldr	r1, =0x1111			@ A, M, E, VPLL Muxing
+	str	r1, [r8, #0x200]		@ CLK_SRC0
+
+	/* Set Clock divider */
+	ldr	r1, =0x10100000
+	str	r1, [r8, #0x300]
+
+	/* wait at least 200us to stablize all clock */
+	mov	r2, #0x10000
+1:	subs	r2, r2, #1
+	bne	1b
+
+	mov	pc, lr
+
+#ifndef CONFIG_ONENAND_IPL
+/*
+ * uart_asm_init: Initialize UART's pins
+ */
+uart_asm_init:
+	mov	r0, r8
+	ldr	r1, =0x22222222
+	str	r1, [r0, #0x0]			@ GPA0_CON
+	ldr	r1, =0x00000022
+	str	r1, [r0, #0x20]			@ GPA1_CON
+
+	mov	pc, lr
+#endif
diff --git a/board/samsung/smdk6442/mem_setup.S b/board/samsung/smdk6442/mem_setup.S
new file mode 100644
index 0000000..bb3bfaf
--- /dev/null
+++ b/board/samsung/smdk6442/mem_setup.S
@@ -0,0 +1,175 @@
+/*
+ * Copyright (C) 2010 Samsung Electrnoics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+	.globl mem_ctrl_asm_init
+mem_ctrl_asm_init:
+	ldr	r6, =S5P6442_DMC_BASE			@ 0xE6000000
+
+	/* DLL parameter setting */
+	ldr	r1, =0x00141408
+	str	r1, [r6, #0x018]			@ PHYCONTROL0
+	ldr	r1, =0x00008044
+	str	r1, [r6, #0x01C]			@ PHYCONTROL1
+
+	/* DLL on */
+	ldr	r1, =0x0014140a
+	str	r1, [r6, #0x018]			@ PHYCONTROL0
+
+	/* DLL start */
+	ldr	r1, =0x0014140b
+	str	r1, [r6, #0x018]			@ PHYCONTROL0
+
+	/*
+	 * auto refresh off
+	 * LPDDR: 0xf001090, MCP_C_TYPE: 0xf0010d0
+	 */
+	ldr	r1, =0x0f0010d0
+	str	r1, [r6, #0x000]			@ CONCONTROL
+
+	/*
+	 * Burst Length 4, 2 chips, 32-bit
+	 * OFF: dynamic self refresh, force precharge, dynamic power down
+	 * ON: clock stop
+	 * LPDDR: 0x00202100, MCP_C_TYPE: 0x00212101
+	 */
+	ldr	r1, =0x00212101
+	str	r1, [r6, #0x004]			@ MEMCONTROL
+
+	/*
+	 * Bank0
+	 * 0x30 -> 0x30000000
+	 * 0xf8 -> 0x37FFFFFF
+	 * [15:12] 0: Linear
+	 * [11:8 ] 2: 9 bits
+	 * [ 7:4 ] 2: 14 bits
+	 * [ 3:0 ] 2: 4 banks
+	 * LPDDR: 0x30f80312, MCP_C_TYPE: 0x30f80222
+	 */
+	ldr	r1, =0x30f80222
+	str	r1, [r6, #0x008]			@ MEMCONFIG0
+
+	/*
+	 * Bank1
+	 * 0x40 -> 0x40000000
+	 * 0xf0 -> 0x4FFFFFFF
+	 * [15:12] 0: Linear
+	 * [11:8 ] 2: 9 bits
+	 * [ 7:4 ] 2: 14 bits
+	 * [ 3:0 ] 2: 4 banks
+	 * LPDDR: 0x40f00222, MCP_C_TYPE: 0x40f00222
+	 */
+	ldr	r1, =0x40f00222
+	str	r1, [r6, #0x00c]			@ MEMCONFIG1
+
+	ldr	r1, =0xf0000000
+	str	r1, [r6, #0x014]			@ PRECHCONFIG
+
+	/*
+	 * FIXME: Please verify these values
+	 * 7.8us * 166MHz %LE %LONG1294(0x50E)
+	 * 7.8us * 133MHz %LE %LONG1038(0x40E),
+	 * 7.8us * 100MHz %LE %LONG780(0x30C),
+	 * 7.8us * 20MHz  %LE %LONG156(0x9C),
+	 * 7.8us * 10MHz  %LE %LONG78(0x4E)
+	 */
+	ldr	r1, =0x0000040e
+	str	r1, [r6, #0x030]			@ TIMINGAREF
+
+	/* 133 MHz */
+	ldr	r1, =0x0c233286
+	str	r1, [r6, #0x034]			@ TIMINGROW
+
+	/* t_wtr=1 t_wr=2 t_rtp=1 cl=3 wl=0 rl=5 */
+	ldr	r1, =0x12130005
+	str	r1, [r6, #0x038]			@ TIMINGDATA
+
+	/*
+	 * t_faw=0xe t_xsr=0x12 t_xp=2 t_cke=2 t_mrd=2
+	 * LPDDR: 0x0e100222, MCP_C_TYPE: 0x0e120222
+	 */
+	ldr	r1, =0x0e120222
+	str	r1, [r6, #0x03C]			@ TIMINGPOWER
+
+	/* LPDDR: chip0, MCP_C_TYPE: chip0, chip1 */
+	/* chip0 Deselect */
+	ldr	r1, =0x07000000
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+
+	/* chip0 PALL */
+	ldr	r1, =0x01000000
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+
+	/* chip0 REFA */
+	ldr	r1, =0x05000000
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+	/* chip0 REFA */
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+
+	/* chip0 MRS, CL%LE %LONG3, BL%LE %LONG4 */
+	ldr	r1, =0x00000032
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+
+	/* chip1 Deselect */
+	ldr	r1, =0x07100000
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+
+	/* chip1 PALL */
+	ldr	r1, =0x01100000
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+
+	/* chip1 REFA */
+	ldr	r1, =0x05100000
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+	/* chip1 REFA */
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+
+	/* chip1 MRS, CL%LE %LONG3, BL%LE %LONG4 */
+	ldr	r1, =0x00100032
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+
+	/*
+	 * auto refresh on
+	 * LPDDR: 0x0f0010b0, MCP_C_TYPE: 0x0f0010f0
+	 */
+	ldr	r1, =0x0f0010f0
+	str	r1, [r6, #0x000]			@ CONCONTROL
+
+	/* PwrdnConfig */
+	ldr	r1, =0x00100002
+	str	r1, [r6, #0x028]			@ PWRDNCONFIG
+
+	/*
+	 * Burst Length 4, 2 chips, 32-bit
+	 * OFF: dynamic self refresh, force precharge, dynamic power down
+	 * ON: clock stop
+	 * LPDDR: 0x00202100, MCP_C_TYPE: 0x00212101
+	 */
+	ldr	r1, =0x00212101
+	str	r1, [r6, #0x004]			@ MEMCONTROL
+
+	mov	pc, lr
+
+	.ltorg
diff --git a/board/samsung/smdk6442/onenand.c b/board/samsung/smdk6442/onenand.c
new file mode 100644
index 0000000..32b9af9
--- /dev/null
+++ b/board/samsung/smdk6442/onenand.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <linux/mtd/samsung_onenand.h>
+
+#include <onenand_uboot.h>
+
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+void onenand_board_init(struct mtd_info *mtd)
+{
+	struct onenand_chip *this = mtd->priv;
+
+	this->base = (void *) 0xB0000000;
+	this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK;
+}
diff --git a/board/samsung/smdk6442/smdk6442.c b/board/samsung/smdk6442/smdk6442.c
new file mode 100644
index 0000000..bb8d469
--- /dev/null
+++ b/board/samsung/smdk6442/smdk6442.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_SMDK6442;
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	printf("Board:\t6442\n");
+	return 0;
+}
+#endif
diff --git a/include/configs/smdk6442.h b/include/configs/smdk6442.h
new file mode 100644
index 0000000..472e43d
--- /dev/null
+++ b/include/configs/smdk6442.h
@@ -0,0 +1,242 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ * Configuation settings for the SAMSUNG board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SAMSUNG		1	/* in a SAMSUNG core */
+#define CONFIG_S5P64XX		1	/* which is in a S5P64XX Family */
+#define CONFIG_S5P6442		1	/* which is in a S5P6442 */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+
+/* input clock of PLL: SMDK6442 has 12MHz input clock */
+#define CONFIG_SYS_CLK_FREQ_6442	12000000
+
+/* DRAM Base */
+#define CONFIG_SYS_SDRAM_BASE		0x30000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * Size of malloc() pool
+ * 1MB = 0x100000, 0x100000 = 1024 * 1024
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes for */
+						/* initial data */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1			1	/* use SERIAL 1 on S5P6442 */
+#define CONFIG_SERIAL_MULTI		1
+#define CONFIG_BAUDRATE			115200
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_XIMG
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NET
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_ONENAND
+#define CONFIG_CMD_MTDPARTS
+
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+#define MTDIDS_DEFAULT		"onenand0=samsung-onenand"
+#define MTDPARTS_DEFAULT	"mtdparts=samsung-onenand:256k(bootloader)"\
+				",256k(params)"\
+				",3m(kernel)"\
+				",16m(test)"\
+				",-(UBI)\0"
+
+#define CONFIG_BOOTCOMMAND	"run ubifsboot"
+
+#define CONFIG_RAMDISK_BOOT	"root=/dev/ram0 rw rootfstype=ext2" \
+				" console=ttySAC1,115200n8" \
+				" ${meminfo}"
+
+#define CONFIG_COMMON_BOOT	"console=ttySAC1,115200n8" \
+				" ${meminfo}" \
+				" ${mtdparts}"
+
+#define CONFIG_BOOTARGS	"root=/dev/mtdblock5 ubi.mtd=4" \
+			" rootfstype=cramfs " CONFIG_COMMON_BOOT
+
+#define CONFIG_UPDATEB	"updateb=onenand erase 0x0 0x40000;" \
+			" onenand write 0x32008000 0x0 0x40000\0"
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_UPDATEB \
+	"updatek=" \
+		"onenand erase 0x80000 0x300000;" \
+		"onenand write 0x31008000 0x80000 0x300000\0" \
+	"updateu=" \
+		"onenand erase 0x01560000 0x1eaa0000;" \
+		"onenand write 0x32000000 0x1260000 0x8C0000\0" \
+	"bootk=" \
+		"onenand read 0x30007FC0 0x80000 0x300000;" \
+		"bootm 0x30007FC0\0" \
+	"flashboot=" \
+		"set bootargs root=/dev/mtdblock${bootblock}" \
+		"rootfstype=${rootfstype}" \
+		"ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT "; " \
+		"run bootk\0" \
+	"ubifsboot=" \
+		"set bootargs root=ubi0!rootfs rootfstype=ubifs" \
+		"ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT "; " \
+		"run bootk\0" \
+	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
+	"android=" \
+		"set bootargs root=ubi0!ramdisk ubi.mtd=${ubiblock} " \
+		"rootfstype=ubifs init=/init.sh " CONFIG_COMMON_BOOT "; " \
+		"run bootk\0" \
+	"nfsboot=" \
+		"set bootargs root=/dev/nfs rw ubi.mtd=${ubiblock} " \
+		"nfsroot=${nfsroot},nolock,tcp " \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:" \
+		"${netmask}:generic:usb0:off " CONFIG_COMMON_BOOT "; " \
+		"run bootk\0" \
+	"ramboot=" \
+		"set bootargs " CONFIG_RAMDISK_BOOT \
+		"initrd=0x33000000,8M ramdisk=8192\0" \
+	"mmcboot=" \
+		"set bootargs root=${mmcblk} rootfstype=${rootfstype}" \
+		"ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT "; " \
+		"run bootk\0" \
+	"verify=n\0" \
+	"rootfstype=cramfs\0" \
+	"mtdparts=" MTDPARTS_DEFAULT \
+	"meminfo=mem=80M mem=256M at 0x40000000\0" \
+	"nfsroot=/nfsroot/arm\0" \
+	"mmcblk=/dev/mmcblk1p1\0" \
+	"bootblock=5\0" \
+	"ubiblock=4\0" \
+	"ubi=enabled"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		"SMDK6442 # "
+#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE	384	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4800000)
+
+#define CONFIG_SYS_HZ			1000
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* base address for uboot */
+#define CONFIG_SYS_PHY_UBOOT_BASE	(CONFIG_SYS_SDRAM_BASE + 0x04800000)
+#define CONFIG_SYS_UBOOT_BASE		(CONFIG_SYS_SDRAM_BASE + 0x04800000)
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(256 << 10)	/* regular stack 256KB */
+
+/* S5P6442 has 2 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS	2
+
+/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE	(80 << 20)		/* 80 MB in Bank #1 */
+
+/* SDRAM Bank #2 */
+#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + 0x10000000)
+#define PHYS_SDRAM_2_SIZE	(256 << 20)		/* 256 MB in Bank #2 */
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH		1
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+/*-----------------------------------------------------------------------
+ * Boot configuration
+ */
+#define CONFIG_ENV_IS_IN_ONENAND	1
+#define CONFIG_ENV_SIZE			(256 << 10)	/* 256 KiB, 0x40000 */
+#define CONFIG_ENV_ADDR			(256 << 10)	/* 256 KiB, 0x40000 */
+#define CONFIG_ENV_OFFSET		(256 << 10)	/* 256 KiB, 0x40000 */
+
+#define CONFIG_USE_ONENAND_BOARD_INIT
+#define CONFIG_SAMSUNG_ONENAND		1
+#define CONFIG_SYS_ONENAND_BASE		0xB0000000
+
+#define CONFIG_DOS_PARTITION	1
+
+#endif	/* __CONFIG_H */
-- 
1.6.3.3