From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andre Przywara Subject: Re: [PATCH] x86/hvm: accelerate I/O intercept handling Date: Wed, 31 Mar 2010 12:08:08 +0200 Message-ID: <4BB31F08.20403@amd.com> References: <4BB30C2A.4020408@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: "Cui, Dexuan" Cc: xen-devel , Keir Fraser List-Id: xen-devel@lists.xenproject.org Cui, Dexuan wrote: > Actually in 15425:6e934c799051, VMX once enabled the feature, but IIRC, > later Keir removed that in some cleanup patches and let the > EXIT_REASON_IO_INSTRUCTION handler invoke handle_mmio() also -- I don't > remember how people commented the slowness of IN/OUT emulation caused > the change... If I got this correctly, 15425 introduces only the OUTS/INS segment decoding feature, something that SVM does not have (yet ;-) As I said in my mail, I doubt the usefulness of the shortcut in this case, since it would require to access the guest memory and is used very rarely. So for the sake of a saner implementation I would avoid utilizing this feature, it simplifies the code much and avoids code duplication. That's why my code just implements non-string instructions. > One thing is: IIRC, old Intel CPUs don't supply the info, but your > patch doesn't check that... so your patch can break the CPUs. > Please refer to 15425. But this is only true for the segment decoding part, right? Appendix G of the Intel 3B manual only speaks of _this_ feature protected by bit 54 of IA32_VMX_BASIC MSR. Is the information shown in table 23-5 in section 23.2.1 not valid on all CPUs? If not, where can I check the support for this? Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 448-3567-12