Re: [PM][PATCH 2/4] OMAP3: Serial: Errata i202: fix for MDR1 access

[Nishanth Menon <nm@ti.com>]

Kattungal, Deepak had written, on 04/09/2010 12:06 PM, the following:
[..]
>> +	/* TX and RX FIFO Clear; FIFO dis */
>> +	serial_write_reg(p, UART_FCR, 0xA6);
> NAK
> Late realization: should be checking if FIFO clear actually occurred 
> before proceeding (FIFO clear bits will be cleared by h/w once it is 
> complete,
> so need to add a
> /* wait till  TX and RX fifos are cleard by h/w */
> while(serial_read_reg(p, UART_FCR) & 0x06)
> 	;
> 
> Deepak : The FCR is a Write-Only Register, the read to it wont return the correct value. If at all we need to add a check, 
 >the LSR should be read for the status of the FIFO. The same follows 
for the below section also.

Gee thx. Since RX fifo empty bit is 0 when empty and tx_fifo_empty bit 
is 1 when empty, i will change to:
while( 0x20 != (serial_read_reg(p, UART_LSR) & 0x21))
  	;
Also From errata it does not require to make sure that shift register 
also needs to be empty.. we could save a few nano seconds by not using that.

-- 
Regards,
Nishanth Menon