From: Heiko Schocher <hs@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/4] mpc832x: add support for the mpc8321 based suvd3 board
Date: Mon, 12 Apr 2010 09:33:18 +0200 [thread overview]
Message-ID: <4BC2CCBE.6060509@denx.de> (raw)
- serial console on UART1
- Ethernet RMII over UCC4
- PHY SMSC LAN8700
- 64MB Flash
- 128 MB DDR2 RAM
- I2C
- bootcount
This board is similiar to the kmeter1 (8360) board,
so common config options are extracted into the
include/configs/km83xx-common.h file.
Signed-off-by: Heiko Schocher <hs@denx.de>
---
MAINTAINERS | 1 +
MAKEALL | 1 +
Makefile | 5 +-
board/keymile/common/common.c | 4 +-
board/keymile/{kmeter1 => km83xx}/Makefile | 0
board/keymile/{kmeter1 => km83xx}/config.mk | 0
.../keymile/{kmeter1/kmeter1.c => km83xx/km83xx.c} | 86 ++++-
cpu/mpc83xx/cpu.c | 2 +-
cpu/mpc83xx/fdt.c | 3 +-
include/configs/km83xx-common.h | 348 ++++++++++++++++++++
include/configs/kmeter1.h | 334 +------------------
include/configs/suvd3.h | 216 ++++++++++++
12 files changed, 666 insertions(+), 334 deletions(-)
rename board/keymile/{kmeter1 => km83xx}/Makefile (100%)
rename board/keymile/{kmeter1 => km83xx}/config.mk (100%)
rename board/keymile/{kmeter1/kmeter1.c => km83xx/km83xx.c} (67%)
create mode 100644 include/configs/km83xx-common.h
create mode 100644 include/configs/suvd3.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 04c8730..47ff4c1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -412,6 +412,7 @@ Heiko Schocher <hs@denx.de>
municse MPC5200
sc3 PPC405GP
suen3 ARM926EJS (Kirkwood SoC)
+ suvd3 MPC8321
uc101 MPC5200
Peter De Schrijver <p2@mind.be>
diff --git a/MAKEALL b/MAKEALL
index fb1f7a3..9ae17c3 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -375,6 +375,7 @@ LIST_83xx=" \
MVBLM7 \
sbc8349 \
SIMPC8313_LP \
+ suvd3 \
TQM834x \
vme8349 \
"
diff --git a/Makefile b/Makefile
index 5d314c6..38b0488 100644
--- a/Makefile
+++ b/Makefile
@@ -2229,7 +2229,7 @@ TASREG_config : unconfig
#########################################################################
kmeter1_config: unconfig
- @$(MKCONFIG) kmeter1 ppc mpc83xx kmeter1 keymile
+ @$(MKCONFIG) kmeter1 ppc mpc83xx km83xx keymile
MPC8313ERDB_33_config \
MPC8313ERDB_66_config \
@@ -2388,6 +2388,9 @@ SIMPC8313_SP_config: unconfig
@$(MKCONFIG) -a SIMPC8313 ppc mpc83xx simpc8313 sheldon
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+suvd3_config: unconfig
+ @$(MKCONFIG) suvd3 ppc mpc83xx km83xx keymile
+
TQM834x_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x tqc
diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index 7b4eefd..9325eee 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -424,7 +424,7 @@ static int get_scl (void)
}
#endif
-#if !defined(CONFIG_KMETER1)
+#if !defined(CONFIG_MPC83xx)
static void writeStartSeq (void)
{
set_sda (1);
@@ -483,7 +483,7 @@ static int i2c_make_abort (void)
*/
void i2c_init_board(void)
{
-#if defined(CONFIG_KMETER1)
+#if defined(CONFIG_MPC83xx)
struct fsl_i2c *dev;
dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
uchar dummy;
diff --git a/board/keymile/kmeter1/Makefile b/board/keymile/km83xx/Makefile
similarity index 100%
rename from board/keymile/kmeter1/Makefile
rename to board/keymile/km83xx/Makefile
diff --git a/board/keymile/kmeter1/config.mk b/board/keymile/km83xx/config.mk
similarity index 100%
rename from board/keymile/kmeter1/config.mk
rename to board/keymile/km83xx/config.mk
diff --git a/board/keymile/kmeter1/kmeter1.c b/board/keymile/km83xx/km83xx.c
similarity index 67%
rename from board/keymile/kmeter1/kmeter1.c
rename to board/keymile/km83xx/km83xx.c
index bbcaf5d..d7e4f82 100644
--- a/board/keymile/kmeter1/kmeter1.c
+++ b/board/keymile/km83xx/km83xx.c
@@ -11,6 +11,9 @@
* (C) Copyright 2008
* Heiko Schocher, DENX Software Engineering, hs at denx.de.
*
+ * (C) Copyright 2009
+ * Heiko Schocher, DENX Software Engineering, hs at denx.de.
+ *
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
@@ -34,7 +37,7 @@ extern void disable_addr_trans (void);
extern void enable_addr_trans (void);
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* port pin dir open_drain assign */
-
+#if defined(CONFIG_KMETER1)
/* MDIO */
{0, 1, 3, 0, 2}, /* MDIO */
{0, 2, 1, 0, 1}, /* MDC */
@@ -57,6 +60,40 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
{5, 2, 1, 0, 1}, /* UART2_RTS */
{5, 3, 2, 0, 2}, /* UART2_SIN */
{5, 1, 2, 0, 3}, /* UART2_CTS */
+#else
+ /* Local Bus */
+ {0, 16, 1, 0, 3}, /* LA00 */
+ {0, 17, 1, 0, 3}, /* LA01 */
+ {0, 18, 1, 0, 3}, /* LA02 */
+ {0, 19, 1, 0, 3}, /* LA03 */
+ {0, 20, 1, 0, 3}, /* LA04 */
+ {0, 21, 1, 0, 3}, /* LA05 */
+ {0, 22, 1, 0, 3}, /* LA06 */
+ {0, 23, 1, 0, 3}, /* LA07 */
+ {0, 24, 1, 0, 3}, /* LA08 */
+ {0, 25, 1, 0, 3}, /* LA09 */
+ {0, 26, 1, 0, 3}, /* LA10 */
+ {0, 27, 1, 0, 3}, /* LA11 */
+ {0, 28, 1, 0, 3}, /* LA12 */
+ {0, 29, 1, 0, 3}, /* LA13 */
+ {0, 30, 1, 0, 3}, /* LA14 */
+ {0, 31, 1, 0, 3}, /* LA15 */
+
+ /* MDIO */
+ {3, 4, 3, 0, 2}, /* MDIO */
+ {3, 5, 1, 0, 2}, /* MDC */
+
+ /* UCC4 - UEC */
+ {1, 18, 1, 0, 1}, /* TxD0 */
+ {1, 19, 1, 0, 1}, /* TxD1 */
+ {1, 22, 2, 0, 1}, /* RxD0 */
+ {1, 23, 2, 0, 1}, /* RxD1 */
+ {1, 26, 2, 0, 1}, /* RxER */
+ {1, 28, 2, 0, 1}, /* Rx_DV */
+ {1, 30, 1, 0, 1}, /* TxEN */
+ {1, 31, 2, 0, 1}, /* CRS */
+ {3, 10, 2, 0, 3}, /* TxCLK->CLK17 */
+#endif
/* END of table */
{0, 0, 0, 0, QE_IOP_TAB_END},
@@ -79,9 +116,35 @@ static int board_init_i2c_busses (void)
return 0;
}
+#if defined(CONFIG_SUVD3)
+const uint upma_table[] =
+{ 0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, //Words 0 to 3
+ 0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, //Words 4 to 7
+ 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, //Words 8 to 11
+ 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, //Words 12 to 15
+ 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, //Words 16 to 19
+ 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, //Words 20 to 23
+ 0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, //Words 24 to 27
+ 0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, //Words 28 to 31
+ 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, //Words 32 to 35
+ 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, //Words 36 to 39
+ 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, //Words 40 to 43
+ 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, //Words 44 to 47
+ 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, //Words 48 to 51
+ 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, //Words 52 to 55
+ 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, //Words 56 to 59
+ 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01 //Words 60 to 63
+};
+#endif
+
int board_early_init_r (void)
{
unsigned short svid;
+#if defined(CONFIG_SUVD3)
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+ volatile fsl_lbus_t *lbus = &immap->lbus;
+ volatile u32 *mxmr = &lbus->mamr;
+#endif
/*
* Because of errata in the UCCs, we have to write to the reserved
@@ -101,9 +164,12 @@ int board_early_init_r (void)
setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x10003), 0x01);
/* enable the Unit LED (green) */
setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x00002), 0x01);
- /* take FE/GbE PHYs out of reset */
- setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x0000f), 0x1c);
+#if defined(CONFIG_SUVD3)
+ /* configure UPMA for APP1 */
+ upmconfig (UPMA, (uint *) upma_table, sizeof (upma_table) / sizeof (uint));
+ out_be32(mxmr, CONFIG_SYS_MAMR);
+#endif
return 0;
}
@@ -183,7 +249,9 @@ phys_size_t initdram (int board_type)
int checkboard (void)
{
- puts ("Board: Keymile kmeter1");
+ puts ("Board: Keymile ");
+ puts(CONFIG_KM_BOARD_NAME);
+
if (ethernet_present ())
puts (" with PIGGY.");
puts ("\n");
@@ -191,19 +259,9 @@ int checkboard (void)
}
#if defined(CONFIG_OF_BOARD_SETUP)
-/*
- * update property in the blob
- */
-void ft_blob_update (void *blob, bd_t *bd)
-{
- /* no board specific update */
-}
-
-
void ft_board_setup (void *blob, bd_t *bd)
{
ft_cpu_setup (blob, bd);
- ft_blob_update (blob, bd);
}
#endif
diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index 51180d6..5ca6f83 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -305,7 +305,7 @@ int cpu_mmc_init(bd_t *bis)
#ifdef CONFIG_BOOTCOUNT_LIMIT
-#if !defined(CONFIG_MPC8360)
+#if !defined(CONFIG_MPC8360) && !defined(CONFIG_MPC832x)
#error "CONFIG_BOOTCOUNT_LIMIT only for MPC8360 implemented"
#endif
diff --git a/cpu/mpc83xx/fdt.c b/cpu/mpc83xx/fdt.c
index daf73a6..482aa7a 100644
--- a/cpu/mpc83xx/fdt.c
+++ b/cpu/mpc83xx/fdt.c
@@ -32,7 +32,8 @@ extern void ft_qe_setup(void *blob);
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_BOOTCOUNT_LIMIT) && defined(CONFIG_MPC8360)
+#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
+ (defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x))
#include <asm/immap_qe.h>
void fdt_fixup_muram (void *blob)
diff --git a/include/configs/km83xx-common.h b/include/configs/km83xx-common.h
new file mode 100644
index 0000000..71dfd25
--- /dev/null
+++ b/include/configs/km83xx-common.h
@@ -0,0 +1,348 @@
+/*
+ * (C) Copyright 2009
+ * Heiko Schocher, DENX Software Engineering, hs at denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __CONFIG_KM83XX_H
+#define __CONFIG_KM83XX_H
+
+/* include common defines/options for all Keymile boards */
+#include "keymile-common.h"
+
+#define MTDIDS_DEFAULT "nor0=boot"
+#define MTDPARTS_DEFAULT "mtdparts=" \
+ "boot:" \
+ "768k(u-boot)," \
+ "128k(env)," \
+ "128k(envred)," \
+ "-(" CONFIG_KM_UBI_PARTITION_NAME ")"
+
+#define CONFIG_MISC_INIT_R 1
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN 66000000
+#define CONFIG_SYS_CLK_FREQ 66000000
+#define CONFIG_83XX_PCICLK 66000000
+
+/*
+ * IMMR new address
+ */
+#define CONFIG_SYS_IMMR 0xE0000000
+
+/*
+ * Bus Arbitration Configuration Register (ACR)
+ */
+#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
+#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
+#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
+#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
+ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+
+#define CFG_83XX_DDR_USES_CS0
+
+#undef CONFIG_DDR_ECC
+
+/*
+ * DDRCDR - DDR Control Driver Register
+ */
+
+#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */
+
+/*
+ * Manually set up DDR parameters
+ */
+#define CONFIG_DDR_II
+#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_FLASH_BASE 0xF0000000
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+/* Reserve 768 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+
+/*
+ * Init Local Bus Memory Controller:
+ *
+ * Bank Bus Machine PortSz Size Device
+ * ---- --- ------- ------ ----- ------
+ * 0 Local GPCM 16 bit 256MB FLASH
+ * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
+ *
+ */
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
+#define CONFIG_SYS_FLASH_PROTECTION 1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+
+#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */
+
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
+ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
+ BR_V)
+
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
+ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
+ OR_GPCM_SCY_5 | \
+ OR_GPCM_TRLX | OR_GPCM_EAD)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+
+/*
+ * PRIO1/PIGGY on the local bus CS1
+ */
+#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */
+
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \
+ (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
+ BR_V)
+#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | \
+ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
+ OR_GPCM_SCY_2 | \
+ OR_GPCM_TRLX | OR_GPCM_EAD)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#undef CONFIG_PCI /* No PCI */
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 1
+#endif
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#define CONFIG_ETHPRIME "FSL UEC0"
+
+#define CONFIG_UEC_ETH1 /* GETH1 */
+#define UEC_VERBOSE_DEBUG 1
+
+#ifdef CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
+#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
+#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
+#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR 0
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
+#endif
+
+/*
+ * Environment
+ */
+
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
+#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
+ CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+#else /* CFG_RAMBOOT */
+#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
+#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE 0x2000
+#endif /* CFG_RAMBOOT */
+
+/* I2C */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_FSL_I2C
+#define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_I2C_MULTI_BUS 1
+#define CONFIG_I2C_MUX 1
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible) */
+#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
+#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */
+#define CONFIG_SYS_DTT_MAX_TEMP 70
+#define CONFIG_SYS_DTT_LOW_TEMP -30
+#define CONFIG_SYS_DTT_HYSTERESIS 3
+#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_KMETER1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE CONFIG_SYS_PIGGY_BASE
+#endif
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#endif
+
+#if defined(CFG_RAMBOOT)
+#undef CONFIG_CMD_SAVEENV
+#undef CONFIG_CMD_LOADS
+#endif
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+
+/*
+ * Core HID Setup
+ */
+#define CONFIG_SYS_HID0_INIT 0x000000000
+#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID2 HID2_HBE
+
+/*
+ * MMU Setup
+ */
+
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
+/* DDR: cache cacheable */
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
+
+/* IMMRBAR & PCI IO: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
+
+/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define BOOTFLASH_START 0xF0000000
+
+#define CONFIG_KM_CONSOLE_TTY "ttyS0"
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
+#define CONFIG_KM_DEF_ENV "km-common=empty\0"
+#endif
+
+#ifndef CONFIG_KM_DEF_ROOTPATH
+#define CONFIG_KM_DEF_ROOTPATH \
+ "rootpath=/opt/eldk/ppc_82xx\0"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_KM_DEF_ENV \
+ CONFIG_KM_DEF_ROOTPATH \
+ "dtt_bus=pca9547:70:a\0" \
+ "EEprom_ivm=pca9547:70:9\0" \
+ "newenv=" \
+ "prot off 0xF00C0000 +0x40000 && " \
+ "era 0xF00C0000 +0x40000\0" \
+ "unlock=yes\0" \
+ ""
+
+#if defined(CONFIG_UEC_ETH)
+#define CONFIG_HAS_ETH0
+#endif
+
+#endif /* __CONFIG_KM83XX_H */
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index ed1e4b0..2df4cb2 100644
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -29,28 +29,21 @@
#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
#define CONFIG_KMETER1 1 /* KMETER1 board specific */
#define CONFIG_HOSTNAME kmeter1
+#define CONFIG_KM_BOARD_NAME "kmeter1"
#define CONFIG_KM_DEF_NETDEV \
"netdev=eth2\0" \
-/* include common defines/options for all Keymile boards */
-#include "keymile-common.h"
-
-#define MTDIDS_DEFAULT "nor0=boot"
-#define MTDPARTS_DEFAULT "mtdparts=" \
- "boot:" \
- "768k(u-boot)," \
- "128k(env)," \
- "128k(envred)," \
- "-(" CONFIG_KM_UBI_PARTITION_NAME ")"
+/* include common defines/options for all 83xx Keymile boards */
+#include "km83xx-common.h"
#define CONFIG_MISC_INIT_R 1
+
/*
- * System Clock Setup
+ * System IO Setup
*/
-#define CONFIG_83XX_CLKIN 66000000
-#define CONFIG_SYS_CLK_FREQ 66000000
-#define CONFIG_83XX_PCICLK 66000000
+#define CONFIG_SYS_SICRH 0x00000006
+#define CONFIG_SYS_SICRL 0x00000000
/*
* Hardware Reset Configuration Word
@@ -71,54 +64,7 @@
HRCWH_LALE_EARLY | \
HRCWH_LDP_CLEAR )
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH 0x00000006
-#define CONFIG_SYS_SICRL 0x00000000
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
-/*
- * Bus Arbitration Configuration Register (ACR)
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
-#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
-#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
- DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-
-#define CFG_83XX_DDR_USES_CS0
-
-#undef CONFIG_DDR_ECC
-
-/*
- * DDRCDR - DDR Control Driver Register
- */
-
-#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */
-
-/*
- * Manually set up DDR parameters
- */
-#define CONFIG_DDR_II
-#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
- CSCONFIG_ROW_BIT_13 | \
- CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
-
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
SDRAM_CFG_SREN)
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
@@ -126,6 +72,11 @@
#define CONFIG_SYS_DDR_INTERVAL ((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
(0x3cf << SDRAM_INTERVAL_REFINT_SHIFT))
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
+ CSCONFIG_ROW_BIT_13 | \
+ CSCONFIG_COL_BIT_10 | \
+ CSCONFIG_ODT_WR_ACS)
+
#define CONFIG_SYS_DDRCDR 0x40000001
#define CONFIG_SYS_DDR_MODE 0x47860452
#define CONFIG_SYS_DDR_MODE2 0x8080c000
@@ -158,32 +109,13 @@
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
-#define CONFIG_SYS_FLASH_BASE 0xF0000000
#define CONFIG_SYS_PIGGY_BASE 0xE8000000
#define CONFIG_SYS_PIGGY_SIZE 128
#define CONFIG_SYS_PAXE_BASE 0xA0000000
#define CONFIG_SYS_PAXE_SIZE 512
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* Reserve 768 kB for Mon */
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
/*
* Local Bus Configuration & Clock Setup
@@ -197,56 +129,14 @@
*
* Bank Bus Machine PortSz Size Device
* ---- --- ------- ------ ----- ------
- * 0 Local GPCM 16 bit 256MB FLASH
- * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
* 3 Local GPCM 8 bit 512MB PAXE
*
*/
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
-#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-#define CONFIG_SYS_FLASH_PROTECTION 1
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
-#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
- (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
- BR_V)
-
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
- OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
- OR_GPCM_SCY_5 | \
- OR_GPCM_TRLX | OR_GPCM_EAD)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-
-/*
- * PRIO1/PIGGY on the local bus CS1
- */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE /* Window base at flash base */
-#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */
-
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \
- (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
- BR_V)
-#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | /* 128MB */ \
- OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
- OR_GPCM_SCY_2 | \
- OR_GPCM_TRLX | OR_GPCM_EAD)
/*
* PAXE on the local bus CS3
*/
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE /* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE
#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \
@@ -258,165 +148,14 @@
OR_GPCM_TRLX | OR_GPCM_EAD)
/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#undef CONFIG_PCI /* No PCI */
-
-#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
-#endif
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME "FSL UEC0"
-
-#define CONFIG_UEC_ETH1 /* GETH1 */
-#define UEC_VERBOSE_DEBUG 1
-
-#ifdef CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
-#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
-#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
-#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR 0
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
-#endif
-
-/*
- * Environment
- */
-
-#ifndef CONFIG_SYS_RAMBOOT
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-#else /* CFG_RAMBOOT */
-#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
-#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
-#define CONFIG_ENV_SIZE 0x2000
-#endif /* CFG_RAMBOOT */
-
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_FSL_I2C
-#define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_I2C_MULTI_BUS 1
-#define CONFIG_I2C_MUX 1
-
-/* EEprom support */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
-/* I2C SYSMON (LM75, AD7414 is almost compatible) */
-#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
-#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */
-#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_LOW_TEMP -30
-#define CONFIG_SYS_DTT_HYSTERESIS 3
-#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
-
-#if defined(CONFIG_CMD_NAND)
-#define CONFIG_NAND_KMETER1
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE CONFIG_SYS_PIGGY_BASE
-#endif
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_PCI
-#endif
-
-#if defined(CFG_RAMBOOT)
-#undef CONFIG_CMD_SAVEENV
-#undef CONFIG_CMD_LOADS
-#endif
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
* MMU Setup
*/
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
/* PAXE: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
@@ -444,39 +183,4 @@
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#endif /* CONFIG_PCI */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#define BOOTFLASH_START 0xF0000000
-
-#define CONFIG_KM_CONSOLE_TTY "ttyS0"
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
-#define CONFIG_KM_DEF_ENV "km-common=empty\0"
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_KM_DEF_ENV \
- "dtt_bus=pca9547:70:a\0" \
- "EEprom_ivm=pca9547:70:9\0" \
- "newenv=" \
- "prot off 0xF00C0000 +0x40000 && " \
- "era 0xF00C0000 +0x40000\0" \
- "rootpath=/opt/eldk/ppc_82xx\0" \
- "unlock=yes\0" \
- ""
-
-#if defined(CONFIG_UEC_ETH)
-#define CONFIG_HAS_ETH0
-#endif
-
#endif /* __CONFIG_H */
diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h
new file mode 100644
index 0000000..b97cd3c
--- /dev/null
+++ b/include/configs/suvd3.h
@@ -0,0 +1,216 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ * Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ * Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs at denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 family */
+#define CONFIG_QE 1 /* Has QE */
+#define CONFIG_MPC83xx 1 /* MPC83xx family */
+#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
+#define CONFIG_SUVD3 1 /* SUVD3 board specific */
+#define CONFIG_HOSTNAME suvd3
+#define CONFIG_KM_BOARD_NAME "suvd3"
+
+#define CONFIG_KM_DEF_NETDEV \
+ "netdev=eth0\0"
+
+#define CONFIG_KM_DEF_ROOTPATH \
+ "rootpath=/opt/eldk/ppc_8xx\0"
+
+/* include common defines/options for all 83xx Keymile boards */
+#include "km83xx-common.h"
+
+#define CONFIG_MISC_INIT_R 1
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRH 0x00000006
+#define CONFIG_SYS_SICRL SICRL_IRQ_CKS
+
+/*
+ * Hardware Reset Configuration Word
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
+ HRCWL_DDR_TO_SCB_CLK_2X1 | \
+ HRCWL_CSB_TO_CLKIN_2X1 | \
+ HRCWL_CORE_TO_CSB_2_5X1 | \
+ HRCWL_CE_PLL_VCO_DIV_2 | \
+ HRCWL_CE_TO_PLL_1X3 )
+
+#define CONFIG_SYS_HRCW_HIGH (\
+ HRCWH_PCI_AGENT | \
+ HRCWH_PCI_ARBITER_DISABLE | \
+ HRCWH_CORE_ENABLE | \
+ HRCWH_FROM_0X00000100 | \
+ HRCWH_BOOTSEQ_DISABLE | \
+ HRCWH_SW_WATCHDOG_DISABLE | \
+ HRCWH_ROM_LOC_LOCAL_16BIT | \
+ HRCWH_BIG_ENDIAN | \
+ HRCWH_LALE_NORMAL )
+
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
+#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
+ SDRAM_CFG_32_BE | \
+ SDRAM_CFG_SREN)
+#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
+#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+ (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
+
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
+ CSCONFIG_ODT_WR_CFG | \
+ CSCONFIG_ROW_BIT_13 | \
+ CSCONFIG_COL_BIT_10)
+
+#define CONFIG_SYS_DDR_MODE 0x47860252
+#define CONFIG_SYS_DDR_MODE2 0x8080c000
+
+#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+ (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+ (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+ (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+ (0 << TIMING_CFG0_WWT_SHIFT) | \
+ (0 << TIMING_CFG0_RRT_SHIFT) | \
+ (0 << TIMING_CFG0_WRT_SHIFT) | \
+ (0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_50) | \
+ ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
+ ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+ ( 2 << TIMING_CFG1_WRREC_SHIFT) | \
+ ( 6 << TIMING_CFG1_REFREC_SHIFT) | \
+ ( 2 << TIMING_CFG1_ACTTORW_SHIFT) | \
+ ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+ ( 2 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+ (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+ (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+ (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+ (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+ (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
+ (5 << TIMING_CFG2_CPO_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+
+#define CONFIG_SYS_PIGGY_BASE 0xE8000000
+#define CONFIG_SYS_PIGGY_SIZE 128
+#define CONFIG_SYS_APP1_BASE 0xA0000000
+#define CONFIG_SYS_APP1_SIZE 256 // Megabytes
+#define CONFIG_SYS_APP2_BASE 0xB0000000
+#define CONFIG_SYS_APP2_SIZE 256 // Megabytes
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2)
+#define CONFIG_SYS_LBC_LBCR 0x00000000
+
+/*
+ * Init Local Bus Memory Controller:
+ *
+ * Bank Bus Machine PortSz Size Device
+ * ---- --- ------- ------ ----- ------
+ * 2 Local UPMA 16 bit 256MB APP1
+ * 3 Local GPCM 16 bit 256MB APP2
+ *
+ */
+
+/*
+ * APP1 on the local bus CS2
+ */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM LBLAWAR_EN | LBLAWAR_256MB
+
+#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \
+ BR_PS_16 | \
+ BR_MS_UPMA | \
+ BR_V)
+#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
+
+#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
+ BR_PS_16 | \
+ BR_V)
+
+#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
+ OR_GPCM_CSNT | \
+ OR_GPCM_ACS_DIV4 | \
+ OR_GPCM_SCY_3 | \
+ OR_GPCM_TRLX)
+
+#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
+ 0x0000c000 | \
+ MxMR_WLFx_2X)
+
+#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
+#define CONFIG_SYS_LBLAWAR3_PRELIM LBLAWAR_EN | LBLAWAR_256MB
+
+/*
+ * MMU Setup
+ */
+
+
+/* APP1: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
+
+#ifdef CONFIG_PCI
+/* PCI MEM space: cacheable */
+#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT6L CFG_IBAT6L
+#define CFG_DBAT6U CFG_IBAT6U
+/* PCI MMIO space: cache-inhibit and guarded */
+#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT7L CFG_IBAT7L
+#define CFG_DBAT7U CFG_IBAT7U
+#else /* CONFIG_PCI */
+
+/* APP2: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
+
+#define CONFIG_SYS_IBAT7L (0)
+#define CONFIG_SYS_IBAT7U (0)
+#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
+#endif /* CONFIG_PCI */
+
+#endif /* __CONFIG_H */
--
1.6.2.5
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
next reply other threads:[~2010-04-12 7:33 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-04-12 7:33 Heiko Schocher [this message]
2010-04-22 11:20 ` [U-Boot] [PATCH 2/4] mpc832x: add support for the mpc8321 based suvd3 board Wolfgang Denk
2010-04-23 11:39 ` Heiko Schocher
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=4BC2CCBE.6060509@denx.de \
--to=hs@denx.de \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.