From: Pat Erley <pat-lkml@erley.org>
To: linux-acpi@vger.kernel.org
Subject: Re: Working DSDT+SSDT, what's next?
Date: Mon, 19 Apr 2010 00:47:25 -0400 [thread overview]
Message-ID: <4BCBE05D.5090600@erley.org> (raw)
In-Reply-To: <f95d4e7ce96630fd1e07c05fd8ab2504@127.0.0.1>
Ok, I've continued learning, more info injected below:
On 04/16/10 14:42, pat-lkml@erley.org wrote:
> Ok, first time poster, long time reader.
>
> I have a Clevo D900T mobo based laptop. These were only ever produced
> with p4 5xx series chips, but the chipset (ICH6) supports the 6xx series.
> Because it was never produced with a 6xx cpu, a bios was never released
> that supported things like EIST or EM64T. EM64T worked fine, out of the
> box. EIST did not (due to no SSDT tables with PSS/PCT/PPC methods). I was
> able to get EIST working with a hacked-up DSDT, but I'm curious if I'm
> doing everything I should.
>
> Intel CPU Spec: http://processorfinder.intel.com/details.aspx?sSpec=SL8Q7
> Intel Data Sheet:
> http://download.intel.com/design/Pentium4/datashts/303128.pdf
>
> Right now, I just have 2 C States, for 3.0Ghz and 2.8Ghz. It's my
> understanding that these are the only speeds EIST can do in this CPU.
>
> now, the questions:
>
> 1. Is there something I should be doing with a _CSD type entry in my
> CPU{0,1} entries to signify that they're HT?
Yep, I needed to add a pair of _CSD entries. EIST is now adjusting speeds correctly!
> 3. How do I determine VID values?
> a. I've just lowered VID 1 by 1, loading the system until it became
> unstable, at which point I added 1 and called it good
> b. Is there any advantage to multiple VID's with 1 VID? IE:
> 3ghz@1.45V, 3Ghz@1.25V
People in linux-pch have helped me here
> 4. in the PSS table, the first entry (3000,2800 in my case), are those
> just for show?
Still don't have an answer here.
> 5. Are there additional features the CPU supports that, due to bios
> limitation, I should enable this way (C1E?)
Ok, I now now I need to come up with a _CST table (unless one of the other tables is doing this...) to enable C-States, and C1E in particular... Anyone have any pointers on where to start on this? All of the info I seem to be able to find are for C2Q and newer CPUs, not older P4s like what I have.
> outline of what I've done: http://pat.erley.org/Other/P4EISTSSDT
>
> Pat Erley
Pat Erley
next prev parent reply other threads:[~2010-04-19 4:47 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-04-16 18:42 Working DSDT+SSDT, what's next? pat-lkml
2010-04-19 4:47 ` Pat Erley [this message]
2010-05-06 6:00 ` Len Brown
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