From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1O3th9-0001OL-Hw for qemu-devel@nongnu.org; Mon, 19 Apr 2010 12:19:35 -0400 Received: from [140.186.70.92] (port=58241 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O3th4-0001K1-Mx for qemu-devel@nongnu.org; Mon, 19 Apr 2010 12:19:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1O3th0-0005S5-7E for qemu-devel@nongnu.org; Mon, 19 Apr 2010 12:19:30 -0400 Received: from moutng.kundenserver.de ([212.227.17.8]:57601) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1O3tgz-0005RC-My for qemu-devel@nongnu.org; Mon, 19 Apr 2010 12:19:26 -0400 Message-ID: <4BCC8289.9030204@mail.berlios.de> Date: Mon, 19 Apr 2010 18:19:21 +0200 From: Stefan Weil MIME-Version: 1.0 References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] Re: singlestep and sparc32 List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Artyom Tarasenko Cc: Blue Swirl , qemu-devel Artyom Tarasenko schrieb: > is -single-step option supposed to work under qemu-system-sparc? Or is > it only for non-pipelined CPUs? > > I get pretty strange results: some addresses seem to be executed > twice, and then qemu hangs on the last nop: > > -------------- > IN: > 0x00000000: b 0xb788 > -------------- > IN: > 0x00000004: rd %psr, %l0 > -------------- > IN: > 0x00000004: rd %psr, %l0 > -------------- > IN: > 0x00000008: nop > -------------- > IN: > 0x00000008: nop > -------------- > IN: > 0x0000000c: nop > -------------- > IN: > 0x0000000c: nop > > ... skipped ... > > IN: > 0x7000a58c: bg 0x7000a588 > -------------- > IN: > 0x7000a590: nop > -------------- > IN: > 0x7000a590: nop > -------------- > IN: > 0x7000a594: b 0x7000a570 > -------------- > IN: > 0x7000a594: b 0x7000a570 > -------------- > IN: > 0x7000a578: be 0x7000a59c > -------------- > IN: > 0x7000a580: stba %l1, [ %l0 ] #ASI_M_BYPASS > -------------- > IN: > 0x7000a588: deccc %l2 > -------------- > IN: > 0x7000a594: b 0x7000a570 > -------------- > IN: > 0x7000a590: nop > > ^^^^^^^^^^^ That's the end > > Without -singlestep it seems to work better: > > > 0x7000a588: deccc %l2 > 0x7000a58c: bg 0x7000a588 > 0x7000a590: nop > > -------------- > IN: > 0x7000a594: b 0x7000a570 > 0x7000a598: inc %l4 > > -------------- > IN: > 0x7000a570: lduba [ %l4 ] #ASI_M_KERNELTXT, %l1 > 0x7000a574: cmp %l1, 0xff > 0x7000a578: be 0x7000a59c > ... and so on ... I use it for x86, mips and powerpc targets. So pipelined CPUs work at least for some target architectures, and sparc's singlestep is broken. Have a look at target-mips/translate.c or target-ppc/translate.c and compare their handling of singlestep to the handling in target-sparc/translate.c. The sparc variant is very simple - too simple, I assume. Stefan