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Message-ID: <4BCF39A7.3020708@caviumnetworks.com>
Date:   Wed, 21 Apr 2010 10:45:11 -0700
From:   David Daney <ddaney@caviumnetworks.com>
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To:     Ralf Baechle <ralf@linux-mips.org>
CC:     Deng-Cheng Zhu <dengcheng.zhu@gmail.com>,
        linux-mips@linux-mips.org, a.p.zijlstra@chello.nl,
        paulus@samba.org, mingo@elte.hu, acme@redhat.com,
        jamie.iles@picochip.com
Subject: Re: [PATCH 1/3] MIPS: use the generic atomic64 operations for perf
 counter support
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On 04/21/2010 10:19 AM, Ralf Baechle wrote:
[...]
>
> -#ifdef CONFIG_64BIT
> +typedef struct {
> +	long long counter;
> +} atomic64_t;
>

How does this not conflict with the definition in linux/types.h for a 
64-bit kernel?


>   #define ATOMIC64_INIT(i)    { (i) }
>
> @@ -410,14 +414,44 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
>    * @v: pointer of type atomic64_t
>    *
>    */
> -#define atomic64_read(v)	((v)->counter)
> +static long long __inline__ atomic64_read(const atomic64_t *v)
> +{
> +	unsigned long flags;
> +	raw_spinlock_t *lock;
> +	long long val;
> +
> +	if (cpu_has_64bit_gp_regs)	/* 64-bit regs imply 64-bit ld / sd  */
> +		return v->counter;
> +

How is this atomic for the o32 ABI?  counter is now not volatile, in 
o32, u64 values are often split between two registers.  There is nothing 
to guarantee that the compiler will use LD.


David Daney