diff for duplicates of <4BD7C240.5050800@renesas.com> diff --git a/a/1.txt b/N1/1.txt index 9c5028f..70f75b7 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -287,7 +287,7 @@ index 0000000..eb97830 + + if (!clk) + return; -+ if (p->sup_pclk && clk == host->clk) ++ if (p->sup_pclk && clk = host->clk) + sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); + else + sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & @@ -370,9 +370,9 @@ index 0000000..eb97830 + /* buf read enable */ + sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); + time = wait_event_interruptible_timeout(host->intr_wait, -+ host->wait_int == 1 || -+ host->sd_error == 1, host->timeout); -+ if (host->wait_int != 1 && (time == 0 || host->sd_error != 0)) ++ host->wait_int = 1 || ++ host->sd_error = 1, host->timeout); ++ if (host->wait_int != 1 && (time = 0 || host->sd_error != 0)) + return sh_mmcif_error_manage(host); + + host->wait_int = 0; @@ -384,9 +384,9 @@ index 0000000..eb97830 + /* buffer read end */ + sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); + time = wait_event_interruptible_timeout(host->intr_wait, -+ host->wait_int == 1 || -+ host->sd_error == 1, host->timeout); -+ if (host->wait_int != 1 && (time == 0 || host->sd_error != 0)) ++ host->wait_int = 1 || ++ host->sd_error = 1, host->timeout); ++ if (host->wait_int != 1 && (time = 0 || host->sd_error != 0)) + return sh_mmcif_error_manage(host); + + host->wait_int = 0; @@ -408,11 +408,11 @@ index 0000000..eb97830 + sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); + /* buf read enable */ + time = wait_event_interruptible_timeout(host->intr_wait, -+ host->wait_int == 1 || -+ host->sd_error == 1, host->timeout); ++ host->wait_int = 1 || ++ host->sd_error = 1, host->timeout); + + if (host->wait_int != 1 && -+ (time == 0 || host->sd_error != 0)) ++ (time = 0 || host->sd_error != 0)) + return sh_mmcif_error_manage(host); + + host->wait_int = 0; @@ -437,9 +437,9 @@ index 0000000..eb97830 + + /* buf write enable */ + time = wait_event_interruptible_timeout(host->intr_wait, -+ host->wait_int == 1 || -+ host->sd_error == 1, host->timeout); -+ if (host->wait_int != 1 && (time == 0 || host->sd_error != 0)) ++ host->wait_int = 1 || ++ host->sd_error = 1, host->timeout); ++ if (host->wait_int != 1 && (time = 0 || host->sd_error != 0)) + return sh_mmcif_error_manage(host); + + host->wait_int = 0; @@ -452,9 +452,9 @@ index 0000000..eb97830 + sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); + + time = wait_event_interruptible_timeout(host->intr_wait, -+ host->wait_int == 1 || -+ host->sd_error == 1, host->timeout); -+ if (host->wait_int != 1 && (time == 0 || host->sd_error != 0)) ++ host->wait_int = 1 || ++ host->sd_error = 1, host->timeout); ++ if (host->wait_int != 1 && (time = 0 || host->sd_error != 0)) + return sh_mmcif_error_manage(host); + + host->wait_int = 0; @@ -477,11 +477,11 @@ index 0000000..eb97830 + sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); + /* buf write enable*/ + time = wait_event_interruptible_timeout(host->intr_wait, -+ host->wait_int == 1 || -+ host->sd_error == 1, host->timeout); ++ host->wait_int = 1 || ++ host->sd_error = 1, host->timeout); + + if (host->wait_int != 1 && -+ (time == 0 || host->sd_error != 0)) ++ (time = 0 || host->sd_error != 0)) + return sh_mmcif_error_manage(host); + + host->wait_int = 0; @@ -564,24 +564,24 @@ index 0000000..eb97830 + } + } + /* DWEN */ -+ if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) ++ if (opc = MMC_WRITE_BLOCK || opc = MMC_WRITE_MULTIPLE_BLOCK) + tmp |= CMD_SET_DWEN; + /* CMLTE/CMD12EN */ -+ if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { ++ if (opc = MMC_READ_MULTIPLE_BLOCK || opc = MMC_WRITE_MULTIPLE_BLOCK) { + tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; + sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, + mrq->data->blocks << 16); + } + /* RIDXC[1:0] check bits */ -+ if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || -+ opc == MMC_SEND_CSD || opc == MMC_SEND_CID) ++ if (opc = MMC_SEND_OP_COND || opc = MMC_ALL_SEND_CID || ++ opc = MMC_SEND_CSD || opc = MMC_SEND_CID) + tmp |= CMD_SET_RIDXC_BITS; + /* RCRC7C[1:0] check bits */ -+ if (opc == MMC_SEND_OP_COND) ++ if (opc = MMC_SEND_OP_COND) + tmp |= CMD_SET_CRC7C_BITS; + /* RCRC7C[1:0] internal CRC7 */ -+ if (opc == MMC_ALL_SEND_CID || -+ opc == MMC_SEND_CSD || opc == MMC_SEND_CID) ++ if (opc = MMC_ALL_SEND_CID || ++ opc = MMC_SEND_CSD || opc = MMC_SEND_CID) + tmp |= CMD_SET_CRC7C_INTERNAL; + + return opc = ((opc << 24) | tmp); @@ -657,8 +657,8 @@ index 0000000..eb97830 + sh_mmcif_writel(host, MMCIF_CE_CMD_SET, opc); + + time = wait_event_interruptible_timeout(host->intr_wait, -+ host->wait_int == 1 || host->sd_error == 1, host->timeout); -+ if (host->wait_int != 1 && time == 0) { ++ host->wait_int = 1 || host->sd_error = 1, host->timeout); ++ if (host->wait_int != 1 && time = 0) { + cmd->error = sh_mmcif_error_manage(host); + return; + } @@ -684,7 +684,7 @@ index 0000000..eb97830 + host->wait_int = 0; + return; + } -+ if (host->wait_int == 1) { ++ if (host->wait_int = 1) { + sh_mmcif_get_response(host, cmd); + host->wait_int = 0; + } @@ -693,8 +693,7 @@ index 0000000..eb97830 + if (ret < 0) + mrq->data->bytes_xfered = 0; + else -+ mrq->data->bytes_xfered = -+ mrq->data->blocks * mrq->data->blksz; ++ mrq->data->bytes_xfered + mrq->data->blocks * mrq->data->blksz; + } + cmd->error = ret; +} @@ -704,9 +703,9 @@ index 0000000..eb97830 +{ + long time; + -+ if (mrq->cmd->opcode == MMC_READ_MULTIPLE_BLOCK) ++ if (mrq->cmd->opcode = MMC_READ_MULTIPLE_BLOCK) + sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); -+ else if (mrq->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK) ++ else if (mrq->cmd->opcode = MMC_WRITE_MULTIPLE_BLOCK) + sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); + else { + pr_err(DRIVER_NAME": not support stop cmd\n"); @@ -715,9 +714,9 @@ index 0000000..eb97830 + } + + time = wait_event_interruptible_timeout(host->intr_wait, -+ host->wait_int == 1 || -+ host->sd_error == 1, host->timeout); -+ if (host->wait_int != 1 && (time == 0 || host->sd_error != 0)) { ++ host->wait_int = 1 || ++ host->sd_error = 1, host->timeout); ++ if (host->wait_int != 1 && (time = 0 || host->sd_error != 0)) { + cmd->error = sh_mmcif_error_manage(host); + return; + } @@ -766,13 +765,13 @@ index 0000000..eb97830 + struct sh_mmcif_host *host = mmc_priv(mmc); + struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; + -+ if (ios->power_mode == MMC_POWER_OFF) { ++ if (ios->power_mode = MMC_POWER_OFF) { + /* clock stop */ + sh_mmcif_clock_control(host, 0); + if (p->down_pwr) + p->down_pwr(host->pd); + return; -+ } else if (ios->power_mode == MMC_POWER_UP) { ++ } else if (ios->power_mode = MMC_POWER_UP) { + if (p->set_pwr) + p->set_pwr(host->pd, ios->power_mode); + } diff --git a/a/content_digest b/N1/content_digest index a0c5962..a502b33 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,6 +1,7 @@ + "ref\020100427221705.1628375b.akpm@linux-foundation.org\0" "From\0Yusuke Goda <yusuke.goda.sx@renesas.com>\0" "Subject\0[PATCH 1/2 v2] MMC:Add support MMCIF for SuperH\0" - "Date\0Wed, 28 Apr 2010 14:06:08 +0900\0" + "Date\0Wed, 28 Apr 2010 05:06:08 +0000\0" "To\0akpm@linux-foundation.org" ben@decadent.org.uk linux-mmc@vger.kernel.org @@ -297,7 +298,7 @@ "+\n" "+\tif (!clk)\n" "+\t\treturn;\n" - "+\tif (p->sup_pclk && clk == host->clk)\n" + "+\tif (p->sup_pclk && clk = host->clk)\n" "+\t\tsh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);\n" "+\telse\n" "+\t\tsh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &\n" @@ -380,9 +381,9 @@ "+\t/* buf read enable */\n" "+\tsh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);\n" "+\ttime = wait_event_interruptible_timeout(host->intr_wait,\n" - "+\t\t\thost->wait_int == 1 ||\n" - "+\t\t\thost->sd_error == 1, host->timeout);\n" - "+\tif (host->wait_int != 1 && (time == 0 || host->sd_error != 0))\n" + "+\t\t\thost->wait_int = 1 ||\n" + "+\t\t\thost->sd_error = 1, host->timeout);\n" + "+\tif (host->wait_int != 1 && (time = 0 || host->sd_error != 0))\n" "+\t\treturn sh_mmcif_error_manage(host);\n" "+\n" "+\thost->wait_int = 0;\n" @@ -394,9 +395,9 @@ "+\t/* buffer read end */\n" "+\tsh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);\n" "+\ttime = wait_event_interruptible_timeout(host->intr_wait,\n" - "+\t\t\thost->wait_int == 1 ||\n" - "+\t\t\thost->sd_error == 1, host->timeout);\n" - "+\tif (host->wait_int != 1 && (time == 0 || host->sd_error != 0))\n" + "+\t\t\thost->wait_int = 1 ||\n" + "+\t\t\thost->sd_error = 1, host->timeout);\n" + "+\tif (host->wait_int != 1 && (time = 0 || host->sd_error != 0))\n" "+\t\treturn sh_mmcif_error_manage(host);\n" "+\n" "+\thost->wait_int = 0;\n" @@ -418,11 +419,11 @@ "+\t\t\tsh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);\n" "+\t\t\t/* buf read enable */\n" "+\t\t\ttime = wait_event_interruptible_timeout(host->intr_wait,\n" - "+\t\t\t\thost->wait_int == 1 ||\n" - "+\t\t\t\thost->sd_error == 1, host->timeout);\n" + "+\t\t\t\thost->wait_int = 1 ||\n" + "+\t\t\t\thost->sd_error = 1, host->timeout);\n" "+\n" "+\t\t\tif (host->wait_int != 1 &&\n" - "+\t\t\t (time == 0 || host->sd_error != 0))\n" + "+\t\t\t (time = 0 || host->sd_error != 0))\n" "+\t\t\t\treturn sh_mmcif_error_manage(host);\n" "+\n" "+\t\t\thost->wait_int = 0;\n" @@ -447,9 +448,9 @@ "+\n" "+\t/* buf write enable */\n" "+\ttime = wait_event_interruptible_timeout(host->intr_wait,\n" - "+\t\t\thost->wait_int == 1 ||\n" - "+\t\t\thost->sd_error == 1, host->timeout);\n" - "+\tif (host->wait_int != 1 && (time == 0 || host->sd_error != 0))\n" + "+\t\t\thost->wait_int = 1 ||\n" + "+\t\t\thost->sd_error = 1, host->timeout);\n" + "+\tif (host->wait_int != 1 && (time = 0 || host->sd_error != 0))\n" "+\t\treturn sh_mmcif_error_manage(host);\n" "+\n" "+\thost->wait_int = 0;\n" @@ -462,9 +463,9 @@ "+\tsh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);\n" "+\n" "+\ttime = wait_event_interruptible_timeout(host->intr_wait,\n" - "+\t\t\thost->wait_int == 1 ||\n" - "+\t\t\thost->sd_error == 1, host->timeout);\n" - "+\tif (host->wait_int != 1 && (time == 0 || host->sd_error != 0))\n" + "+\t\t\thost->wait_int = 1 ||\n" + "+\t\t\thost->sd_error = 1, host->timeout);\n" + "+\tif (host->wait_int != 1 && (time = 0 || host->sd_error != 0))\n" "+\t\treturn sh_mmcif_error_manage(host);\n" "+\n" "+\thost->wait_int = 0;\n" @@ -487,11 +488,11 @@ "+\t\t\tsh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);\n" "+\t\t\t/* buf write enable*/\n" "+\t\t\ttime = wait_event_interruptible_timeout(host->intr_wait,\n" - "+\t\t\t\thost->wait_int == 1 ||\n" - "+\t\t\t\thost->sd_error == 1, host->timeout);\n" + "+\t\t\t\thost->wait_int = 1 ||\n" + "+\t\t\t\thost->sd_error = 1, host->timeout);\n" "+\n" "+\t\t\tif (host->wait_int != 1 &&\n" - "+\t\t\t (time == 0 || host->sd_error != 0))\n" + "+\t\t\t (time = 0 || host->sd_error != 0))\n" "+\t\t\t\treturn sh_mmcif_error_manage(host);\n" "+\n" "+\t\t\thost->wait_int = 0;\n" @@ -574,24 +575,24 @@ "+\t\t}\n" "+\t}\n" "+\t/* DWEN */\n" - "+\tif (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)\n" + "+\tif (opc = MMC_WRITE_BLOCK || opc = MMC_WRITE_MULTIPLE_BLOCK)\n" "+\t\ttmp |= CMD_SET_DWEN;\n" "+\t/* CMLTE/CMD12EN */\n" - "+\tif (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {\n" + "+\tif (opc = MMC_READ_MULTIPLE_BLOCK || opc = MMC_WRITE_MULTIPLE_BLOCK) {\n" "+\t\ttmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;\n" "+\t\tsh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,\n" "+\t\t\t\t\tmrq->data->blocks << 16);\n" "+\t}\n" "+\t/* RIDXC[1:0] check bits */\n" - "+\tif (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||\n" - "+\t opc == MMC_SEND_CSD || opc == MMC_SEND_CID)\n" + "+\tif (opc = MMC_SEND_OP_COND || opc = MMC_ALL_SEND_CID ||\n" + "+\t opc = MMC_SEND_CSD || opc = MMC_SEND_CID)\n" "+\t\ttmp |= CMD_SET_RIDXC_BITS;\n" "+\t/* RCRC7C[1:0] check bits */\n" - "+\tif (opc == MMC_SEND_OP_COND)\n" + "+\tif (opc = MMC_SEND_OP_COND)\n" "+\t\ttmp |= CMD_SET_CRC7C_BITS;\n" "+\t/* RCRC7C[1:0] internal CRC7 */\n" - "+\tif (opc == MMC_ALL_SEND_CID ||\n" - "+\t\topc == MMC_SEND_CSD || opc == MMC_SEND_CID)\n" + "+\tif (opc = MMC_ALL_SEND_CID ||\n" + "+\t\topc = MMC_SEND_CSD || opc = MMC_SEND_CID)\n" "+\t\ttmp |= CMD_SET_CRC7C_INTERNAL;\n" "+\n" "+\treturn opc = ((opc << 24) | tmp);\n" @@ -667,8 +668,8 @@ "+\tsh_mmcif_writel(host, MMCIF_CE_CMD_SET, opc);\n" "+\n" "+\ttime = wait_event_interruptible_timeout(host->intr_wait,\n" - "+\t\thost->wait_int == 1 || host->sd_error == 1, host->timeout);\n" - "+\tif (host->wait_int != 1 && time == 0) {\n" + "+\t\thost->wait_int = 1 || host->sd_error = 1, host->timeout);\n" + "+\tif (host->wait_int != 1 && time = 0) {\n" "+\t\tcmd->error = sh_mmcif_error_manage(host);\n" "+\t\treturn;\n" "+\t}\n" @@ -694,7 +695,7 @@ "+\t\thost->wait_int = 0;\n" "+\t\treturn;\n" "+\t}\n" - "+\tif (host->wait_int == 1) {\n" + "+\tif (host->wait_int = 1) {\n" "+\t\tsh_mmcif_get_response(host, cmd);\n" "+\t\thost->wait_int = 0;\n" "+\t}\n" @@ -703,8 +704,7 @@ "+\t\tif (ret < 0)\n" "+\t\t\tmrq->data->bytes_xfered = 0;\n" "+\t\telse\n" - "+\t\t\tmrq->data->bytes_xfered =\n" - "+\t\t\t\tmrq->data->blocks * mrq->data->blksz;\n" + "+\t\t\tmrq->data->bytes_xfered +\t\t\t\tmrq->data->blocks * mrq->data->blksz;\n" "+\t}\n" "+\tcmd->error = ret;\n" "+}\n" @@ -714,9 +714,9 @@ "+{\n" "+\tlong time;\n" "+\n" - "+\tif (mrq->cmd->opcode == MMC_READ_MULTIPLE_BLOCK)\n" + "+\tif (mrq->cmd->opcode = MMC_READ_MULTIPLE_BLOCK)\n" "+\t\tsh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);\n" - "+\telse if (mrq->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK)\n" + "+\telse if (mrq->cmd->opcode = MMC_WRITE_MULTIPLE_BLOCK)\n" "+\t\tsh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);\n" "+\telse {\n" "+\t\tpr_err(DRIVER_NAME\": not support stop cmd\\n\");\n" @@ -725,9 +725,9 @@ "+\t}\n" "+\n" "+\ttime = wait_event_interruptible_timeout(host->intr_wait,\n" - "+\t\t\thost->wait_int == 1 ||\n" - "+\t\t\thost->sd_error == 1, host->timeout);\n" - "+\tif (host->wait_int != 1 && (time == 0 || host->sd_error != 0)) {\n" + "+\t\t\thost->wait_int = 1 ||\n" + "+\t\t\thost->sd_error = 1, host->timeout);\n" + "+\tif (host->wait_int != 1 && (time = 0 || host->sd_error != 0)) {\n" "+\t\tcmd->error = sh_mmcif_error_manage(host);\n" "+\t\treturn;\n" "+\t}\n" @@ -776,13 +776,13 @@ "+\tstruct sh_mmcif_host *host = mmc_priv(mmc);\n" "+\tstruct sh_mmcif_plat_data *p = host->pd->dev.platform_data;\n" "+\n" - "+\tif (ios->power_mode == MMC_POWER_OFF) {\n" + "+\tif (ios->power_mode = MMC_POWER_OFF) {\n" "+\t\t/* clock stop */\n" "+\t\tsh_mmcif_clock_control(host, 0);\n" "+\t\tif (p->down_pwr)\n" "+\t\t\tp->down_pwr(host->pd);\n" "+\t\treturn;\n" - "+\t} else if (ios->power_mode == MMC_POWER_UP) {\n" + "+\t} else if (ios->power_mode = MMC_POWER_UP) {\n" "+\t\tif (p->set_pwr)\n" "+\t\t\tp->set_pwr(host->pd, ios->power_mode);\n" "+\t}\n" @@ -1068,4 +1068,4 @@ "-- \n" 1.7.0 -5483e20ff6be28bfc2b40d643f65dd09a58e184bc01a6d859e9bf62792b61820 +8702e12228fdd1061f8ef9240a2a621a0d4fb77cf8b36ed18017b8f943390acf
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