From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=37788 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1ONpeM-0000O9-QN for qemu-devel@nongnu.org; Sun, 13 Jun 2010 12:03:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1ONpeL-0000xp-I4 for qemu-devel@nongnu.org; Sun, 13 Jun 2010 12:03:06 -0400 Received: from mail-px0-f173.google.com ([209.85.212.173]:56863) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1ONpeL-0000xh-Df for qemu-devel@nongnu.org; Sun, 13 Jun 2010 12:03:05 -0400 Received: by pxi7 with SMTP id 7so1346818pxi.4 for ; Sun, 13 Jun 2010 09:03:04 -0700 (PDT) Sender: Richard Henderson Message-ID: <4C150120.2050600@twiddle.net> Date: Sun, 13 Jun 2010 09:02:40 -0700 From: Richard Henderson MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH 15/35] tcg-s390: Query instruction extensions that are installed. References: <1275678883-7082-1-git-send-email-rth@twiddle.net> <1275678883-7082-16-git-send-email-rth@twiddle.net> <20100610102815.GM26968@volta.aurel32.net> <4C1164ED.7020403@twiddle.net> <20100611080634.GP26968@volta.aurel32.net> <4C12368D.3050807@twiddle.net> <20100613104940.GA30341@volta.aurel32.net> In-Reply-To: <20100613104940.GA30341@volta.aurel32.net> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno Cc: qemu-devel@nongnu.org, agraf@suse.de On 06/13/2010 03:49 AM, Aurelien Jarno wrote: >> Also, what era is that second machine without highgprs? Is it running an >> old kernel, or a 32-bit kernel? > > I have very few infos about it, it's an IBM System z10 machine running a > 64-bit 2.6.26 kernel. Ah, I see it now: ea2a4d3a3a929ef494952bba57a0ef1a8a877881 [S390] 64-bit register support for 31-bit processes which adds a mechanism to pass the high parts of the gprs in the ucontext to the 31-bit signal handler, and adds a spot for them in the 31-bit core dump. It doesn't change the actual saving of registers within the kernel. Since we take asynchronous signals and return from them (as opposed to always longjmping out), we cannot use the full 64-bit register within a 31-bit process without having that bit set in HWCAP. Something to remember if we ever implement TCG for 31-bit mode. At the moment we only allow KVM in 31-bit mode. r~