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Date: Mon, 14 Jun 2010 13:08:37 -0700
From: "H. Peter Anvin" <hpa@zytor.com>
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To: Bjorn Helgaas <bjorn.helgaas@hp.com>
CC: Yinghai Lu <yinghai.lu@oracle.com>,
       Jesse Barnes <jbarnes@virtuousgeek.org>,
       Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@elte.hu>,
       Graham Ramsey <ramsey.graham@ntlworld.com>,
       linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
       Robert Richter <robert.richter@amd.com>,
       Harald Welte <HaraldWelte@viatech.com>,
       Joseph Chan <JosephChan@via.com.tw>, Jiri Slaby <jslaby@suse.cz>,
       Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>,
       Andrew Morton <akpm@linux-foundation.org>,
       Dominik Brodowski <linux@dominikbrodowski.net>
Subject: Re: [PATCH -v2] x86, pci: Handle fallout pci devices with peer root
 bus
References: <4BF40014.30303@ntlworld.com> <4C16777A.7060600@zytor.com> <4C167B30.2080307@oracle.com> <201006141400.22653.bjorn.helgaas@hp.com>
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On 06/14/2010 01:00 PM, Bjorn Helgaas wrote:
>>
>> the host bridges is on AMD CPUs, 
> 
> Don't confuse the HT host bridge with the PCI host bridge.  The HT I/O spec
> is quite clear that it uses "host bridge" to refer to the HT host bridge,
> i.e., the interface between CPUs and a HyperTransport link.
> 
> I agree that the *HT host bridge* is indeed on the AMD CPU.  But that is
> certainly not the same as the PCI host bridge that bridges between an HT
> link and a PCI bus.
> 
> See sections 4.9.4 (HT host bridge) and 7.4 (HT/PCI host bridge), for
> example.
> 

>>From a software point of view the latter is [largely] a PCI-to-PCI
bridge, though; it's not a root-level host bridge in the classical sense
(as noted in section 7.4).

Incidentally, in my copy of HT 3.10b, section 7.4 is marked
"HyperTransport Bridge Headers", and does not use the term "host bridge"
to refer to a secondary PCI bus.  Section 4.9.4 is simply marked "Host
Bridge".  As such, I think the HT spec is pretty consistent about
unambiguously referring to the HT host bridge when using the term "host
bridge".

	-hpa