diff for duplicates of <4C2DA889.5010809@samsung.com> diff --git a/a/1.1.hdr b/a/1.1.hdr deleted file mode 100644 index 8121da0..0000000 --- a/a/1.1.hdr +++ /dev/null @@ -1,2 +0,0 @@ -Content-type: text/plain; charset=EUC-KR -Content-transfer-encoding: 7BIT diff --git a/a/1.2.bin b/a/1.2.bin deleted file mode 100644 index 9d2e45a..0000000 --- a/a/1.2.bin +++ /dev/null @@ -1,3098 +0,0 @@ -<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"> -<html> -<head> - <meta content="text/html; charset=EUC-KR" http-equiv="Content-Type"> -</head> -<body bgcolor="#ffffff" text="#000000"> -this patch addes MIPI-DSI Driver.<br> -<br> -to use this driver, some structures below should be added to machine -specific file.<br> -<br> -struct dsim_config<br> -- define clock info, data lane count and video mode info for MIPI-DSI -Controller.<br> -<br> -struct dsim_lcd_config<br> -- define interface mode, channel ID, Pixel format and so on.<br> -<br> -struct s5p_platform_dsim<br> -- define callbacks for initializing D-PHY, MIPI reset and trigger -releated interfaces of s3c-fb.c file.<br> -<br> -Signed-off-by: InKi Dae <<a href="mailto:p.osciak@samsung.com">inki.dae@samsung.com</a>><br> -Signed-off-by: Kyungmin Park <<a - href="mailto:kyungmin.park@samsung.com">kyungmin.park@samsung.com</a>><br> ----<br> -<br> -<pre>diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h -index 2a25ab4..f716678 100644 ---- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h -+++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h -@@ -162,6 +162,7 @@ - - /* MIPI */ - #define S5P_MIPI_DPHY_EN (3) -+#define S5P_MIPI_M_RESETN (1 << 1) - - /* S5P_DAC_CONTROL */ - #define S5P_DAC_ENABLE (1) -diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile -index b1d82cc..3cd43f2 100644 ---- a/arch/arm/plat-samsung/Makefile -+++ b/arch/arm/plat-samsung/Makefile -@@ -49,6 +49,9 @@ obj-$(CONFIG_S3C_DEV_RTC) += dev-rtc.o - obj-$(CONFIG_SAMSUNG_DEV_ADC) += dev-adc.o - obj-$(CONFIG_SAMSUNG_DEV_TS) += dev-ts.o - -+# Device setup - MIPI-DSI -+obj-$(CONFIG_S5P_MIPI_DSI) += setup-dsim.o -+ - # DMA support - - obj-$(CONFIG_S3C_DMA) += dma.o -diff --git a/arch/arm/plat-samsung/include/plat/dsim.h b/arch/arm/plat-samsung/include/plat/dsim.h -new file mode 100644 -index 0000000..28bc595 ---- /dev/null -+++ b/arch/arm/plat-samsung/include/plat/dsim.h -@@ -0,0 +1,470 @@ -+/* linux/arm/arch/mach-s5pc110/include/mach/dsim.h -+ * -+ * Platform data header for Samsung MIPI-DSIM. -+ * -+ * Copyright (c) 2009 Samsung Electronics -+ * InKi Dae <a class="moz-txt-link-rfc2396E" href="mailto:inki.dae@samsung.com"><inki.dae@samsung.com></a> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+*/ -+ -+#ifndef _DSIM_H -+#define _DSIM_H -+ -+#include <linux/device.h> -+ -+/* h/w configuration */ -+#define MIPI_FIN 24000000 -+#define DSIM_TIMEOUT_MS 5000 -+#define DSIM_NO_OF_INTERRUPT 26 -+#define DSIM_PM_STABLE_TIME 10 -+ -+#define DSIM_TRUE 1 -+#define DSIM_FALSE 0 -+ -+#define DSIM_HEADER_FIFO_SZ 16 -+ -+enum dsim_interface_type { -+ DSIM_COMMAND = 0, -+ DSIM_VIDEO = 1, -+}; -+ -+enum dsim_state { -+ DSIM_STATE_RESET = 0, -+ DSIM_STATE_INIT = 1, -+ DSIM_STATE_STOP = 2, -+ DSIM_STATE_HSCLKEN = 3, -+ DSIM_STATE_ULPS = 4, -+}; -+ -+enum { -+ DSIM_NONE_STATE = 0, -+ DSIM_RESUME_COMPLETE = 1, -+ DSIM_FRAME_DONE = 2, -+}; -+ -+enum dsim_virtual_ch_no { -+ DSIM_VIRTUAL_CH_0 = 0, -+ DSIM_VIRTUAL_CH_1 = 1, -+ DSIM_VIRTUAL_CH_2 = 2, -+ DSIM_VIRTUAL_CH_3 = 3, -+}; -+ -+enum dsim_video_mode_type { -+ DSIM_NON_BURST_SYNC_EVENT = 0, -+ DSIM_NON_BURST_SYNC_PULSE = 2, -+ DSIM_BURST = 3, -+ DSIM_NON_VIDEO_MODE = 4, -+}; -+ -+enum dsim_fifo_state { -+ DSIM_RX_DATA_FULL = (1 << 25), -+ DSIM_RX_DATA_EMPTY = (1 << 24), -+ SFR_HEADER_FULL = (1 << 23), -+ SFR_HEADER_EMPTY = (1 << 22), -+ SFR_PAYLOAD_FULL = (1 << 21), -+ SFR_PAYLOAD_EMPTY = (1 << 20), -+ I80_HEADER_FULL = (1 << 19), -+ I80_HEADER_EMPTY = (1 << 18), -+ I80_PALOAD_FULL = (1 << 17), -+ I80_PALOAD_EMPTY = (1 << 16), -+ SUB_DISP_HEADER_FULL = (1 << 15), -+ SUB_DISP_HEADER_EMPTY = (1 << 14), -+ SUB_DISP_PAYLOAD_FULL = (1 << 13), -+ SUB_DISP_PAYLOAD_EMPTY = (1 << 12), -+ MAIN_DISP_HEADER_FULL = (1 << 11), -+ MAIN_DISP_HEADER_EMPTY = (1 << 10), -+ MAIN_DISP_PAYLOAD_FULL = (1 << 9), -+ MAIN_DISP_PAYLOAD_EMPTY = (1 << 8), -+}; -+ -+enum dsim_no_of_data_lane { -+ DSIM_DATA_LANE_1 = 0, -+ DSIM_DATA_LANE_2 = 1, -+ DSIM_DATA_LANE_3 = 2, -+ DSIM_DATA_LANE_4 = 3, -+}; -+ -+enum dsim_byte_clk_src { -+ DSIM_PLL_OUT_DIV8 = 0, -+ DSIM_EXT_CLK_DIV8 = 1, -+ DSIM_EXT_CLK_BYPASS = 2, -+}; -+ -+enum dsim_lane { -+ DSIM_LANE_DATA0 = (1 << 0), -+ DSIM_LANE_DATA1 = (1 << 1), -+ DSIM_LANE_DATA2 = (1 << 2), -+ DSIM_LANE_DATA3 = (1 << 3), -+ DSIM_LANE_DATA_ALL = 0xf, -+ DSIM_LANE_CLOCK = (1 << 4), -+ DSIM_LANE_ALL = DSIM_LANE_CLOCK | DSIM_LANE_DATA_ALL, -+}; -+ -+enum dsim_pixel_format { -+ DSIM_CMD_3BPP = 0, -+ DSIM_CMD_8BPP = 1, -+ DSIM_CMD_12BPP = 2, -+ DSIM_CMD_16BPP = 3, -+ DSIM_VID_16BPP_565 = 4, -+ DSIM_VID_18BPP_666PACKED = 5, -+ DSIM_18BPP_666LOOSELYPACKED = 6, -+ DSIM_24BPP_888 = 7, -+}; -+ -+enum dsim_lane_state { -+ DSIM_LANE_STATE_HS_READY, -+ DSIM_LANE_STATE_ULPS, -+ DSIM_LANE_STATE_STOP, -+ DSIM_LANE_STATE_LPDT, -+}; -+ -+enum dsim_transfer { -+ DSIM_TRANSFER_NEITHER = 0, -+ DSIM_TRANSFER_BYCPU = (1 << 7), -+ DSIM_TRANSFER_BYLCDC = (1 << 6), -+ DSIM_TRANSFER_BOTH = (0x3 << 6) -+}; -+ -+enum dsim_lane_change { -+ DSIM_NO_CHANGE = 0, -+ DSIM_DATA_LANE_CHANGE = 1, -+ DSIM_CLOCK_NALE_CHANGE = 2, -+ DSIM_ALL_LANE_CHANGE = 3, -+}; -+ -+enum dsim_int_src { -+ DSIM_ALL_OF_INTR = 0xffffffff, -+ DSIM_PLL_STABLE = (1 << 31), -+}; -+ -+enum dsim_data_id { -+ /* short packet types of packet types for command */ -+ GEN_SHORT_WR_NO_PARA = 0x03, -+ GEN_SHORT_WR_1_PARA = 0x13, -+ GEN_SHORT_WR_2_PARA = 0x23, -+ GEN_RD_NO_PARA = 0x04, -+ GEN_RD_1_PARA = 0x14, -+ GEN_RD_2_PARA = 0x24, -+ DCS_WR_NO_PARA = 0x05, -+ DCS_WR_1_PARA = 0x15, -+ DCS_RD_NO_PARA = 0x06, -+ SET_MAX_RTN_PKT_SIZE = 0x37, -+ -+ /* long packet types of packet types for command */ -+ NULL_PKT = 0x09, -+ BLANKING_PKT = 0x19, -+ GEN_LONG_WR = 0x29, -+ DCS_LONG_WR = 0x39, -+ -+ /* short packet types of generic command */ -+ CMD_OFF = 0x02, -+ CMD_ON = 0x12, -+ SHUT_DOWN = 0x22, -+ TURN_ON = 0x32, -+ -+ /* short packet types for video data */ -+ VSYNC_START = 0x01, -+ VSYNC_END = 0x11, -+ HSYNC_START = 0x21, -+ HSYNC_END = 0x31, -+ EOT_PKT = 0x08, -+ -+ /* long packet types for video data */ -+ RGB565_PACKED = 0x0e, -+ RGB666_PACKED = 0x1e, -+ RGB666_LOOSLY = 0x2e, -+ RGB888_PACKED = 0x3e, -+}; -+ -+/** -+ * struct dsim_config - interface for configuring mipi-dsi controller. -+ * -+ * @auto_flush: enable or disable Auto flush of MD FIFO using VSYNC pulse. -+ * @eot_disable: enable or disable EoT packet in HS mode. -+ * @auto_vertical_cnt: specifies auto vertical count mode. -+ * in Video mode, the vertical line transition uses line counter -+ * configured by VSA, VBP, and Vertical resolution. -+ * If this bit is set to '1', the line counter does not use VSA and VBP -+ * registers.(in command mode, this variable is ignored) -+ * @hse: set horizontal sync event mode. -+ * In VSYNC pulse and Vporch area, MIPI DSI master transfers only HSYNC -+ * start packet to MIPI DSI slave at MIPI DSI spec1.1r02. -+ * this bit transfers HSYNC end packet in VSYNC pulse and Vporch area -+ * (in mommand mode, this variable is ignored) -+ * @hfp: specifies HFP disable mode. -+ * if this variable is set, DSI master ignores HFP area in VIDEO mode. -+ * (in command mode, this variable is ignored) -+ * @hbp: specifies HBP disable mode. -+ * if this variable is set, DSI master ignores HBP area in VIDEO mode. -+ * (in command mode, this variable is ignored) -+ * @hsa: specifies HSA disable mode. -+ * if this variable is set, DSI master ignores HSA area in VIDEO mode. -+ * (in command mode, this variable is ignored) -+ * @e_no_data_lane: specifies data lane count to be used by Master. -+ * @e_byte_clk: select byte clock source. (it must be DSIM_PLL_OUT_DIV8) -+ * DSIM_EXT_CLK_DIV8 and DSIM_EXT_CLK_BYPASSS are not supported. -+ * @pll_stable_time: specifies the PLL Timer for stability of the ganerated -+ * clock(System clock cycle base) -+ * if the timer value goes to 0x00000000, the clock stable bit of status -+ * and interrupt register is set. -+ * @esc_clk: specifies escape clock frequency for getting the escape clock -+ * prescaler value. -+ * @stop_holding_cnt: specifies the interval value between transmitting -+ * read packet(or write "set_tear_on" command) and BTA request. -+ * after transmitting read packet or write "set_tear_on" command, -+ * BTA requests to D-PHY automatically. this counter value specifies -+ * the interval between them. -+ * @bta_timeout: specifies the timer for BTA. -+ * this register specifies time out from BTA request to change -+ * the direction with respect to Tx escape clock. -+ * @rx_timeout: specifies the timer for LP Rx mode timeout. -+ * this register specifies time out on how long RxValid deasserts, -+ * after RxLpdt asserts with respect to Tx escape clock. -+ * - RxValid specifies Rx data valid indicator. -+ * - RxLpdt specifies an indicator that D-PHY is under RxLpdt mode. -+ * - RxValid and RxLpdt specifies signal from D-PHY. -+ * @e_lane_swap: swaps Dp/Dn channel of Clock lane or Data lane. -+ * if this bit is set, Dp and Dn channel would be swapped each other. -+ */ -+struct dsim_config { -+ unsigned char auto_flush; -+ unsigned char eot_disable; -+ -+ unsigned char auto_vertical_cnt; -+ unsigned char hse; -+ unsigned char hfp; -+ unsigned char hbp; -+ unsigned char hsa; -+ -+ enum dsim_no_of_data_lane e_no_data_lane; -+ enum dsim_byte_clk_src e_byte_clk; -+ -+ /* -+ * =========================================== -+ * | P | M | S | MHz | -+ * ------------------------------------------- -+ * | 3 | 100 | 3 | 100 | -+ * | 3 | 100 | 2 | 200 | -+ * | 3 | 63 | 1 | 252 | -+ * | 4 | 100 | 1 | 300 | -+ * | 4 | 110 | 1 | 330 | -+ * | 12 | 350 | 1 | 350 | -+ * | 3 | 100 | 1 | 400 | -+ * | 4 | 150 | 1 | 450 | -+ * | 3 | 118 | 1 | 472 | -+ * | 12 | 250 | 0 | 500 | -+ * | 4 | 100 | 0 | 600 | -+ * | 3 | 81 | 0 | 648 | -+ * | 3 | 88 | 0 | 704 | -+ * | 3 | 90 | 0 | 720 | -+ * | 3 | 100 | 0 | 800 | -+ * | 12 | 425 | 0 | 850 | -+ * | 4 | 150 | 0 | 900 | -+ * | 12 | 475 | 0 | 950 | -+ * | 6 | 250 | 0 | 1000 | -+ * ------------------------------------------- -+ */ -+ unsigned char p; -+ unsigned short m; -+ unsigned char s; -+ -+ unsigned int pll_stable_time; -+ unsigned long esc_clk; -+ -+ unsigned short stop_holding_cnt; -+ unsigned char bta_timeout; -+ unsigned short rx_timeout; -+ enum dsim_video_mode_type e_lane_swap; -+}; -+ -+/** -+ * struct dsim_lcd_config - interface for configuring mipi-dsi based lcd panel. -+ * -+ * @e_interface: specifies interface to be used.(CPU or RGB interface) -+ * @parameter[0]: specifies virtual channel number -+ * that main or sub diaplsy uses. -+ * @parameter[1]: specifies pixel stream format for main or sub display. -+ * @parameter[2]: selects Burst mode in Video mode. -+ * in Non-burst mode, RGB data area is filled with RGB data and NULL -+ * packets, according to input bandwidth of RGB interface. -+ * In Burst mode, RGB data area is filled with RGB data only. -+ * @lcd_panel_info: pointer for lcd panel specific structure. -+ * this structure specifies width, height, timing and polarity and so on. -+ * @mipi_ddi_pd: pointer for lcd panel platform data. -+ */ -+struct dsim_lcd_config { -+ enum dsim_interface_type e_interface; -+ unsigned int parameter[3]; -+ -+ void *lcd_panel_info; -+ void *mipi_ddi_pd; -+}; -+ -+struct dsim_global; -+struct fb_info; -+ -+/** -+ * struct s5p_platform_dsim - interface to platform data for mipi-dsi driver. -+ * -+ * @clk_name: specifies clock name for mipi-dsi. -+ * @lcd_panel_name: specifies lcd panel name registered to mipi-dsi driver. -+ * lcd panel driver searched would be actived. -+ * @platfrom_rev: specifies platform revision number. -+ * revision number should become 1. -+ * @dsim_config: pointer of structure for configuring mipi-dsi controller. -+ * @dsim_lcd_info: pointer to structure for configuring -+ * mipi-dsi based lcd panel. -+ * @mipi_power: callback pointer for enabling or disabling mipi power. -+ * @part_reset: callback pointer for reseting mipi phy. -+ * @init_d_phy: callback pointer for enabing d_phy of dsi master. -+ * @get_fb_frame_done: callback pointer for getting frame done status of the -+ * display controller(FIMD). -+ * @trigger: callback pointer for triggering display controller(FIMD) -+ * in case of CPU mode. -+ * @delay_for_stabilization: specifies stable time. -+ * this delay needs when writing data on SFR -+ * after mipi mode became LP mode. -+ */ -+struct s5p_platform_dsim { -+ char *clk_name; -+ char lcd_panel_name[64]; -+ unsigned int platform_rev; -+ -+ struct dsim_config *dsim_info; -+ struct dsim_lcd_config *dsim_lcd_info; -+ -+ unsigned int delay_for_stabilization; -+ -+ int (*mipi_power) (struct dsim_global *dsim, void *p_mipi_1_1v, -+ void *p_mipi_1_8v, int enable); -+ int (*part_reset) (struct dsim_global *dsim); -+ int (*init_d_phy) (struct dsim_global *dsim); -+ int (*get_fb_frame_done) (struct fb_info *info); -+ void (*trigger) (struct fb_info *info); -+}; -+ -+/** -+ * struct dsim_global - global interface for mipi-dsi driver. -+ * -+ * @dev: driver model representation of the device. -+ * @clock: pointer to MIPI-DSI clock of clock framework. -+ * @irq: interrupt number to MIPI-DSI controller. -+ * @reg_base: base address to memory mapped SRF of MIPI-DSI controller. -+ * (virtual address) -+ * @r_mipi_1_1v: pointer to regulator for MIPI 1.1v power. -+ * @r_mipi_1_8v: pointer to regulator for MIPI 1.8v power. -+ * @pd: pointer to MIPI-DSI driver platform data. -+ * @dsim_lcd_info: pointer to structure for configuring -+ * mipi-dsi based lcd panel. -+ * @lcd_panel_info: pointer for lcd panel specific structure. -+ * this structure specifies width, height, timing and polarity and so on. -+ * @mipi_ddi_pd: pointer for lcd panel platform data. -+ * @mipi_drv: pointer to driver structure for mipi-dsi based lcd panel. -+ * @s3cfb_notif: kernel notifier structure to be registered -+ * by device specific framebuffer driver. -+ * this notifier could be used by fb_blank of device specifiec -+ * framebuffer driver. -+ * @state: specifies status of MIPI-DSI controller. -+ * the status could be RESET, INIT, STOP, HSCLKEN and ULPS. -+ * @data_lane: specifiec enabled data lane number. -+ * this variable would be set by driver according to e_no_data_lane -+ * automatically. -+ * @e_clk_src: select byte clock source. -+ * this variable would be set by driver according to e_byte_clock -+ * automatically. -+ * @hs_clk: HS clock rate. -+ * this variable would be set by driver automatically. -+ * @byte_clk: Byte clock rate. -+ * this variable would be set by driver automatically. -+ * @escape_clk: ESCAPE clock rate. -+ * this variable would be set by driver automatically. -+ * @freq_band: indicates Bitclk frequency band for D-PHY global timing. -+ * Serial Clock(=ByteClk X 8) FreqBand[3:0] -+ * ~ 99.99 MHz 0000 -+ * 100 ~ 119.99 MHz 0001 -+ * 120 ~ 159.99 MHz 0010 -+ * 160 ~ 199.99 MHz 0011 -+ * 200 ~ 239.99 MHz 0100 -+ * 140 ~ 319.99 MHz 0101 -+ * 320 ~ 389.99 MHz 0110 -+ * 390 ~ 449.99 MHz 0111 -+ * 450 ~ 509.99 MHz 1000 -+ * 510 ~ 559.99 MHz 1001 -+ * 560 ~ 639.99 MHz 1010 -+ * 640 ~ 689.99 MHz 1011 -+ * 690 ~ 769.99 MHz 1100 -+ * 770 ~ 869.99 MHz 1101 -+ * 870 ~ 949.99 MHz 1110 -+ * 950 ~ 1000 MHz 1111 -+ * this variable would be calculated by driver automatically. -+ * -+ * @header_fifo_index: specifies header fifo index. -+ * this variable is not used yet. -+ */ -+struct dsim_global { -+ struct device *dev; -+ struct clk *clock; -+ unsigned int irq; -+ unsigned int reg_base; -+ -+ struct regulator *r_mipi_1_1v; -+ struct regulator *r_mipi_1_8v; -+ -+ struct s5p_platform_dsim *pd; -+ struct dsim_config *dsim_info; -+ struct dsim_lcd_config *dsim_lcd_info; -+ struct fb_videomode *lcd_panel_info; -+ struct mipi_ddi_platform_data *mipi_ddi_pd; -+ struct mipi_lcd_driver *mipi_drv; -+ struct notifier_block s3cfb_notif; -+ -+ unsigned char state; -+ unsigned int data_lane; -+ enum dsim_byte_clk_src e_clk_src; -+ unsigned long hs_clk; -+ unsigned long byte_clk; -+ unsigned long escape_clk; -+ unsigned char freq_band; -+ -+ char header_fifo_index[DSIM_HEADER_FIFO_SZ]; -+}; -+ -+/* -+ * driver structure for mipi-dsi based lcd panel. -+ * -+ * this structure should be registered by lcd panel driver. -+ * mipi-dsi driver seeks lcd panel registered through name field -+ * and calls these callback functions in appropriate time. -+ */ -+struct mipi_lcd_driver { -+ s8 name[64]; -+ -+ s32 (*init)(struct device *dev); -+ void (*display_on)(struct device *dev); -+ s32 (*set_link)(struct mipi_ddi_platform_data *pd); -+ s32 (*probe)(struct device *dev); -+ s32 (*remove)(struct device *dev); -+ void (*shutdown)(struct device *dev); -+ s32 (*suspend)(struct device *dev, pm_message_t mesg); -+ s32 (*resume)(struct device *dev); -+}; -+ -+/* -+ * register mipi_lcd_driver object defined by lcd panel driver -+ * to mipi-dsi driver. -+ */ -+extern int s5p_dsim_register_lcd_driver(struct mipi_lcd_driver *lcd_drv); -+ -+/* reset MIPI PHY through MIPI PHY CONTROL REGISTER. */ -+extern int s5p_dsim_part_reset(struct dsim_global *dsim); -+/* enable MIPI D-PHY and DSI Master block. */ -+extern int s5p_dsim_init_d_phy(struct dsim_global *dsim); -+ -+/* enable regulators to MIPI-DSI power. */ -+extern int s5p_dsim_mipi_power(struct dsim_global *dsim, void *p_mipi_1_1v, -+ void *p_mipi_1_8v, int enable); -+ -+#endif /* _DSIM_H */ -diff --git a/arch/arm/plat-samsung/include/plat/mipi_ddi.h b/arch/arm/plat-samsung/include/plat/mipi_ddi.h -new file mode 100644 -index 0000000..57ed613 ---- /dev/null -+++ b/arch/arm/plat-samsung/include/plat/mipi_ddi.h -@@ -0,0 +1,98 @@ -+/* linux/arm/arch/mach-s5pc110/include/mach/mipi_ddi.h -+ * -+ * definitions for DDI based MIPI-DSI. -+ * -+ * Copyright (c) 2009 Samsung Electronics -+ * InKi Dae <a class="moz-txt-link-rfc2396E" href="mailto:inki.dae@samsung.com"><inki.dae@samsung.com></a> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+*/ -+ -+#ifndef _MIPI_DDI_H -+#define _MIPI_DDI_H -+ -+enum mipi_ddi_interface { -+ RGB_IF = 0x4000, -+ I80_IF = 0x8000, -+ YUV_601 = 0x10000, -+ YUV_656 = 0x20000, -+ MIPI_VIDEO = 0x1000, -+ MIPI_COMMAND = 0x2000, -+}; -+ -+enum mipi_ddi_panel_select { -+ DDI_MAIN_LCD = 0, -+ DDI_SUB_LCD = 1, -+}; -+ -+enum mipi_ddi_model { -+ S6DR117 = 0, -+}; -+ -+enum mipi_ddi_parameter { -+ /* DSIM video interface parameter */ -+ DSI_VIRTUAL_CH_ID = 0, -+ DSI_FORMAT = 1, -+ DSI_VIDEO_MODE_SEL = 2, -+}; -+ -+struct lcd_device; -+struct fb_info; -+ -+struct mipi_ddi_platform_data { -+ void *dsim_data; -+ /* -+ * it is used for command mode lcd panel and -+ * when all contents of framebuffer in panel module are transfered -+ * to lcd panel it occurs te signal. -+ * -+ * note: -+ * - in case of command mode(cpu mode), it should be triggered only -+ * when TE signal of lcd panel and frame done interrupt of display -+ * controller or mipi controller occurs. -+ */ -+ unsigned int te_irq; -+ -+ /* -+ * it is used for PM stable time at te interrupt handler and -+ * could be used according to lcd panel characteristic or not. -+ */ -+ unsigned int resume_complete; -+ -+ int (*lcd_reset) (struct lcd_device *ld); -+ int (*lcd_power_on) (struct lcd_device *ld, int enable); -+ int (*backlight_on) (int enable); -+ -+ /* transfer command to lcd panel at LP mode. */ -+ int (*cmd_write) (void *dsim_data, unsigned int data_id, -+ unsigned int data0, unsigned int data1); -+ int (*cmd_read) (void *dsim_data, unsigned int data_id, -+ unsigned int data0, unsigned int data1); -+ /* -+ * get the status that all screen data have been transferred -+ * to mipi-dsi. -+ */ -+ int (*get_dsim_frame_done) (void *dsim_data); -+ int (*clear_dsim_frame_done) (void *dsim_data); -+ -+ /* -+ * changes mipi transfer mode to LP or HS mode. -+ * -+ * LP mode needs when some commands like gamma values transfers -+ * to lcd panel. -+ */ -+ int (*change_dsim_transfer_mode) (int mode); -+ -+ /* get frame done status of display controller. */ -+ int (*get_fb_frame_done) (struct fb_info *info); -+ /* trigger display controller in case of cpu mode. */ -+ void (*trigger) (struct fb_info *info); -+ -+ unsigned int reset_delay; -+ unsigned int power_on_delay; -+ unsigned int power_off_delay; -+}; -+ -+#endif /* _MIPI_DDI_H */ -diff --git a/arch/arm/plat-samsung/include/plat/regs-dsim.h b/arch/arm/plat-samsung/include/plat/regs-dsim.h -new file mode 100644 -index 0000000..dc83089 ---- /dev/null -+++ b/arch/arm/plat-samsung/include/plat/regs-dsim.h -@@ -0,0 +1,281 @@ -+/* linux/arch/arm/plat-s5pc11x/include/plat/regs-dsim.h -+ * -+ * Register definition file for Samsung MIPI-DSIM driver -+ * -+ * InKi Dae <a class="moz-txt-link-rfc2396E" href="mailto:inki.dae@samsung.com"><inki.dae@samsung.com></a>, Copyright (c) 2009 Samsung Electronics -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+*/ -+ -+#ifndef _REGS_DSIM_H -+#define _REGS_DSIM_H -+ -+#define S5P_DSIM_STATUS (0x0) /* Status register */ -+#define S5P_DSIM_SWRST (0x4) /* Software reset register */ -+#define S5P_DSIM_CLKCTRL (0x8) /* Clock control register */ -+#define S5P_DSIM_TIMEOUT (0xc) /* Time out register */ -+#define S5P_DSIM_CONFIG (0x10) /* Configuration register */ -+#define S5P_DSIM_ESCMODE (0x14) /* Escape mode register */ -+ -+/* Main display image resolution register */ -+#define S5P_DSIM_MDRESOL (0x18) -+#define S5P_DSIM_MVPORCH (0x1c) /* Main display Vporch register */ -+#define S5P_DSIM_MHPORCH (0x20) /* Main display Hporch register */ -+#define S5P_DSIM_MSYNC (0x24) /* Main display sync area register */ -+ -+/* Sub display image resolution register */ -+#define S5P_DSIM_SDRESOL (0x28) -+#define S5P_DSIM_INTSRC (0x2c) /* Interrupt source register */ -+#define S5P_DSIM_INTMSK (0x30) /* Interrupt mask register */ -+#define S5P_DSIM_PKTHDR (0x34) /* Packet Header FIFO register */ -+#define S5P_DSIM_PAYLOAD (0x38) /* Payload FIFO register */ -+#define S5P_DSIM_RXFIFO (0x3c) /* Read FIFO register */ -+#define S5P_DSIM_FIFOTHLD (0x40) /* FIFO threshold level register */ -+#define S5P_DSIM_FIFOCTRL (0x44) /* FIFO status and control register */ -+ -+/* FIFO memory AC characteristic register */ -+#define S5P_DSIM_MEMACCHR (0x48) -+#define S5P_DSIM_PLLCTRL (0x4c) /* PLL control register */ -+#define S5P_DSIM_PLLTMR (0x50) /* PLL timer register */ -+#define S5P_DSIM_PHYACCHR (0x54) /* D-PHY AC characteristic register */ -+#define S5P_DSIM_PHYACCHR1 (0x58) /* D-PHY AC characteristic register1 */ -+ -+/* DSIM_SWRST */ -+#define DSIM_FUNCRST (1 << 16) -+#define DSIM_SWRST (1 << 0) -+ -+/* S5P_DSIM_TIMEOUT */ -+#define DSIM_LPDR_TOUT_SHIFT (0) -+#define DSIM_BTA_TOUT_SHIFT (16) -+#define DSIM_LPDR_TOUT(x) (((x) & 0xffff) << DSIM_LPDR_TOUT_SHIFT) -+#define DSIM_BTA_TOUT(x) (((x) & 0xff) << DSIM_BTA_TOUT_SHIFT) -+ -+/* S5P_DSIM_CLKCTRL */ -+#define DSIM_ESC_PRESCALER_SHIFT (0) -+#define DSIM_LANE_ESC_CLKEN_SHIFT (19) -+#define DSIM_BYTE_CLKEN_SHIFT (24) -+#define DSIM_BYTE_CLK_SRC_SHIFT (25) -+#define DSIM_PLL_BYPASS_SHIFT (27) -+#define DSIM_ESC_CLKEN_SHIFT (28) -+#define DSIM_TX_REQUEST_HSCLK_SHIFT (31) -+#define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << \ -+ DSIM_ESC_PRESCALER_SHIFT) -+#define DSIM_LANE_ESC_CLKEN(x) (((x) & 0x1f) << \ -+ DSIM_LANE_ESC_CLKEN_SHIFT) -+#define DSIM_BYTE_CLK_ENABLE (1 << DSIM_BYTE_CLKEN_SHIFT) -+#define DSIM_BYTE_CLK_DISABLE (0 << DSIM_BYTE_CLKEN_SHIFT) -+#define DSIM_BYTE_CLKSRC(x) (((x) & 0x3) << DSIM_BYTE_CLK_SRC_SHIFT) -+#define DSIM_PLL_BYPASS_PLL (0 << DSIM_PLL_BYPASS_SHIFT) -+#define DSIM_PLL_BYPASS_EXTERNAL (1 << DSIM_PLL_BYPASS_SHIFT) -+#define DSIM_ESC_CLKEN_ENABLE (1 << DSIM_ESC_CLKEN_SHIFT) -+#define DSIM_ESC_CLKEN_DISABLE (0 << DSIM_ESC_CLKEN_SHIFT) -+ -+/* S5P_DSIM_CONFIG */ -+#define DSIM_LANE_EN_SHIFT (0) -+#define DSIM_NUM_OF_DATALANE_SHIFT (5) -+#define DSIM_SUB_PIX_FORMAT_SHIFT (8) -+#define DSIM_MAIN_PIX_FORMAT_SHIFT (12) -+#define DSIM_SUB_VC_SHIFT (16) -+#define DSIM_MAIN_VC_SHIFT (18) -+#define DSIM_HSA_MODE_SHIFT (20) -+#define DSIM_HBP_MODE_SHIFT (21) -+#define DSIM_HFP_MODE_SHIFT (22) -+#define DSIM_HSE_MODE_SHIFT (23) -+#define DSIM_AUTO_MODE_SHIFT (24) -+#define DSIM_VIDEO_MODE_SHIFT (25) -+#define DSIM_BURST_MODE_SHIFT (26) -+#define DSIM_SYNC_INFORM_SHIFT (27) -+#define DSIM_EOT_R03_SHIFT (28) -+#define DSIM_LANE_ENx(x) ((1) << x) -+ -+/* in case of Gemunus, it should be 0x1. */ -+#define DSIM_NUM_OF_DATA_LANE(x) ((x) << 5) -+#define DSIM_SUB_PIX_FORMAT_3BPP (0 << 8) /* command mode only */ -+#define DSIM_SUB_PIX_FORMAT_8BPP (1 << 8) /* command mode only */ -+#define DSIM_SUB_PIX_FORMAT_12BPP (2 << 8) /* command mode only */ -+#define DSIM_SUB_PIX_FORMAT_16BPP (3 << 8) /* command mode only */ -+#define DSIM_SUB_PIX_FORMAT_16BPP_RGB (4 << 8) /* video mode only */ -+#define DSIM_SUB_PIX_FORMAT_18BPP_PRGB (5 << 8) /* video mode only */ -+#define DSIM_SUB_PIX_FORMAT_18BPP_LRGB (6 << 8) /* common */ -+#define DSIM_SUB_PIX_FORMAT_24BPP_RGB (7 << 8) /* common */ -+#define DSIM_MAIN_PIX_FORMAT_3BPP (0 << 12) /* command mode only */ -+#define DSIM_MAIN_PIX_FORMAT_8BPP (1 << 12) /* command mode only */ -+#define DSIM_MAIN_PIX_FORMAT_12BPP (2 << 12) /* command mode only */ -+#define DSIM_MAIN_PIX_FORMAT_16BPP (3 << 12) /* command mode only */ -+#define DSIM_MAIN_PIX_FORMAT_16BPP_RGB (4 << 12) /* video mode only */ -+#define DSIM_MAIN_PIX_FORMAT_18BPP_PRGB (5 << 12) /* video mode only */ -+#define DSIM_MAIN_PIX_FORMAT_18BPP_LRGB (6 << 12) /* common */ -+#define DSIM_MAIN_PIX_FORMAT_24BPP_RGB (7 << 12) /* common */ -+ -+/* Virtual channel number for sub display */ -+#define DSIM_SUB_VC(x) (((x) & 0x3) << 16) -+/* Virtual channel number for main display */ -+#define DSIM_MAIN_VC(x) (((x) & 0x3) << 18) -+#define DSIM_HSA_MODE_ENABLE (1 << 20) -+#define DSIM_HSA_MODE_DISABLE (0 << 20) -+#define DSIM_HBP_MODE_ENABLE (1 << 21) -+#define DSIM_HBP_MODE_DISABLE (0 << 21) -+#define DSIM_HFP_MODE_ENABLE (1 << 22) -+#define DSIM_HFP_MODE_DISABLE (0 << 22) -+#define DSIM_HSE_MODE_ENABLE (1 << 23) -+#define DSIM_HSE_MODE_DISABLE (0 << 23) -+#define DSIM_AUTO_MODE (1 << 24) -+#define DSIM_CONFIGURATION_MODE (0 << 24) -+#define DSIM_VIDEO_MODE (1 << 25) -+#define DSIM_COMMAND_MODE (0 << 25) -+#define DSIM_BURST_MODE (1 << 26) -+#define DSIM_NON_BURST_MODE (0 << 26) -+#define DSIM_SYNC_INFORM_PULSE (1 << 27) -+#define DSIM_SYNC_INFORM_EVENT (0 << 27) -+/* enable EoT packet generation for V1.01r11 */ -+#define DSIM_EOT_R03_ENABLE (0 << 28) -+/* disable EoT packet generation for V1.01r03 */ -+#define DSIM_EOT_R03_DISABLE (1 << 28) -+ -+/* S5P_DSIM_ESCMODE */ -+#define DSIM_STOP_STATE_CNT_SHIFT (21) -+#define DSIM_STOP_STATE_CNT(x) (((x) & 0x3ff) << \ -+ DSIM_STOP_STATE_CNT_SHIFT) -+#define DSIM_FORCE_STOP_STATE_SHIFT (20) -+#define DSIM_FORCE_BTA_SHIFT (16) -+#define DSIM_CMD_LPDT_HS_MODE (0 << 7) -+#define DSIM_CMD_LPDT_LP_MODE (1 << 7) -+#define DSIM_TX_LPDT_HS_MODE (0 << 6) -+#define DSIM_TX_LPDT_LP_MODE (1 << 6) -+#define DSIM_TX_TRIGGER_RST_SHIFT (4) -+#define DSIM_TX_UIPS_DAT_SHIFT (3) -+#define DSIM_TX_UIPS_EXIT_SHIFT (2) -+#define DSIM_TX_UIPS_CLK_SHIFT (1) -+#define DSIM_TX_UIPS_CLK_EXIT_SHIFT (0) -+ -+/* S5P_DSIM_MDRESOL */ -+#define DSIM_MAIN_STAND_BY (1 << 31) -+#define DSIM_MAIN_NOT_READY (0 << 31) -+#define DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16) -+#define DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0) -+ -+/* S5P_DSIM_MVPORCH */ -+#define DSIM_CMD_ALLOW_SHIFT (28) -+#define DSIM_STABLE_VFP_SHIFT (16) -+#define DSIM_MAIN_VBP_SHIFT (0) -+#define DSIM_CMD_ALLOW_MASK (0xf << DSIM_CMD_ALLOW_SHIFT) -+#define DSIM_STABLE_VFP_MASK (0x7ff << DSIM_STABLE_VFP_SHIFT) -+#define DSIM_MAIN_VBP_MASK (0x7ff << DSIM_MAIN_VBP_SHIFT) -+#define DSIM_CMD_ALLOW(x) (((x) & 0xf) << DSIM_CMD_ALLOW_SHIFT) -+#define DSIM_STABLE_VFP(x) (((x) & 0x7ff) << DSIM_STABLE_VFP_SHIFT) -+#define DSIM_MAIN_VBP(x) (((x) & 0x7ff) << DSIM_MAIN_VBP_SHIFT) -+ -+/* S5P_DSIM_MHPORCH */ -+#define DSIM_MAIN_HFP_SHIFT (16) -+#define DSIM_MAIN_HBP_SHIFT (0) -+#define DSIM_MAIN_HFP_MASK ((0xffff) << DSIM_MAIN_HFP_SHIFT) -+#define DSIM_MAIN_HBP_MASK ((0xffff) << DSIM_MAIN_HBP_SHIFT) -+#define DSIM_MAIN_HFP(x) (((x) & 0xffff) << DSIM_MAIN_HFP_SHIFT) -+#define DSIM_MAIN_HBP(x) (((x) & 0xffff) << DSIM_MAIN_HBP_SHIFT) -+ -+/* S5P_DSIM_MSYNC */ -+#define DSIM_MAIN_VSA_SHIFT (22) -+#define DSIM_MAIN_HSA_SHIFT (0) -+#define DSIM_MAIN_VSA_MASK ((0x3ff) << DSIM_MAIN_VSA_SHIFT) -+#define DSIM_MAIN_HSA_MASK ((0xffff) << DSIM_MAIN_HSA_SHIFT) -+#define DSIM_MAIN_VSA(x) (((x) & 0x3ff) << DSIM_MAIN_VSA_SHIFT) -+#define DSIM_MAIN_HSA(x) (((x) & 0xffff) << DSIM_MAIN_HSA_SHIFT) -+ -+/* S5P_DSIM_SDRESOL */ -+#define DSIM_SUB_STANDY_SHIFT (31) -+#define DSIM_SUB_VRESOL_SHIFT (16) -+#define DSIM_SUB_HRESOL_SHIFT (0) -+#define DSIM_SUB_STANDY_MASK ((0x1) << DSIM_SUB_STANDY_SHIFT) -+#define DSIM_SUB_VRESOL_MASK ((0x7ff) << DSIM_SUB_VRESOL_SHIFT) -+#define DSIM_SUB_HRESOL_MASK ((0x7ff) << DSIM_SUB_HRESOL_SHIFT) -+#define DSIM_SUB_STANDY (1 << DSIM_SUB_STANDY_SHIFT) -+#define DSIM_SUB_NOT_READY (0 << DSIM_SUB_STANDY_SHIFT) -+#define DSIM_SUB_VRESOL(x) (((x) & 0x7ff) << DSIM_SUB_VRESOL_SHIFT) -+#define DSIM_SUB_HRESOL(x) (((x) & 0x7ff) << DSIM_SUB_HRESOL_SHIFT) -+ -+/* S5P_DSIM_INTSRC */ -+#define INTSRC_ERR_CONTENT_LP1 (1 << 0) -+#define INTSRC_ERR_CONTENT_LP0 (1 << 1) -+#define INTSRC_ERR_CONTROL0 (1 << 2) -+#define INTSRC_ERR_CONTROL1 (1 << 3) -+#define INTSRC_ERR_CONTROL2 (1 << 4) -+#define INTSRC_ERR_CONTROL3 (1 << 5) -+#define INTSRC_ERR_SYNC0 (1 << 6) -+#define INTSRC_ERR_SYNC1 (1 << 7) -+#define INTSRC_ERR_SYNC2 (1 << 8) -+#define INTSRC_ERR_SYNC3 (1 << 9) -+#define INTSRC_ERR_ESC0 (1 << 10) -+#define INTSRC_ERR_ESC1 (1 << 11) -+#define INTSRC_ERR_ESC2 (1 << 12) -+#define INTSRC_ERR_ESC3 (1 << 13) -+#define INTSRC_ERR_RX_CRC (1 << 14) -+#define INTSRC_ERR_RX_ECC (1 << 15) -+#define INTSRC_RX_ACK (1 << 16) -+#define INTSRC_RX_TE (1 << 17) -+#define INTSRC_RX_DAT_DONE (1 << 18) -+#define INTSRC_TA_TOUT (1 << 20) -+#define INTSRC_LPDR_TOUT (1 << 21) -+#define INTSRC_FRAME_DONE (1 << 24) -+#define INTSRC_BUS_TURN_OVER (1 << 25) -+#define INTSRC_SYNC_OVERRIDE (1 << 28) -+#define INTSRC_SFR_FIFO_EMPTY (1 << 29) -+#define INTSRC_SW_RST_RELEASE (1 << 30) -+#define INTSRC_PLL_STABLE (1 << 31) -+ -+/* S5P_DSIM_INTMSK */ -+#define INTMSK_ERR_CONTENT_LP1 (1 << 0) -+#define INTMSK_ERR_CONTENT_LP0 (1 << 1) -+#define INTMSK_ERR_CONTROL0 (1 << 2) -+#define INTMSK_ERR_CONTROL1 (1 << 3) -+#define INTMSK_ERR_CONTROL2 (1 << 4) -+#define INTMSK_ERR_CONTROL3 (1 << 5) -+#define INTMSK_ERR_SYNC0 (1 << 6) -+#define INTMSK_ERR_SYNC1 (1 << 7) -+#define INTMSK_ERR_SYNC2 (1 << 8) -+#define INTMSK_ERR_SYNC3 (1 << 9) -+#define INTMSK_ERR_ESC0 (1 << 10) -+#define INTMSK_ERR_ESC1 (1 << 11) -+#define INTMSK_ERR_ESC2 (1 << 12) -+#define INTMSK_ERR_ESC3 (1 << 13) -+#define INTMSK_ERR_RX_CRC (1 << 14) -+#define INTMSK_ERR_RX_ECC (1 << 15) -+#define INTMSK_RX_ACK (1 << 16) -+#define INTMSK_RX_TE (1 << 17) -+#define INTMSK_RX_DAT_DONE (1 << 18) -+#define INTMSK_TA_TOUT (1 << 20) -+#define INTMSK_LPDR_TOUT (1 << 21) -+#define INTMSK_FRAME_DONE (1 << 24) -+#define INTMSK_BUS_TURN_OVER (1 << 25) -+#define INTMSK_SFR_FIFO_EMPTY (1 << 29) -+#define INTMSK_SW_RST_RELEASE (1 << 30) -+#define INTMSK_PLL_STABLE (1 << 31) -+ -+/* S5P_DSIM_PKTHDR */ -+#define DSIM_PACKET_HEADER_DI(x) (((x) & 0xff) << 0) -+/* Word count lower byte for long packet */ -+#define DSIM_PACKET_HEADER_DAT0(x) (((x) & 0xff) << 8) -+/* Word count upper byte for long packet */ -+#define DSIM_PACKET_HEADER_DAT1(x) (((x) & 0xff) << 16) -+ -+/* S5P_DSIM_FIFOCTRL */ -+#define DSIM_RX_FIFO (1 << 4) -+#define DSIM_TX_SFR_FIFO (1 << 3) -+#define DSIM_I80_FIFO (1 << 2) -+#define DSIM_SUB_DISP_FIFO (1 << 1) -+#define DSIM_MAIN_DISP_FIFO (1 << 0) -+ -+/* S5P_DSIM_PHYACCHR */ -+#define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) -+#define DSIM_AFC_ENABLE (1 << 14) -+#define DSIM_AFC_DISABLE (0 << 14) -+ -+/* S5P_DSIM_PLLCTRL */ -+#define DSIM_PMS_SHIFT (1) -+#define DSIM_PLL_EN_SHIFT (23) -+#define DSIM_FREQ_BAND_SHIFT (24) -+#define DSIM_PMS(x) (((x) & 0x7ffff) << DSIM_PMS_SHIFT) -+#define DSIM_FREQ_BAND(x) (((x) & 0xf) << DSIM_FREQ_BAND_SHIFT) -+ -+#endif /* _REGS_DSIM_H */ -diff --git a/arch/arm/plat-samsung/setup-dsim.c b/arch/arm/plat-samsung/setup-dsim.c -new file mode 100644 -index 0000000..833ade2 ---- /dev/null -+++ b/arch/arm/plat-samsung/setup-dsim.c -@@ -0,0 +1,161 @@ -+/* -+ * S5PC110 MIPI-DSIM driver. -+ * -+ * Author: InKi Dae <a class="moz-txt-link-rfc2396E" href="mailto:inki.dae@samsung.com"><inki.dae@samsung.com></a> -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ */ -+#include <linux/kernel.h> -+#include <linux/string.h> -+#include <linux/io.h> -+#include <linux/err.h> -+#include <linux/platform_device.h> -+#include <linux/clk.h> -+#include <linux/regulator/consumer.h> -+ -+#include <mach/map.h> -+#include <mach/regs-clock.h> -+ -+#include <plat/dsim.h> -+#include <plat/clock.h> -+#include <plat/regs-dsim.h> -+ -+static int s5p_dsim_enable_d_phy(struct dsim_global *dsim, unsigned int enable) -+{ -+ unsigned int reg; -+ -+ if (dsim == NULL) { -+ printk(KERN_ERR "dsim is NULL.\n"); -+ return -EFAULT; -+ } -+ -+ reg = (readl(S5P_MIPI_CONTROL)) & ~(1 << 0); -+ reg |= (enable << 0); -+ writel(reg, S5P_MIPI_CONTROL); -+ -+ dev_dbg(dsim->dev, "%s : %x\n", __func__, reg); -+ -+ return 0; -+} -+ -+static int s5p_dsim_enable_dsi_master(struct dsim_global *dsim, -+ unsigned int enable) -+{ -+ unsigned int reg; -+ -+ if (dsim == NULL) { -+ printk(KERN_ERR "dsim is NULL.\n"); -+ return -EFAULT; -+ } -+ -+ reg = (readl(S5P_MIPI_CONTROL)) & ~(1 << 2); -+ reg |= (enable << 2); -+ writel(reg, S5P_MIPI_CONTROL); -+ -+ dev_dbg(dsim->dev, "%s : %x\n", __func__, reg); -+ -+ return 0; -+} -+ -+int s5p_dsim_part_reset(struct dsim_global *dsim) -+{ -+ if (dsim == NULL) { -+ printk(KERN_ERR "dsim is NULL.\n"); -+ return -EFAULT; -+ } -+ -+ writel(S5P_MIPI_M_RESETN, S5P_MIPI_PHY_CON0); -+ -+ dev_dbg(dsim->dev, "%s\n", __func__); -+ -+ return 0; -+} -+ -+int s5p_dsim_init_d_phy(struct dsim_global *dsim) -+{ -+ if (dsim == NULL) { -+ printk(KERN_ERR "dsim is NULL.\n"); -+ return -EFAULT; -+ } -+ -+ /* enable D-PHY */ -+ s5p_dsim_enable_d_phy(dsim, 1); -+ -+ /* enable DSI master block */ -+ s5p_dsim_enable_dsi_master(dsim, 1); -+ -+ dev_dbg(dsim->dev, "%s\n", __func__); -+ -+ return 0; -+} -+ -+int s5p_dsim_mipi_power(struct dsim_global *dsim, void *p_mipi_1_1v, -+ void *p_mipi_1_8v, int enable) -+{ -+ struct regulator *r_mipi_1_1v = NULL, *r_mipi_1_8v = NULL; -+ int ret = -1; -+ -+ r_mipi_1_1v = (struct regulator *) p_mipi_1_1v; -+ r_mipi_1_8v = (struct regulator *) p_mipi_1_8v; -+ -+ if (dsim == NULL) { -+ printk(KERN_ERR "dsim is NULL.\n"); -+ return -EFAULT; -+ } -+ -+ if (IS_ERR(r_mipi_1_1v) || IS_ERR(r_mipi_1_8v)) { -+ dev_err(dsim->dev, "r_mipi_1_1v or r_mipi_1_8v is NULL.\n"); -+ return -EINVAL; -+ } -+ -+ if (enable) { -+ if (r_mipi_1_1v) -+ ret = regulator_enable(r_mipi_1_1v); -+ -+ if (ret < 0) { -+ dev_err(dsim->dev, -+ "failed to enable regulator mipi_1_1v.\n"); -+ return ret; -+ } -+ -+ if (r_mipi_1_8v) -+ ret = regulator_enable(r_mipi_1_8v); -+ -+ if (ret < 0) { -+ dev_err(dsim->dev, -+ "failed to enable regulator mipi_1_8v.\n"); -+ return ret; -+ } -+ } else { -+ if (r_mipi_1_1v) -+ ret = regulator_force_disable(r_mipi_1_1v); -+ if (ret < 0) { -+ dev_err(dsim->dev, -+ "failed to disable regulator mipi_1_1v.\n"); -+ return ret; -+ } -+ -+ if (r_mipi_1_8v) -+ ret = regulator_force_disable(r_mipi_1_8v); -+ if (ret < 0) { -+ dev_err(dsim->dev, -+ "failed to disable regulator mipi_1_8v.\n"); -+ return ret; -+ } -+ } -+ -+ return ret; -+} -diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig -index 3d94a14..c916ac1 100644 ---- a/drivers/video/Kconfig -+++ b/drivers/video/Kconfig -@@ -1930,7 +1930,7 @@ config FB_TMIO_ACCELL - - config FB_S3C - tristate "Samsung S3C framebuffer support" -- depends on FB && ARCH_S3C64XX -+ depends on FB && (ARCH_S3C64XX || ARCH_S5PV210) - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT -@@ -1975,6 +1975,13 @@ config FB_S3C2410_DEBUG - Turn on debugging messages. Note that you can set/unset at run time - through sysfs - -+config S5P_MIPI_DSI -+ tristate "Samsung SoC MIPI-DSI support." -+ depends on FB_S3C && ARCH_S5PV210 -+ default n -+ ---help--- -+ This enables support for MIPI-DSI device. -+ - config FB_NUC900 - bool "NUC900 LCD framebuffer support" - depends on FB && ARCH_W90X900 -diff --git a/drivers/video/Makefile b/drivers/video/Makefile -index ddc2af2..d841433 100644 ---- a/drivers/video/Makefile -+++ b/drivers/video/Makefile -@@ -115,6 +115,8 @@ obj-$(CONFIG_FB_SH7760) += sh7760fb.o - obj-$(CONFIG_FB_IMX) += imxfb.o - obj-$(CONFIG_FB_S3C) += s3c-fb.o - obj-$(CONFIG_FB_S3C2410) += s3c2410fb.o -+obj-$(CONFIG_S5P_MIPI_DSI) += s5p-dsim.o s5p_dsim_common.o \ -+ s5p_dsim_lowlevel.o - obj-$(CONFIG_FB_FSL_DIU) += fsl-diu-fb.o - obj-$(CONFIG_FB_COBALT) += cobalt_lcdfb.o - obj-$(CONFIG_FB_PNX4008_DUM) += pnx4008/ -diff --git a/drivers/video/s5p-dsim.c b/drivers/video/s5p-dsim.c -new file mode 100644 -index 0000000..96893bc ---- /dev/null -+++ b/drivers/video/s5p-dsim.c -@@ -0,0 +1,483 @@ -+/* linux/drivers/video/samsung/s5p-dsim.c -+ * -+ * Samsung MIPI-DSIM driver. -+ * -+ * InKi Dae, <a class="moz-txt-link-rfc2396E" href="mailto:inki.dae@samsung.com"><inki.dae@samsung.com></a> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+*/ -+ -+#include <linux/module.h> -+#include <linux/kernel.h> -+#include <linux/errno.h> -+#include <linux/clk.h> -+#include <linux/mutex.h> -+#include <linux/wait.h> -+#include <linux/fs.h> -+#include <linux/mm.h> -+#include <linux/fb.h> -+#include <linux/ctype.h> -+#include <linux/platform_device.h> -+#include <linux/io.h> -+#include <linux/irq.h> -+#include <linux/memory.h> -+#include <linux/delay.h> -+#include <linux/interrupt.h> -+#include <linux/kthread.h> -+#include <linux/regulator/consumer.h> -+#include <linux/notifier.h> -+ -+#include <plat/fb.h> -+#include <plat/regs-dsim.h> -+#include <plat/dsim.h> -+#include <plat/mipi_ddi.h> -+ -+#include <mach/map.h> -+ -+#include "s5p_dsim_common.h" -+ -+struct mipi_lcd_info { -+ struct list_head list; -+ struct mipi_lcd_driver *mipi_drv; -+}; -+ -+static LIST_HEAD(lcd_info_list); -+static DEFINE_MUTEX(mipi_lock); -+ -+struct dsim_global dsim; -+ -+struct s5p_platform_dsim *to_dsim_plat(struct device *dev) -+{ -+ struct platform_device *pdev = to_platform_device(dev); -+ -+ return (struct s5p_platform_dsim *)pdev->dev.platform_data; -+} -+ -+/* -+ * notifier callback function for fb_blank -+ * - this function would be called by device specific fb_blank. -+ */ -+static int s5p_dsim_notifier_callback(struct notifier_block *self, -+ unsigned long event, void *data) -+{ -+ pm_message_t pm; -+ -+ pm.event = 0; -+ -+ switch (event) { -+ case FB_BLANK_UNBLANK: -+ case FB_BLANK_NORMAL: -+ if (dsim.pd->mipi_power) -+ dsim.pd->mipi_power(&dsim, (void *) dsim.r_mipi_1_1v, -+ (void *) dsim.r_mipi_1_8v, 1); -+ -+ clk_enable(dsim.clock); -+ -+ if (dsim.mipi_drv->resume) -+ dsim.mipi_drv->resume(dsim.dev); -+ -+ s5p_dsim_init_dsim(&dsim); -+ s5p_dsim_init_link(&dsim); -+ -+ s5p_dsim_set_hs_enable(&dsim); -+ s5p_dsim_set_data_transfer_mode(&dsim, -+ DSIM_TRANSFER_BYCPU, 1); -+ -+ /* it needs delay for stabilization */ -+ mdelay(dsim.pd->delay_for_stabilization); -+ -+ if (dsim.mipi_drv->init) -+ dsim.mipi_drv->init(dsim.dev); -+ else -+ dev_warn(dsim.dev, "init func is null.\n"); -+ -+ s5p_dsim_set_display_mode(&dsim, dsim.dsim_lcd_info, NULL); -+ -+ s5p_dsim_set_data_transfer_mode(&dsim, DSIM_TRANSFER_BYLCDC, 1); -+ dsim.mipi_ddi_pd->resume_complete = 1; -+ -+ dev_dbg(dsim.dev, "FB_BLANK_NORMAL or UNBLANK.\n"); -+ -+ break; -+ case FB_BLANK_POWERDOWN: -+ dsim.mipi_ddi_pd->resume_complete = 0; -+ -+ if (dsim.mipi_drv->suspend) -+ dsim.mipi_drv->suspend(dsim.dev, pm); -+ -+ clk_disable(dsim.clock); -+ -+ if (dsim.pd->mipi_power) -+ dsim.pd->mipi_power(&dsim, (void *) dsim.r_mipi_1_1v, -+ (void *) dsim.r_mipi_1_8v, 0); -+ -+ dev_dbg(dsim.dev, "FB_BLANK_POWERDOWN.\n"); -+ break; -+ default: -+ dev_warn(dsim.dev, "unknown FB_BLANK command.\n"); -+ break; -+ } -+ -+ return 0; -+} -+ -+static int s5p_dsim_register_notif(struct device *dev) -+{ -+ memset(&dsim.s3cfb_notif, 0, sizeof(struct notifier_block)); -+ dsim.s3cfb_notif.notifier_call = s5p_dsim_notifier_callback; -+ -+ return 0/*s3cfb_register_client(&dsim.s3cfb_notif)*/; -+} -+ -+static irqreturn_t s5p_dsim_interrupt_handler(int irq, void *dev_id) -+{ -+ disable_irq(irq); -+ -+ /* additional work. */ -+ -+ enable_irq(irq); -+ -+ return IRQ_HANDLED; -+} -+ -+int s5p_dsim_register_lcd_driver(struct mipi_lcd_driver *lcd_drv) -+{ -+ struct mipi_lcd_info *lcd_info = NULL; -+ -+ lcd_info = kmalloc(sizeof(struct mipi_lcd_info), GFP_KERNEL); -+ if (lcd_info == NULL) -+ return -ENOMEM; -+ -+ lcd_info->mipi_drv = kmalloc(sizeof(struct mipi_lcd_driver), -+ GFP_KERNEL); -+ if (lcd_info->mipi_drv == NULL) -+ return -ENOMEM; -+ -+ -+ memcpy(lcd_info->mipi_drv, lcd_drv, sizeof(struct mipi_lcd_driver)); -+ -+ mutex_lock(&mipi_lock); -+ list_add_tail(&lcd_info->list, &lcd_info_list); -+ mutex_unlock(&mipi_lock); -+ -+ dev_dbg(dsim.dev, "registered panel driver(%s) to mipi-dsi driver.\n", -+ lcd_drv->name); -+ -+ return 0; -+} -+ -+/* -+ * This function is wrapper for changing transfer mode. -+ * It is used to in panel driver before and after changing gamma value. -+ */ -+static int s5p_dsim_change_transfer_mode(int mode) -+{ -+ if (mode < 0 || mode > 1) { -+ dev_err(dsim.dev, "mode range should be 0 or 1.\n"); -+ return -EFAULT; -+ } -+ -+ if (mode == 0) -+ s5p_dsim_set_data_transfer_mode(&dsim, -+ DSIM_TRANSFER_BYCPU, mode); -+ else -+ s5p_dsim_set_data_transfer_mode(&dsim, -+ DSIM_TRANSFER_BYLCDC, mode); -+ -+ return 0; -+} -+ -+struct mipi_lcd_driver *scan_mipi_driver(const char *name) -+{ -+ struct mipi_lcd_info *lcd_info; -+ struct mipi_lcd_driver *mipi_drv = NULL; -+ -+ mutex_lock(&mipi_lock); -+ -+ dev_dbg(dsim.dev, "find lcd panel driver(%s).\n", -+ name); -+ -+ list_for_each_entry(lcd_info, &lcd_info_list, list) { -+ mipi_drv = lcd_info->mipi_drv; -+ -+ if ((strcmp(mipi_drv->name, name)) == 0) { -+ mutex_unlock(&mipi_lock); -+ dev_dbg(dsim.dev, "found!!!(%s).\n", mipi_drv->name); -+ return mipi_drv; -+ } -+ } -+ -+ dev_warn(dsim.dev, "failed to find lcd panel driver(%s).\n", -+ name); -+ -+ mutex_unlock(&mipi_lock); -+ -+ return NULL; -+} -+ -+static int s5p_dsim_probe(struct platform_device *pdev) -+{ -+ struct resource *res; -+ int ret = -1; -+ -+ dsim.pd = to_dsim_plat(&pdev->dev); -+ dsim.dev = &pdev->dev; -+ -+ /* set dsim config data, dsim lcd config data and lcd panel data. */ -+ dsim.dsim_info = dsim.pd->dsim_info; -+ dsim.dsim_lcd_info = dsim.pd->dsim_lcd_info; -+ dsim.lcd_panel_info = -+ (struct fb_videomode *) dsim.dsim_lcd_info->lcd_panel_info; -+ dsim.mipi_ddi_pd = -+ (struct mipi_ddi_platform_data *) -+ dsim.dsim_lcd_info->mipi_ddi_pd; -+ -+ dsim.mipi_ddi_pd->resume_complete = 0; -+ -+ dsim.r_mipi_1_1v = regulator_get(&pdev->dev, "VMIPI_1.1V"); -+ if (IS_ERR(dsim.r_mipi_1_1v)) { -+ dev_err(&pdev->dev, "failed to get regulator VMIPI_1.1V.\n"); -+ goto regulator_get_err; -+ } -+ -+ dsim.r_mipi_1_8v = regulator_get(&pdev->dev, "VMIPI_1.8V"); -+ if (IS_ERR(dsim.r_mipi_1_8v)) { -+ dev_err(&pdev->dev, "failed to get regulator VMIPI_1.8V.\n"); -+ goto regulator_get_err; -+ } -+ -+ /* clock */ -+ dsim.clock = clk_get(&pdev->dev, dsim.pd->clk_name); -+ if (IS_ERR(dsim.clock)) { -+ dev_err(&pdev->dev, "failed to get dsim clock source\n"); -+ return -EINVAL; -+ } -+ -+ clk_enable(dsim.clock); -+ -+ /* io memory */ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) { -+ dev_err(&pdev->dev, "failed to get io memory region\n"); -+ ret = -EINVAL; -+ goto err_clk_disable; -+ } -+ -+ /* request mem region */ -+ res = request_mem_region(res->start, -+ res->end - res->start + 1, pdev->name); -+ if (!res) { -+ dev_err(&pdev->dev, "failed to request io memory region\n"); -+ ret = -EINVAL; -+ goto err_clk_disable; -+ } -+ -+ /* ioremap for register block */ -+ dsim.reg_base = (unsigned int) ioremap(res->start, -+ res->end - res->start + 1); -+ if (!dsim.reg_base) { -+ dev_err(&pdev->dev, "failed to remap io region\n"); -+ ret = -EINVAL; -+ goto err_clk_disable; -+ } -+ -+ /* it is used for MIPI-DSI based lcd panel driver. */ -+ dsim.mipi_ddi_pd->dsim_data = (void *)&dsim; -+ -+ /* -+ * it uses frame done interrupt handler -+ * only in case of MIPI Video mode. -+ */ -+ if (dsim.dsim_lcd_info->e_interface == DSIM_VIDEO) { -+ dsim.irq = platform_get_irq(pdev, 0); -+ if (request_irq(dsim.irq, s5p_dsim_interrupt_handler, -+ IRQF_TRIGGER_RISING, "mipi-dsi", &dsim)) { -+ dev_err(&pdev->dev, "request_irq failed.\n"); -+ goto err_trigger_irq; -+ } -+ } -+ -+ if (dsim.pd->mipi_power) -+ dsim.pd->mipi_power(&dsim, (void *) dsim.r_mipi_1_1v, -+ (void *) dsim.r_mipi_1_8v, 1); -+ else { -+ dev_err(&pdev->dev, "mipi_power is NULL.\n"); -+ goto mipi_power_err; -+ } -+ -+ /* find lcd panel driver registered to mipi-dsi driver. */ -+ dsim.mipi_drv = scan_mipi_driver(dsim.pd->lcd_panel_name); -+ if (dsim.mipi_drv == NULL) { -+ dev_err(&pdev->dev, "mipi_drv is NULL.\n"); -+ goto mipi_drv_err; -+ } -+ -+ /* register callback functions that lcd panel driver needs. */ -+ dsim.mipi_ddi_pd->cmd_write = s5p_dsim_wr_data; -+ dsim.mipi_ddi_pd->cmd_read = NULL; -+ dsim.mipi_ddi_pd->get_dsim_frame_done = -+ s5p_dsim_get_frame_done_status; -+ dsim.mipi_ddi_pd->clear_dsim_frame_done = s5p_dsim_clear_frame_done; -+ dsim.mipi_ddi_pd->change_dsim_transfer_mode = -+ s5p_dsim_change_transfer_mode; -+ dsim.mipi_ddi_pd->get_fb_frame_done = dsim.pd->get_fb_frame_done; -+ dsim.mipi_ddi_pd->trigger = dsim.pd->trigger; -+ -+ /* set lcd panel driver link */ -+ ret = dsim.mipi_drv->set_link(dsim.mipi_ddi_pd); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "failed to set link.\n"); -+ goto mipi_drv_err; -+ } -+ -+ dsim.mipi_drv->probe(&pdev->dev); -+ -+ s5p_dsim_init_dsim(&dsim); -+ s5p_dsim_init_link(&dsim); -+ -+ s5p_dsim_set_hs_enable(&dsim); -+ s5p_dsim_set_data_transfer_mode(&dsim, DSIM_TRANSFER_BYCPU, 1); -+ -+ /* it needs delay for stabilization */ -+ mdelay(dsim.pd->delay_for_stabilization); -+ -+ /* initialize lcd panel */ -+ if (dsim.mipi_drv->init) -+ dsim.mipi_drv->init(&pdev->dev); -+ else -+ dev_warn(&pdev->dev, "init func is null.\n"); -+ -+ if (dsim.mipi_drv->display_on) -+ dsim.mipi_drv->display_on(&pdev->dev); -+ else -+ dev_warn(&pdev->dev, "display_on func is null.\n"); -+ -+ s5p_dsim_set_display_mode(&dsim, dsim.dsim_lcd_info, NULL); -+ -+ s5p_dsim_set_data_transfer_mode(&dsim, DSIM_TRANSFER_BYLCDC, 1); -+ -+ s5p_dsim_register_notif(&pdev->dev); -+ -+ /* in case of command mode, trigger. */ -+ if (dsim.dsim_lcd_info->e_interface == DSIM_COMMAND) { -+ if (dsim.pd->trigger) -+ dsim.pd->trigger(registered_fb[0]); -+ else -+ dev_warn(&pdev->dev, "trigger is null.\n"); -+ } -+ -+ dev_info(&pdev->dev, "mipi-dsi driver(%s mode) has been probed.\n", -+ (dsim.dsim_lcd_info->e_interface == DSIM_COMMAND) ? -+ "CPU" : "RGB"); -+ -+ return 0; -+ -+err_trigger_irq: -+mipi_drv_err: -+ dsim.pd->mipi_power(&dsim, (void *) dsim.r_mipi_1_1v, -+ (void *) dsim.r_mipi_1_8v, 0); -+ -+mipi_power_err: -+ iounmap((void __iomem *) dsim.reg_base); -+ -+err_clk_disable: -+ clk_disable(dsim.clock); -+ -+regulator_get_err: -+ -+ return ret; -+ -+} -+ -+static int s5p_dsim_remove(struct platform_device *pdev) -+{ -+ return 0; -+} -+ -+#ifdef CONFIG_PM -+int s5p_dsim_suspend(struct platform_device *pdev, pm_message_t state) -+{ -+ dsim.mipi_ddi_pd->resume_complete = 0; -+ -+ if (dsim.mipi_drv->suspend) -+ dsim.mipi_drv->suspend(&pdev->dev, state); -+ -+ clk_disable(dsim.clock); -+ -+ if (dsim.pd->mipi_power) -+ dsim.pd->mipi_power(&dsim, (void *) dsim.r_mipi_1_1v, -+ (void *) dsim.r_mipi_1_8v, 0); -+ -+ return 0; -+} -+ -+int s5p_dsim_resume(struct platform_device *pdev) -+{ -+ if (dsim.pd->mipi_power) -+ dsim.pd->mipi_power(&dsim, (void *) dsim.r_mipi_1_1v, -+ (void *) dsim.r_mipi_1_8v, 1); -+ -+ clk_enable(dsim.clock); -+ -+ if (dsim.mipi_drv->resume) -+ dsim.mipi_drv->resume(&pdev->dev); -+ -+ s5p_dsim_init_dsim(&dsim); -+ s5p_dsim_init_link(&dsim); -+ -+ s5p_dsim_set_hs_enable(&dsim); -+ s5p_dsim_set_data_transfer_mode(&dsim, DSIM_TRANSFER_BYCPU, 1); -+ -+ /* it needs delay for stabilization */ -+ mdelay(dsim.pd->delay_for_stabilization); -+ -+ /* initialize lcd panel */ -+ if (dsim.mipi_drv->init) -+ dsim.mipi_drv->init(&pdev->dev); -+ else -+ dev_warn(&pdev->dev, "init func is null.\n"); -+ -+ s5p_dsim_set_display_mode(&dsim, dsim.dsim_lcd_info, NULL); -+ -+ s5p_dsim_set_data_transfer_mode(&dsim, DSIM_TRANSFER_BYLCDC, 1); -+ -+ dsim.mipi_ddi_pd->resume_complete = 1; -+ -+ return 0; -+} -+#else -+#define s5p_dsim_suspend NULL -+#define s5p_dsim_resume NULL -+#endif -+ -+static struct platform_driver s5p_dsim_driver = { -+ .probe = s5p_dsim_probe, -+ .remove = s5p_dsim_remove, -+ .suspend = s5p_dsim_suspend, -+ .resume = s5p_dsim_resume, -+ .driver = { -+ .name = "s5p-dsim", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int s5p_dsim_register(void) -+{ -+ platform_driver_register(&s5p_dsim_driver); -+ -+ return 0; -+} -+ -+static void s5p_dsim_unregister(void) -+{ -+ platform_driver_unregister(&s5p_dsim_driver); -+} -+ -+module_init(s5p_dsim_register); -+module_exit(s5p_dsim_unregister); -+ -+MODULE_AUTHOR("InKi Dae <a class="moz-txt-link-rfc2396E" href="mailto:inki.dae@samsung.com"><inki.dae@samsung.com></a>"); -+MODULE_DESCRIPTION("Samusung MIPI-DSIM driver"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/video/s5p_dsim_common.c b/drivers/video/s5p_dsim_common.c -new file mode 100644 -index 0000000..77724dc ---- /dev/null -+++ b/drivers/video/s5p_dsim_common.c -@@ -0,0 +1,753 @@ -+/* linux/drivers/video/samsung/s5p_dsim_common.c -+ * -+ * Samsung MIPI-DSIM common driver. -+ * -+ * InKi Dae, <a class="moz-txt-link-rfc2396E" href="mailto:inki.dae@samsung.com"><inki.dae@samsung.com></a> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+*/ -+ -+#include <linux/module.h> -+#include <linux/kernel.h> -+#include <linux/errno.h> -+#include <linux/mutex.h> -+#include <linux/wait.h> -+#include <linux/fs.h> -+#include <linux/mm.h> -+#include <linux/fb.h> -+#include <linux/ctype.h> -+#include <linux/platform_device.h> -+#include <linux/io.h> -+#include <linux/memory.h> -+#include <linux/delay.h> -+#include <linux/kthread.h> -+ -+#include <plat/fb.h> -+#include <plat/regs-dsim.h> -+ -+#include <mach/map.h> -+#include <plat/dsim.h> -+#include <plat/mipi_ddi.h> -+ -+#include "s5p_dsim_lowlevel.h" -+ -+static void s5p_dsim_long_data_wr(struct dsim_global *dsim, unsigned int data0, -+ unsigned int data1) -+{ -+ unsigned int data_cnt = 0, payload = 0; -+ -+ /* in case that data count is more then 4 */ -+ for (data_cnt = 0; data_cnt < data1; data_cnt += 4) { -+ /* -+ * after sending 4bytes per one time, -+ * send remainder data less then 4. -+ */ -+ if ((data1 - data_cnt) < 4) { -+ if ((data1 - data_cnt) == 3) { -+ payload = *(u8 *)(data0 + data_cnt) | -+ (*(u8 *)(data0 + (data_cnt + 1))) << 8 | -+ (*(u8 *)(data0 + (data_cnt + 2))) << 16; -+ dev_dbg(dsim->dev, "count = 3 payload = %x, %x %x %x\n", -+ payload, *(u8 *)(data0 + data_cnt), -+ *(u8 *)(data0 + (data_cnt + 1)), -+ *(u8 *)(data0 + (data_cnt + 2))); -+ } else if ((data1 - data_cnt) == 2) { -+ payload = *(u8 *)(data0 + data_cnt) | -+ (*(u8 *)(data0 + (data_cnt + 1))) << 8; -+ dev_dbg(dsim->dev, -+ "count = 2 payload = %x, %x %x\n", payload, -+ *(u8 *)(data0 + data_cnt), -+ *(u8 *)(data0 + (data_cnt + 1))); -+ } else if ((data1 - data_cnt) == 1) { -+ payload = *(u8 *)(data0 + data_cnt); -+ } -+ -+ s5p_dsim_wr_tx_data(dsim, payload); -+ /* send 4bytes per one time. */ -+ } else { -+ payload = *(u8 *)(data0 + data_cnt) | -+ (*(u8 *)(data0 + (data_cnt + 1))) << 8 | -+ (*(u8 *)(data0 + (data_cnt + 2))) << 16 | -+ (*(u8 *)(data0 + (data_cnt + 3))) << 24; -+ -+ dev_dbg(dsim->dev, -+ "count = 4 payload = %x, %x %x %x %x\n", -+ payload, *(u8 *)(data0 + data_cnt), -+ *(u8 *)(data0 + (data_cnt + 1)), -+ *(u8 *)(data0 + (data_cnt + 2)), -+ *(u8 *)(data0 + (data_cnt + 3))); -+ -+ s5p_dsim_wr_tx_data(dsim, payload); -+ } -+ } -+} -+ -+int s5p_dsim_wr_data(void *dsim_data, unsigned int data_id, -+ unsigned int data0, unsigned int data1) -+{ -+ struct dsim_global *dsim = NULL; -+ unsigned int timeout = 5000 * 2; -+ unsigned long delay_val, udelay; -+ unsigned char check_rx_ack = 0; -+ -+ dsim = (struct dsim_global *)dsim_data; -+ -+ if (dsim == NULL) { -+ dev_err(dsim->dev, "dsim_data is NULL.\n"); -+ return -EFAULT; -+ } -+ -+ -+ if (dsim->state == DSIM_STATE_ULPS) { -+ dev_err(dsim->dev, "state is ULPS.\n"); -+ -+ return -EINVAL; -+ } -+ -+ delay_val = 1000000 / dsim->dsim_info->esc_clk; -+ udelay = 10 * delay_val; -+ -+ mdelay(udelay); -+ -+ /* only if transfer mode is LPDT, wait SFR becomes empty. */ -+ if (dsim->state == DSIM_STATE_STOP) { -+ while (!(s5p_dsim_get_fifo_state(dsim) & -+ SFR_HEADER_EMPTY)) { -+ if ((timeout--) > 0) -+ mdelay(1); -+ else { -+ dev_err(dsim->dev, -+ "SRF header fifo is not empty.\n"); -+ return -EINVAL; -+ } -+ } -+ } -+ -+ switch (data_id) { -+ /* short packet types of packet types for command. */ -+ case GEN_SHORT_WR_NO_PARA: -+ case GEN_SHORT_WR_1_PARA: -+ case GEN_SHORT_WR_2_PARA: -+ case DCS_WR_NO_PARA: -+ case DCS_WR_1_PARA: -+ case SET_MAX_RTN_PKT_SIZE: -+ s5p_dsim_wr_tx_header(dsim, (unsigned char) data_id, -+ (unsigned char) data0, (unsigned char) data1); -+ if (check_rx_ack) -+ /* process response func should be implemented */ -+ return 0; -+ else -+ return -EINVAL; -+ -+ /* general command */ -+ case CMD_OFF: -+ case CMD_ON: -+ case SHUT_DOWN: -+ case TURN_ON: -+ s5p_dsim_wr_tx_header(dsim, (unsigned char) data_id, -+ (unsigned char) data0, (unsigned char) data1); -+ if (check_rx_ack) -+ /* process response func should be implemented. */ -+ return 0; -+ else -+ return -EINVAL; -+ -+ /* packet types for video data */ -+ case VSYNC_START: -+ case VSYNC_END: -+ case HSYNC_START: -+ case HSYNC_END: -+ case EOT_PKT: -+ return 0; -+ -+ /* short and response packet types for command */ -+ case GEN_RD_1_PARA: -+ case GEN_RD_2_PARA: -+ case GEN_RD_NO_PARA: -+ case DCS_RD_NO_PARA: -+ s5p_dsim_clear_interrupt(dsim, 0xffffffff); -+ s5p_dsim_wr_tx_header(dsim, (unsigned char) data_id, -+ (unsigned char) data0, (unsigned char) data1); -+ /* process response func should be implemented. */ -+ return 0; -+ -+ /* long packet type and null packet */ -+ case NULL_PKT: -+ case BLANKING_PKT: -+ return 0; -+ case GEN_LONG_WR: -+ case DCS_LONG_WR: -+ { -+ unsigned int size, data_cnt = 0, payload = 0; -+ -+ size = data1 * 4; -+ -+ /* if data count is less then 4, then send 3bytes data. */ -+ if (data1 < 4) { -+ payload = *(u8 *)(data0) | -+ *(u8 *)(data0 + 1) << 8 | -+ *(u8 *)(data0 + 2) << 16; -+ -+ s5p_dsim_wr_tx_data(dsim, payload); -+ -+ dev_dbg(dsim->dev, "count = %d payload = %x,%x %x %x\n", -+ data1, payload, -+ *(u8 *)(data0 + data_cnt), -+ *(u8 *)(data0 + (data_cnt + 1)), -+ *(u8 *)(data0 + (data_cnt + 2))); -+ /* in case that data count is more then 4 */ -+ } else -+ s5p_dsim_long_data_wr(dsim, data0, data1); -+ -+ /* put data into header fifo */ -+ s5p_dsim_wr_tx_header(dsim, (unsigned char) data_id, -+ (unsigned char) (((unsigned short) data1) & 0xff), -+ (unsigned char) ((((unsigned short) data1) & 0xff00) >> -+ 8)); -+ -+ } -+ if (check_rx_ack) -+ /* process response func should be implemented. */ -+ return 0; -+ else -+ return -EINVAL; -+ -+ /* packet typo for video data */ -+ case RGB565_PACKED: -+ case RGB666_PACKED: -+ case RGB666_LOOSLY: -+ case RGB888_PACKED: -+ if (check_rx_ack) -+ /* process response func should be implemented. */ -+ return 0; -+ else -+ return -EINVAL; -+ default: -+ dev_warn(dsim->dev, -+ "data id %x is not supported current DSI spec.\n", -+ data_id); -+ -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+int s5p_dsim_init_header_fifo(struct dsim_global *dsim) -+{ -+ unsigned int cnt; -+ -+ if (dsim == NULL) { -+ printk(KERN_ERR "dsim_global pointer is NULL.\n"); -+ return -EFAULT; -+ } -+ -+ for (cnt = 0; cnt < DSIM_HEADER_FIFO_SZ; cnt++) -+ dsim->header_fifo_index[cnt] = -1; -+ return 0; -+} -+ -+int s5p_dsim_pll_on(struct dsim_global *dsim, unsigned char enable) -+{ -+ if (dsim == NULL) { -+ printk(KERN_ERR "dsim_global pointer is NULL.\n"); -+ return -EFAULT; -+ } -+ -+ if (enable) { -+ int sw_timeout = 1000; -+ s5p_dsim_clear_interrupt(dsim, DSIM_PLL_STABLE); -+ s5p_dsim_enable_pll(dsim, 1); -+ while (1) { -+ sw_timeout--; -+ if (s5p_dsim_is_pll_stable(dsim)) -+ return 0; -+ if (sw_timeout == 0) -+ return -EINVAL; -+ } -+ } else -+ s5p_dsim_enable_pll(dsim, 0); -+ -+ return 0; -+} -+ -+unsigned long s5p_dsim_change_pll(struct dsim_global *dsim, -+ unsigned char pre_divider, unsigned short main_divider, -+ unsigned char scaler) -+{ -+ unsigned long dfin_pll, dfvco, dpll_out; -+ unsigned char freq_band; -+ -+ if (dsim == NULL) { -+ printk(KERN_ERR "dsim_global pointer is NULL.\n"); -+ return 0; -+ } -+ -+ dfin_pll = (MIPI_FIN / pre_divider); -+ -+ if (dfin_pll < 6 * 1000 * 1000 || dfin_pll > 12 * 1000 * 1000) { -+ dev_warn(dsim->dev, "warning!!\n"); -+ dev_warn(dsim->dev, "fin_pll range is 6MHz ~ 12MHz\n"); -+ dev_warn(dsim->dev, "fin_pll of mipi dphy pll is %luMHz\n", -+ (dfin_pll / 1000000)); -+ -+ s5p_dsim_enable_afc(dsim, 0, 0); -+ } else { -+ if (dfin_pll < 7 * 1000000) -+ s5p_dsim_enable_afc(dsim, 1, 0x1); -+ else if (dfin_pll < 8 * 1000000) -+ s5p_dsim_enable_afc(dsim, 1, 0x0); -+ else if (dfin_pll < 9 * 1000000) -+ s5p_dsim_enable_afc(dsim, 1, 0x3); -+ else if (dfin_pll < 10 * 1000000) -+ s5p_dsim_enable_afc(dsim, 1, 0x2); -+ else if (dfin_pll < 11 * 1000000) -+ s5p_dsim_enable_afc(dsim, 1, 0x5); -+ else -+ s5p_dsim_enable_afc(dsim, 1, 0x4); -+ } -+ -+ dfvco = dfin_pll * main_divider; -+ dev_dbg(dsim->dev, "dfvco = %lu, dfin_pll = %lu, main_divider = %d\n", -+ dfvco, dfin_pll, main_divider); -+ if (dfvco < 500000000 || dfvco > 1000000000) { -+ dev_warn(dsim->dev, "Caution!!\n"); -+ dev_warn(dsim->dev, "fvco range is 500MHz ~ 1000MHz\n"); -+ dev_warn(dsim->dev, "fvco of mipi dphy pll is %luMHz\n", -+ (dfvco / 1000000)); -+ } -+ -+ dpll_out = dfvco / (1 << scaler); -+ dev_dbg(dsim->dev, "dpll_out = %lu, dfvco = %lu, scaler = %d\n", -+ dpll_out, dfvco, scaler); -+ if (dpll_out < 100 * 1000000) -+ freq_band = 0x0; -+ else if (dpll_out < 120 * 1000000) -+ freq_band = 0x1; -+ else if (dpll_out < 170 * 1000000) -+ freq_band = 0x2; -+ else if (dpll_out < 220 * 1000000) -+ freq_band = 0x3; -+ else if (dpll_out < 270 * 1000000) -+ freq_band = 0x4; -+ else if (dpll_out < 320 * 1000000) -+ freq_band = 0x5; -+ else if (dpll_out < 390 * 1000000) -+ freq_band = 0x6; -+ else if (dpll_out < 450 * 1000000) -+ freq_band = 0x7; -+ else if (dpll_out < 510 * 1000000) -+ freq_band = 0x8; -+ else if (dpll_out < 560 * 1000000) -+ freq_band = 0x9; -+ else if (dpll_out < 640 * 1000000) -+ freq_band = 0xa; -+ else if (dpll_out < 690 * 1000000) -+ freq_band = 0xb; -+ else if (dpll_out < 770 * 1000000) -+ freq_band = 0xc; -+ else if (dpll_out < 870 * 1000000) -+ freq_band = 0xd; -+ else if (dpll_out < 950 * 1000000) -+ freq_band = 0xe; -+ else -+ freq_band = 0xf; -+ -+ dev_dbg(dsim->dev, "freq_band = %d\n", freq_band); -+ -+ s5p_dsim_pll_freq(dsim, pre_divider, main_divider, scaler); -+ -+ { -+ unsigned char temp0, temp1; -+ -+ temp0 = 0; -+ s5p_dsim_hs_zero_ctrl(dsim, temp0); -+ temp1 = 0; -+ s5p_dsim_prep_ctrl(dsim, temp1); -+ } -+ -+ /* Freq Band */ -+ s5p_dsim_pll_freq_band(dsim, freq_band); -+ -+ /* Stable time */ -+ s5p_dsim_pll_stable_time(dsim, -+ dsim->dsim_info->pll_stable_time); -+ -+ /* Enable PLL */ -+ dev_dbg(dsim->dev, "FOUT of mipi dphy pll is %luMHz\n", -+ (dpll_out / 1000000)); -+ -+ return dpll_out; -+} -+ -+int s5p_dsim_set_clock(struct dsim_global *dsim, -+ unsigned char byte_clk_sel, unsigned char enable) -+{ -+ unsigned int esc_div; -+ unsigned long esc_clk_error_rate; -+ -+ if (dsim == NULL) { -+ printk(KERN_ERR "dsim_global pointer is NULL.\n"); -+ return -EINVAL; -+ } -+ -+ if (enable) { -+ dsim->e_clk_src = byte_clk_sel; -+ -+ /* Escape mode clock and byte clock source */ -+ s5p_dsim_set_byte_clock_src(dsim, byte_clk_sel); -+ -+ /* DPHY, DSIM Link : D-PHY clock out */ -+ if (byte_clk_sel == DSIM_PLL_OUT_DIV8) { -+ dsim->hs_clk = s5p_dsim_change_pll(dsim, -+ dsim->dsim_info->p, dsim->dsim_info->m, -+ dsim->dsim_info->s); -+ if (dsim->hs_clk == 0) { -+ dev_err(dsim->dev, -+ "failed to get hs clock.\n"); -+ return -EINVAL; -+ } -+ -+ dsim->byte_clk = dsim->hs_clk / 8; -+ s5p_dsim_enable_pll_bypass(dsim, 0); -+ s5p_dsim_pll_on(dsim, 1); -+ /* DPHY : D-PHY clock out, DSIM link : external clock out */ -+ } else if (byte_clk_sel == DSIM_EXT_CLK_DIV8) -+ dev_warn(dsim->dev, -+ "this project is not support \ -+ external clock source for MIPI DSIM\n"); -+ else if (byte_clk_sel == DSIM_EXT_CLK_BYPASS) -+ dev_warn(dsim->dev, -+ "this project is not support \ -+ external clock source for MIPI DSIM\n"); -+ -+ /* escape clock divider */ -+ esc_div = dsim->byte_clk / (dsim->dsim_info->esc_clk); -+ dev_dbg(dsim->dev, -+ "esc_div = %d, byte_clk = %lu, esc_clk = %lu\n", -+ esc_div, dsim->byte_clk, dsim->dsim_info->esc_clk); -+ if ((dsim->byte_clk / esc_div) >= 20000000 || -+ (dsim->byte_clk / esc_div) > dsim->dsim_info->esc_clk) -+ esc_div += 1; -+ -+ dsim->escape_clk = dsim->byte_clk / esc_div; -+ dev_dbg(dsim->dev, -+ "escape_clk = %lu, byte_clk = %lu, esc_div = %d\n", -+ dsim->escape_clk, dsim->byte_clk, esc_div); -+ -+ /* -+ * enable escclk on lane -+ * -+ * in case of evt0, DSIM_TRUE is enable and -+ * DSIM_FALSE is enable for evt1. -+ */ -+ if (dsim->pd->platform_rev == 1) -+ s5p_dsim_enable_byte_clock(dsim, DSIM_FALSE); -+ else -+ s5p_dsim_enable_byte_clock(dsim, DSIM_TRUE); -+ -+ /* enable byte clk and escape clock */ -+ s5p_dsim_set_esc_clk_prs(dsim, 1, esc_div); -+ /* escape clock on lane */ -+ s5p_dsim_enable_esc_clk_on_lane(dsim, -+ (DSIM_LANE_CLOCK | dsim->data_lane), 1); -+ -+ dev_dbg(dsim->dev, "byte clock is %luMHz\n", -+ (dsim->byte_clk / 1000000)); -+ dev_dbg(dsim->dev, "escape clock that user's need is %lu\n", -+ (dsim->dsim_info->esc_clk / 1000000)); -+ dev_dbg(dsim->dev, "escape clock divider is %x\n", esc_div); -+ dev_dbg(dsim->dev, "escape clock is %luMHz\n", -+ ((dsim->byte_clk / esc_div) / 1000000)); -+ -+ if ((dsim->byte_clk / esc_div) > dsim->escape_clk) { -+ esc_clk_error_rate = dsim->escape_clk / -+ (dsim->byte_clk / esc_div); -+ dev_warn(dsim->dev, "error rate is %lu over.\n", -+ (esc_clk_error_rate / 100)); -+ } else if ((dsim->byte_clk / esc_div) < (dsim->escape_clk)) { -+ esc_clk_error_rate = (dsim->byte_clk / esc_div) / -+ dsim->escape_clk; -+ dev_warn(dsim->dev, "error rate is %lu under.\n", -+ (esc_clk_error_rate / 100)); -+ } -+ } else { -+ s5p_dsim_enable_esc_clk_on_lane(dsim, -+ (DSIM_LANE_CLOCK | dsim->data_lane), 0); -+ s5p_dsim_set_esc_clk_prs(dsim, 0, 0); -+ -+ /* -+ * in case of evt0, DSIM_FALSE is disable and -+ * DSIM_TRUE is disable for evt1. -+ */ -+ if (dsim->pd->platform_rev == 1) -+ s5p_dsim_enable_byte_clock(dsim, DSIM_TRUE); -+ else -+ s5p_dsim_enable_byte_clock(dsim, DSIM_FALSE); -+ -+ if (byte_clk_sel == DSIM_PLL_OUT_DIV8) -+ s5p_dsim_pll_on(dsim, 0); -+ } -+ -+ return 0; -+} -+ -+int s5p_dsim_init_dsim(struct dsim_global *dsim) -+{ -+ if (dsim == NULL) { -+ printk(KERN_ERR "dsim_global pointer is NULL.\n"); -+ return -EFAULT; -+ } -+ -+ if (dsim->pd->init_d_phy) -+ dsim->pd->init_d_phy(dsim); -+ -+ dsim->state = DSIM_STATE_RESET; -+ -+ switch (dsim->dsim_info->e_no_data_lane) { -+ case DSIM_DATA_LANE_1: -+ dsim->data_lane = DSIM_LANE_DATA0; -+ break; -+ case DSIM_DATA_LANE_2: -+ dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1; -+ break; -+ case DSIM_DATA_LANE_3: -+ dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 | -+ DSIM_LANE_DATA2; -+ break; -+ case DSIM_DATA_LANE_4: -+ dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 | -+ DSIM_LANE_DATA2 | DSIM_LANE_DATA3; -+ break; -+ default: -+ dev_info(dsim->dev, "data lane is invalid.\n"); -+ return -EINVAL; -+ }; -+ -+ s5p_dsim_init_header_fifo(dsim); -+ s5p_dsim_sw_reset(dsim); -+ s5p_dsim_dp_dn_swap(dsim, dsim->dsim_info->e_lane_swap); -+ -+ return 0; -+} -+ -+int s5p_dsim_enable_frame_done_int(struct dsim_global *dsim, int enable) -+{ -+ /* enable only frame done interrupt */ -+ s5p_dsim_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable); -+ -+ return 0; -+} -+ -+int s5p_dsim_set_display_mode(struct dsim_global *dsim, -+ struct dsim_lcd_config *main_lcd, struct dsim_lcd_config *sub_lcd) -+{ -+ struct fb_videomode *mlcd_video = NULL; -+ struct fb_cmdmode *mlcd_command = NULL; -+ struct s3c_fb_pd_win *pd; -+ unsigned int width = 0, height = 0; -+ -+ if (dsim == NULL) { -+ printk(KERN_ERR "dsim_global pointer is NULL.\n"); -+ return -EFAULT; -+ } -+ -+ pd = (struct s3c_fb_pd_win *)main_lcd->lcd_panel_info; -+ -+ /* in case of VIDEO MODE (RGB INTERFACE) */ -+ if (dsim->dsim_lcd_info->e_interface == (u32) DSIM_VIDEO) { -+ mlcd_video = (struct fb_videomode *)&pd->win_mode; -+ width = mlcd_video->xres; -+ height = mlcd_video->yres; -+ -+ if (dsim->dsim_info->auto_vertical_cnt == DSIM_FALSE) { -+ s5p_dsim_set_main_disp_vporch(dsim, -+ mlcd_video->upper_margin, -+ mlcd_video->lower_margin, 0); -+ s5p_dsim_set_main_disp_hporch(dsim, -+ mlcd_video->left_margin, -+ mlcd_video->right_margin); -+ s5p_dsim_set_main_disp_sync_area(dsim, -+ mlcd_video->vsync_len, -+ mlcd_video->hsync_len); -+ } -+ } else { /* in case of COMMAND MODE (CPU or I80 INTERFACE) */ -+ mlcd_command = (struct fb_cmdmode *)&pd->cmd_mode; -+ width = mlcd_command->xres; -+ height = mlcd_command->yres; -+ } -+ -+ s5p_dsim_set_main_disp_resol(dsim, height, width); -+ -+ if (sub_lcd != NULL) -+ dev_warn(dsim->dev, "sub lcd isn't supported yet.\n"); -+ -+ s5p_dsim_display_config(dsim, dsim->dsim_lcd_info, NULL); -+ -+ return 0; -+} -+ -+int s5p_dsim_init_link(struct dsim_global *dsim) -+{ -+ unsigned int time_out = 100; -+ -+ if (dsim == NULL) { -+ printk(KERN_ERR "dsim_global pointer is NULL.\n"); -+ return -EFAULT; -+ } -+ -+ switch (dsim->state) { -+ case DSIM_STATE_RESET: -+ s5p_dsim_sw_reset(dsim); -+ case DSIM_STATE_INIT: -+ s5p_dsim_init_fifo_pointer(dsim, 0x1f); -+ -+ /* dsi configuration */ -+ s5p_dsim_init_config(dsim, dsim->dsim_lcd_info, -+ NULL, dsim->dsim_info); -+ s5p_dsim_enable_lane(dsim, DSIM_LANE_CLOCK, 1); -+ s5p_dsim_enable_lane(dsim, dsim->data_lane, 1); -+ -+ /* set clock configuration */ -+ s5p_dsim_set_clock(dsim, dsim->dsim_info->e_byte_clk, -+ 1); -+ -+ /* check clock and data lane state is stop state */ -+ while (!(s5p_dsim_is_lane_state(dsim, DSIM_LANE_CLOCK) -+ == DSIM_LANE_STATE_STOP) && -+ !(s5p_dsim_is_lane_state(dsim, -+ dsim->data_lane) == DSIM_LANE_STATE_STOP)) { -+ time_out--; -+ if (time_out == 0) { -+ dev_info(dsim->dev, -+ "DSI Master is not stop state.\n"); -+ dev_info(dsim->dev, -+ "Check initialization process\n"); -+ -+ return -EINVAL; -+ } -+ } -+ -+ if (time_out != 0) { -+ dev_info(dsim->dev, -+ "initialization of DSI Master is successful\n"); -+ dev_info(dsim->dev, "DSI Master state is stop state\n"); -+ } -+ -+ dsim->state = DSIM_STATE_STOP; -+ -+ /* BTA sequence counters */ -+ s5p_dsim_set_stop_state_counter(dsim, -+ dsim->dsim_info->stop_holding_cnt); -+ s5p_dsim_set_bta_timeout(dsim, -+ dsim->dsim_info->bta_timeout); -+ s5p_dsim_set_lpdr_timeout(dsim, -+ dsim->dsim_info->rx_timeout); -+ -+ /* default LPDT by both cpu and lcd controller */ -+ s5p_dsim_set_data_mode(dsim, DSIM_TRANSFER_BOTH, -+ DSIM_STATE_STOP); -+ -+ return 0; -+ default: -+ dev_info(dsim->dev, "DSI Master is already init.\n"); -+ return 0; -+ } -+ -+ return 0; -+} -+ -+int s5p_dsim_set_hs_enable(struct dsim_global *dsim) -+{ -+ if (dsim == NULL) { -+ printk(KERN_ERR "dsim_global pointer is NULL.\n"); -+ return -EFAULT; -+ } -+ -+ if (dsim->state == DSIM_STATE_STOP) { -+ if (dsim->e_clk_src != DSIM_EXT_CLK_BYPASS) { -+ dsim->state = DSIM_STATE_HSCLKEN; -+ s5p_dsim_set_data_mode(dsim, -+ DSIM_TRANSFER_BOTH, DSIM_STATE_HSCLKEN); -+ s5p_dsim_enable_hs_clock(dsim, 1); -+ -+ return 0; -+ } else -+ dev_warn(dsim->dev, -+ "clock source is external bypass.\n"); -+ } else -+ dev_warn(dsim->dev, "DSIM is not stop state.\n"); -+ -+ return 0; -+} -+ -+int s5p_dsim_set_data_transfer_mode(struct dsim_global *dsim, -+ unsigned char data_path, unsigned char hs_enable) -+{ -+ int ret = -1; -+ -+ if (dsim == NULL) { -+ printk(KERN_ERR "dsim_global pointer is NULL.\n"); -+ return -EFAULT; -+ } -+ -+ if (hs_enable) { -+ if (dsim->state == DSIM_STATE_HSCLKEN) { -+ s5p_dsim_set_data_mode(dsim, data_path, -+ DSIM_STATE_HSCLKEN); -+ ret = 0; -+ } else { -+ dev_err(dsim->dev, "HS Clock lane is not enabled.\n"); -+ ret = -EINVAL; -+ } -+ } else { -+ if (dsim->state == DSIM_STATE_INIT || dsim->state == -+ DSIM_STATE_ULPS) { -+ dev_err(dsim->dev, -+ "DSI Master is not STOP or HSDT state.\n"); -+ ret = -EINVAL; -+ } else { -+ s5p_dsim_set_data_mode(dsim, data_path, -+ DSIM_STATE_STOP); -+ ret = 0; -+ } -+ } -+ -+ return ret; -+} -+ -+int s5p_dsim_get_frame_done_status(void *dsim_data) -+{ -+ struct dsim_global *dsim = NULL; -+ -+ dsim = (struct dsim_global *)dsim_data; -+ -+ if (dsim == NULL) { -+ dev_err(dsim->dev, "dsim_global pointer is NULL.\n"); -+ return -EFAULT; -+ } -+ -+ return _s5p_dsim_get_frame_done_status(dsim); -+} -+ -+int s5p_dsim_clear_frame_done(void *dsim_data) -+{ -+ struct dsim_global *dsim = NULL; -+ -+ dsim = (struct dsim_global *)dsim_data; -+ -+ if (dsim == NULL) { -+ dev_err(dsim->dev, "dsim_global pointer is NULL.\n"); -+ return -EFAULT; -+ } -+ -+ _s5p_dsim_clear_frame_done(dsim); -+ -+ return 0; -+} -+ -+MODULE_AUTHOR("InKi Dae <a class="moz-txt-link-rfc2396E" href="mailto:inki.dae@samsung.com"><inki.dae@samsung.com></a>"); -+MODULE_DESCRIPTION("Samusung MIPI-DSIM common driver"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/video/s5p_dsim_common.h b/drivers/video/s5p_dsim_common.h -new file mode 100644 -index 0000000..deefca1 ---- /dev/null -+++ b/drivers/video/s5p_dsim_common.h -@@ -0,0 +1,38 @@ -+/* linux/drivers/video/samsung/s5p_dsim_common.h -+ * -+ * Header file for Samsung MIPI-DSI common driver. -+ * -+ * Copyright (c) 2009 Samsung Electronics -+ * InKi Dae <a class="moz-txt-link-rfc2396E" href="mailto:inki.dae@samsung.com"><inki.dae@samsung.com></a> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+*/ -+ -+#ifndef _S5P_DSIM_COMMON_H -+#define _S5P_DSIM_COMMON_H -+ -+extern int s5p_dsim_wr_data(void *dsim_data, unsigned int data_id, -+ unsigned int data0, unsigned int data1); -+extern int s5p_dsim_init_header_fifo(struct dsim_global *dsim); -+extern int s5p_dsim_pll_on(struct dsim_global *dsim, unsigned char enable); -+extern unsigned long s5p_dsim_change_pll(struct dsim_global *dsim, -+ unsigned char pre_divider, unsigned short main_divider, -+ unsigned char scaler); -+extern int s5p_dsim_set_clock(struct dsim_global *dsim, -+ unsigned char byte_clk_sel, unsigned char enable); -+extern int s5p_dsim_init_dsim(struct dsim_global *dsim); -+extern int s5p_dsim_set_display_mode(struct dsim_global *dsim, -+ struct dsim_lcd_config *main_lcd, struct dsim_lcd_config *sub_lcd); -+extern int s5p_dsim_init_link(struct dsim_global *dsim); -+extern int s5p_dsim_set_hs_enable(struct dsim_global *dsim); -+extern int s5p_dsim_set_data_transfer_mode(struct dsim_global *dsim, -+ unsigned char data_path, unsigned char hs_enable); -+extern int s5p_dsim_get_frame_done_status(void *dsim_data); -+extern int s5p_dsim_clear_frame_done(void *dsim_data); -+extern int s5p_dsim_enable_frame_done_int(struct dsim_global *dsim, int enable); -+ -+extern struct fb_info *registered_fb[FB_MAX] __read_mostly; -+ -+#endif /* _S5P_DSIM_COMMON_H */ -diff --git a/drivers/video/s5p_dsim_lowlevel.c b/drivers/video/s5p_dsim_lowlevel.c -new file mode 100644 -index 0000000..6a27395 ---- /dev/null -+++ b/drivers/video/s5p_dsim_lowlevel.c -@@ -0,0 +1,562 @@ -+/* linux/drivers/video/samsung/s5p-dsim.c -+ * -+ * Samsung MIPI-DSIM lowlevel driver. -+ * -+ * InKi Dae, <a class="moz-txt-link-rfc2396E" href="mailto:inki.dae@samsung.com"><inki.dae@samsung.com></a> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+*/ -+ -+#include <linux/module.h> -+#include <linux/kernel.h> -+#include <linux/errno.h> -+#include <linux/mutex.h> -+#include <linux/wait.h> -+#include <linux/delay.h> -+#include <linux/fs.h> -+#include <linux/mm.h> -+#include <linux/ctype.h> -+#include <linux/io.h> -+ -+#include <mach/map.h> -+ -+#include <plat/dsim.h> -+#include <plat/mipi_ddi.h> -+#include <plat/regs-dsim.h> -+ -+void s5p_dsim_func_reset(struct dsim_global *dsim) -+{ -+ unsigned int cfg = 0; -+ -+ cfg = DSIM_FUNCRST; -+ -+ writel(cfg, dsim->reg_base + S5P_DSIM_SWRST); -+} -+ -+void s5p_dsim_sw_reset(struct dsim_global *dsim) -+{ -+ unsigned int cfg = 0; -+ -+ cfg = DSIM_SWRST; -+ -+ writel(cfg, dsim->reg_base + S5P_DSIM_SWRST); -+} -+ -+void s5p_dsim_set_interrupt_mask(struct dsim_global *dsim, unsigned int mode, -+ unsigned int mask) -+{ -+ unsigned int reg = readl(dsim->reg_base + S5P_DSIM_INTMSK); -+ -+ if (mask) -+ reg |= mode; -+ else -+ reg &= ~(mode); -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_INTMSK); -+} -+ -+void s5p_dsim_init_fifo_pointer(struct dsim_global *dsim, unsigned char cfg) -+{ -+ unsigned int reg; -+ -+ reg = readl(dsim->reg_base + S5P_DSIM_FIFOCTRL); -+ -+ writel(reg & ~(cfg), dsim->reg_base + S5P_DSIM_FIFOCTRL); -+ mdelay(10); -+ reg |= cfg; -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_FIFOCTRL); -+} -+ -+/* -+ * this function set PLL P, M and S value in D-PHY -+ */ -+void s5p_dsim_set_phy_tunning(struct dsim_global *dsim, unsigned int value) -+{ -+ writel(DSIM_AFC_CTL(value), dsim->reg_base + S5P_DSIM_PHYACCHR); -+} -+ -+void s5p_dsim_set_main_disp_resol(struct dsim_global *dsim, -+ unsigned short vert_resol, unsigned short hori_resol) -+{ -+ unsigned int reg; -+ -+ /* standby should be set after configuration so set to not ready*/ -+ reg = (readl(dsim->reg_base + S5P_DSIM_MDRESOL)) & -+ ~(DSIM_MAIN_STAND_BY); -+ writel(reg, dsim->reg_base + S5P_DSIM_MDRESOL); -+ -+ reg &= ~(0x7ff << 16) & ~(0x7ff << 0); -+ reg |= DSIM_MAIN_VRESOL(vert_resol) | DSIM_MAIN_HRESOL(hori_resol); -+ -+ reg |= DSIM_MAIN_STAND_BY; -+ writel(reg, dsim->reg_base + S5P_DSIM_MDRESOL); -+} -+ -+void s5p_dsim_set_main_disp_vporch(struct dsim_global *dsim, -+ unsigned int cmd_allow, unsigned int vfront, unsigned int vback) -+{ -+ unsigned int reg; -+ -+ reg = (readl(dsim->reg_base + S5P_DSIM_MVPORCH)) & -+ ~(DSIM_CMD_ALLOW_MASK) & ~(DSIM_STABLE_VFP_MASK) & -+ ~(DSIM_MAIN_VBP_MASK); -+ -+ reg |= ((cmd_allow & 0xf) << DSIM_CMD_ALLOW_SHIFT) | -+ ((vfront & 0x7ff) << DSIM_STABLE_VFP_SHIFT) | -+ ((vback & 0x7ff) << DSIM_MAIN_VBP_SHIFT); -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_MVPORCH); -+} -+ -+void s5p_dsim_set_main_disp_hporch(struct dsim_global *dsim, -+ unsigned short front, unsigned short back) -+{ -+ unsigned int reg; -+ -+ reg = (readl(dsim->reg_base + S5P_DSIM_MHPORCH)) & -+ ~(DSIM_MAIN_HFP_MASK) & ~(DSIM_MAIN_HBP_MASK); -+ -+ reg |= (front << DSIM_MAIN_HFP_SHIFT) | (back << DSIM_MAIN_HBP_SHIFT); -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_MHPORCH); -+} -+ -+void s5p_dsim_set_main_disp_sync_area(struct dsim_global *dsim, -+ unsigned short vert, unsigned short hori) -+{ -+ unsigned int reg; -+ -+ reg = (readl(dsim->reg_base + S5P_DSIM_MSYNC)) & -+ ~(DSIM_MAIN_VSA_MASK) & ~(DSIM_MAIN_HSA_MASK); -+ -+ reg |= ((vert & 0x3ff) << DSIM_MAIN_VSA_SHIFT) | -+ (hori << DSIM_MAIN_HSA_SHIFT); -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_MSYNC); -+} -+ -+void s5p_dsim_set_sub_disp_resol(struct dsim_global *dsim, -+ unsigned short vert, unsigned short hori) -+{ -+ unsigned int reg; -+ -+ reg = (readl(dsim->reg_base + S5P_DSIM_SDRESOL)) & -+ ~(DSIM_SUB_STANDY_MASK); -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_SDRESOL); -+ -+ reg &= ~(DSIM_SUB_VRESOL_MASK) | ~(DSIM_SUB_HRESOL_MASK); -+ reg |= ((vert & 0x7ff) << DSIM_SUB_VRESOL_SHIFT) | -+ ((hori & 0x7ff) << DSIM_SUB_HRESOL_SHIFT); -+ writel(reg, dsim->reg_base + S5P_DSIM_SDRESOL); -+ -+ reg |= (1 << DSIM_SUB_STANDY_SHIFT); -+ writel(reg, dsim->reg_base + S5P_DSIM_SDRESOL); -+} -+ -+void s5p_dsim_init_config(struct dsim_global *dsim, -+ struct dsim_lcd_config *main_lcd_info, -+ struct dsim_lcd_config *sub_lcd_info, struct dsim_config *dsim_info) -+{ -+ unsigned int cfg = (readl(dsim->reg_base + S5P_DSIM_CONFIG)) & -+ ~(1 << 28) & ~(0x1f << 20) & ~(0x3 << 5); -+ -+ cfg = (dsim_info->auto_flush << 29) | -+ (dsim_info->eot_disable << 28) | -+ (dsim_info->auto_vertical_cnt << DSIM_AUTO_MODE_SHIFT) | -+ (dsim_info->hse << DSIM_HSE_MODE_SHIFT) | -+ (dsim_info->hfp << DSIM_HFP_MODE_SHIFT) | -+ (dsim_info->hbp << DSIM_HBP_MODE_SHIFT) | -+ (dsim_info->hsa << DSIM_HSA_MODE_SHIFT) | -+ (dsim_info->e_no_data_lane << DSIM_NUM_OF_DATALANE_SHIFT); -+ -+ writel(cfg, dsim->reg_base + S5P_DSIM_CONFIG); -+} -+ -+void s5p_dsim_display_config(struct dsim_global *dsim, -+ struct dsim_lcd_config *main_lcd, struct dsim_lcd_config *sub_lcd) -+{ -+ u32 reg = (readl(dsim->reg_base + S5P_DSIM_CONFIG)) & -+ ~(0x3 << 26) & ~(1 << 25) & ~(0x3 << 18) & ~(0x7 << 12) & -+ ~(0x3 << 16) & ~(0x7 << 8); -+ -+ if (main_lcd->e_interface == DSIM_VIDEO) -+ reg |= (1 << 25); -+ else if (main_lcd->e_interface == DSIM_COMMAND) -+ reg &= ~(1 << 25); -+ else { -+ dev_err(dsim->dev, "this ddi is not MIPI interface.\n"); -+ return; -+ } -+ -+ /* main lcd */ -+ reg |= ((u8) (main_lcd->parameter[DSI_VIDEO_MODE_SEL]) & 0x3) << 26 | -+ ((u8) (main_lcd->parameter[DSI_VIRTUAL_CH_ID]) & 0x3) << 18 | -+ ((u8) (main_lcd->parameter[DSI_FORMAT]) & 0x7) << 12; -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_CONFIG); -+} -+ -+void s5p_dsim_enable_lane(struct dsim_global *dsim, unsigned char lane, -+ unsigned char enable) -+{ -+ unsigned int reg; -+ -+ reg = readl(dsim->reg_base + S5P_DSIM_CONFIG); -+ -+ if (lane == DSIM_LANE_CLOCK) { -+ if (enable) -+ reg |= (1 << 0); -+ else -+ reg &= ~(1 << 0); -+ } else { -+ if (enable) -+ reg |= (lane << 1); -+ else -+ reg &= ~(lane << 1); -+ } -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_CONFIG); -+} -+ -+ -+void s5p_dsim_set_data_lane_number(struct dsim_global *dsim, -+ unsigned char count) -+{ -+ unsigned int cfg = 0; -+ -+ /* get the data lane number. */ -+ cfg = DSIM_NUM_OF_DATA_LANE(count); -+ -+ writel(cfg, dsim->reg_base + S5P_DSIM_CONFIG); -+} -+ -+void s5p_dsim_enable_afc(struct dsim_global *dsim, unsigned char enable, -+ unsigned char afc_code) -+{ -+ unsigned int reg = readl(dsim->reg_base + S5P_DSIM_PHYACCHR); -+ -+ if (enable) { -+ reg |= (1 << 14); -+ reg &= ~(0x7 << 5); -+ reg |= (afc_code & 0x7) << 5; -+ } else -+ reg &= ~(1 << 14); -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_PHYACCHR); -+} -+ -+void s5p_dsim_enable_pll_bypass(struct dsim_global *dsim, -+ unsigned char enable) -+{ -+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_CLKCTRL)) & -+ ~(DSIM_PLL_BYPASS_EXTERNAL); -+ -+ reg |= enable << DSIM_PLL_BYPASS_SHIFT; -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL); -+} -+ -+void s5p_dsim_set_pll_pms(struct dsim_global *dsim, unsigned char p, -+ unsigned short m, unsigned short s) -+{ -+ unsigned int reg = readl(dsim->reg_base + S5P_DSIM_PLLCTRL); -+ -+ reg |= ((p & 0x3f) << 13) | ((m & 0x1ff) << 4) | ((s & 0x7) << 1); -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL); -+} -+ -+void s5p_dsim_pll_freq_band(struct dsim_global *dsim, unsigned char freq_band) -+{ -+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) & -+ ~(0x1f << DSIM_FREQ_BAND_SHIFT); -+ -+ reg |= ((freq_band & 0x1f) << DSIM_FREQ_BAND_SHIFT); -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL); -+} -+ -+void s5p_dsim_pll_freq(struct dsim_global *dsim, unsigned char pre_divider, -+ unsigned short main_divider, unsigned char scaler) -+{ -+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) & -+ ~(0x7ffff << 1); -+ -+ reg |= (pre_divider & 0x3f) << 13 | (main_divider & 0x1ff) << 4 | -+ (scaler & 0x7) << 1; -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL); -+} -+ -+void s5p_dsim_pll_stable_time(struct dsim_global *dsim, -+ unsigned int lock_time) -+{ -+ writel(lock_time, dsim->reg_base + S5P_DSIM_PLLTMR); -+} -+ -+void s5p_dsim_enable_pll(struct dsim_global *dsim, unsigned char enable) -+{ -+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) & -+ ~(0x1 << DSIM_PLL_EN_SHIFT); -+ -+ reg |= ((enable & 0x1) << DSIM_PLL_EN_SHIFT); -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL); -+} -+ -+void s5p_dsim_set_byte_clock_src(struct dsim_global *dsim, unsigned char src) -+{ -+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_CLKCTRL)) & -+ ~(0x3 << DSIM_BYTE_CLK_SRC_SHIFT); -+ -+ reg |= ((unsigned int) src) << DSIM_BYTE_CLK_SRC_SHIFT; -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL); -+} -+ -+void s5p_dsim_enable_byte_clock(struct dsim_global *dsim, -+ unsigned char enable) -+{ -+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_CLKCTRL)) & -+ ~(1 << DSIM_BYTE_CLKEN_SHIFT); -+ -+ reg |= enable << DSIM_BYTE_CLKEN_SHIFT; -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL); -+} -+ -+void s5p_dsim_set_esc_clk_prs(struct dsim_global *dsim, unsigned char enable, -+ unsigned short prs_val) -+{ -+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_CLKCTRL)) & -+ ~(1 << DSIM_ESC_CLKEN_SHIFT) & ~(0xffff); -+ -+ reg |= enable << DSIM_ESC_CLKEN_SHIFT; -+ if (enable) -+ reg |= prs_val; -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL); -+} -+ -+void s5p_dsim_enable_esc_clk_on_lane(struct dsim_global *dsim, -+ unsigned char lane_sel, unsigned char enable) -+{ -+ unsigned int reg = readl(dsim->reg_base + S5P_DSIM_CLKCTRL); -+ -+ if (enable) { -+ if (lane_sel & DSIM_LANE_CLOCK) -+ reg |= 1 << DSIM_LANE_ESC_CLKEN_SHIFT; -+ if (lane_sel & DSIM_LANE_DATA0) -+ reg |= 1 << (DSIM_LANE_ESC_CLKEN_SHIFT + 1); -+ if (lane_sel & DSIM_LANE_DATA1) -+ reg |= 1 << (DSIM_LANE_ESC_CLKEN_SHIFT + 2); -+ if (lane_sel & DSIM_LANE_DATA2) -+ reg |= 1 << (DSIM_LANE_ESC_CLKEN_SHIFT + 3); -+ if (lane_sel & DSIM_LANE_DATA2) -+ reg |= 1 << (DSIM_LANE_ESC_CLKEN_SHIFT + 4); -+ } else { -+ if (lane_sel & DSIM_LANE_CLOCK) -+ reg &= ~(1 << DSIM_LANE_ESC_CLKEN_SHIFT); -+ if (lane_sel & DSIM_LANE_DATA0) -+ reg &= ~(1 << (DSIM_LANE_ESC_CLKEN_SHIFT + 1)); -+ if (lane_sel & DSIM_LANE_DATA1) -+ reg &= ~(1 << (DSIM_LANE_ESC_CLKEN_SHIFT + 2)); -+ if (lane_sel & DSIM_LANE_DATA2) -+ reg &= ~(1 << (DSIM_LANE_ESC_CLKEN_SHIFT + 3)); -+ if (lane_sel & DSIM_LANE_DATA2) -+ reg &= ~(1 << (DSIM_LANE_ESC_CLKEN_SHIFT + 4)); -+ } -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL); -+} -+ -+void s5p_dsim_force_dphy_stop_state(struct dsim_global *dsim, -+ unsigned char enable) -+{ -+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_ESCMODE)) & -+ ~(0x1 << DSIM_FORCE_STOP_STATE_SHIFT); -+ -+ reg |= ((enable & 0x1) << DSIM_FORCE_STOP_STATE_SHIFT); -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_ESCMODE); -+} -+ -+unsigned char s5p_dsim_is_lane_state(struct dsim_global *dsim, -+ unsigned char lane) -+{ -+ unsigned int reg = readl(dsim->reg_base + S5P_DSIM_STATUS); -+ -+ if ((lane & DSIM_LANE_ALL) > DSIM_LANE_CLOCK) { /* all lane state */ -+ if ((reg & 0x7ff) ^ (((lane & 0xf) << 4) | (1 << 9))) -+ return DSIM_LANE_STATE_ULPS; -+ else if ((reg & 0x7ff) ^ (((lane & 0xf) << 0) | (1 << 8))) -+ return DSIM_LANE_STATE_STOP; -+ else { -+ dev_err(dsim->dev, "land state is unknown.\n"); -+ return -1; -+ } -+ } else if (lane & DSIM_LANE_DATA_ALL) { /* data lane */ -+ if (reg & (lane << 4)) -+ return DSIM_LANE_STATE_ULPS; -+ else if (reg & (lane << 0)) -+ return DSIM_LANE_STATE_STOP; -+ else { -+ dev_err(dsim->dev, "data lane state is unknown.\n"); -+ return -1; -+ } -+ } else if (lane & DSIM_LANE_CLOCK) { /* clock lane */ -+ if (reg & (1 << 9)) -+ return DSIM_LANE_STATE_ULPS; -+ else if (reg & (1 << 8)) -+ return DSIM_LANE_STATE_STOP; -+ else if (reg & (1 << 10)) -+ return DSIM_LANE_STATE_HS_READY; -+ else { -+ dev_err(dsim->dev, "data lane state is unknown.\n"); -+ return -1; -+ } -+ } -+ -+ return 0; -+} -+ -+void s5p_dsim_set_stop_state_counter(struct dsim_global *dsim, -+ unsigned short cnt_val) -+{ -+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_ESCMODE)) & -+ ~(0x7ff << DSIM_STOP_STATE_CNT_SHIFT); -+ -+ reg |= ((cnt_val & 0x7ff) << DSIM_STOP_STATE_CNT_SHIFT); -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_ESCMODE); -+} -+ -+void s5p_dsim_set_bta_timeout(struct dsim_global *dsim, unsigned char timeout) -+{ -+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_TIMEOUT)) & -+ ~(0xff << DSIM_BTA_TOUT_SHIFT); -+ -+ reg |= (timeout << DSIM_BTA_TOUT_SHIFT); -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_TIMEOUT); -+} -+ -+void s5p_dsim_set_lpdr_timeout(struct dsim_global *dsim, -+ unsigned short timeout) -+{ -+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_TIMEOUT)) & -+ ~(0xffff << DSIM_LPDR_TOUT_SHIFT); -+ -+ reg |= (timeout << DSIM_LPDR_TOUT_SHIFT); -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_TIMEOUT); -+} -+ -+void s5p_dsim_set_data_mode(struct dsim_global *dsim, unsigned char data, -+ unsigned char state) -+{ -+ unsigned int reg = readl(dsim->reg_base + S5P_DSIM_ESCMODE); -+ -+ if (state == DSIM_STATE_HSCLKEN) -+ reg &= ~data; -+ else -+ reg |= data; -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_ESCMODE); -+} -+ -+void s5p_dsim_enable_hs_clock(struct dsim_global *dsim, unsigned char enable) -+{ -+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_CLKCTRL)) & -+ ~(1 << DSIM_TX_REQUEST_HSCLK_SHIFT); -+ -+ reg |= enable << DSIM_TX_REQUEST_HSCLK_SHIFT; -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL); -+} -+ -+void s5p_dsim_dp_dn_swap(struct dsim_global *dsim, unsigned char swap_en) -+{ -+ unsigned int reg = readl(dsim->reg_base + S5P_DSIM_PHYACCHR1); -+ -+ reg &= ~(0x3 << 0); -+ reg |= (swap_en & 0x3) << 0; -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_PHYACCHR1); -+} -+ -+void s5p_dsim_hs_zero_ctrl(struct dsim_global *dsim, unsigned char hs_zero) -+{ -+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) & -+ ~(0xf << 28); -+ -+ reg |= ((hs_zero & 0xf) << 28); -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL); -+} -+ -+void s5p_dsim_prep_ctrl(struct dsim_global *dsim, unsigned char prep) -+{ -+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) & -+ ~(0x7 << 20); -+ -+ reg |= ((prep & 0x7) << 20); -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL); -+} -+ -+void s5p_dsim_clear_interrupt(struct dsim_global *dsim, unsigned int int_src) -+{ -+ unsigned int reg = readl(dsim->reg_base + S5P_DSIM_INTSRC); -+ -+ reg |= int_src; -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_INTSRC); -+} -+ -+unsigned char s5p_dsim_is_pll_stable(struct dsim_global *dsim) -+{ -+ return (unsigned char) ((readl(dsim->reg_base + S5P_DSIM_STATUS) & -+ (1 << 31)) >> 31); -+} -+ -+unsigned int s5p_dsim_get_fifo_state(struct dsim_global *dsim) -+{ -+ unsigned int ret = 0; -+ -+ ret = (readl(dsim->reg_base + S5P_DSIM_FIFOCTRL) & ~(0x1f)); -+ -+ return ret; -+} -+ -+void s5p_dsim_wr_tx_header(struct dsim_global *dsim, -+ unsigned char di, unsigned char data0, unsigned char data1) -+{ -+ unsigned int reg = (data1 << 16) | (data0 << 8) | ((di & 0x3f) << 0); -+ -+ writel(reg, dsim->reg_base + S5P_DSIM_PKTHDR); -+} -+ -+unsigned int _s5p_dsim_get_frame_done_status(struct dsim_global *dsim) -+{ -+ unsigned int reg = readl(dsim->reg_base + S5P_DSIM_INTSRC); -+ -+ return (reg & INTSRC_FRAME_DONE) ? 1 : 0; -+} -+ -+void _s5p_dsim_clear_frame_done(struct dsim_global *dsim) -+{ -+ unsigned int reg = readl(dsim->reg_base + S5P_DSIM_INTSRC); -+ -+ writel(reg | INTSRC_FRAME_DONE, dsim->reg_base + -+ S5P_DSIM_INTSRC); -+} -+ -+void s5p_dsim_wr_tx_data(struct dsim_global *dsim, unsigned int tx_data) -+{ -+ writel(tx_data, dsim->reg_base + S5P_DSIM_PAYLOAD); -+} -diff --git a/drivers/video/s5p_dsim_lowlevel.h b/drivers/video/s5p_dsim_lowlevel.h -new file mode 100644 -index 0000000..ff950ba ---- /dev/null -+++ b/drivers/video/s5p_dsim_lowlevel.h -@@ -0,0 +1,101 @@ -+/* linux/drivers/video/samsung/s5p_dsim_lowlevel.h -+ * -+ * Header file for Samsung MIPI-DSIM lowlevel driver. -+ * -+ * Copyright (c) 2009 Samsung Electronics -+ * InKi Dae <a class="moz-txt-link-rfc2396E" href="mailto:inki.dae@samsung.com"><inki.dae@samsung.com></a> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+*/ -+ -+#ifndef _S5P_DSIM_LOWLEVEL_H -+#define _S5P_DSIM_LOWLEVEL_H -+ -+struct dsim_global; -+ -+extern void s5p_dsim_func_reset(struct dsim_global *dsim); -+extern void s5p_dsim_sw_reset(struct dsim_global *dsim); -+extern void s5p_dsim_set_interrupt_mask(struct dsim_global *dsim, -+ unsigned int mode, unsigned int mask); -+extern void s5p_dsim_set_data_lane_number(struct dsim_global *dsim, -+ unsigned char count); -+extern void s5p_dsim_init_fifo_pointer(struct dsim_global *dsim, -+ unsigned char cfg); -+extern void s5p_dsim_set_phy_tunning(struct dsim_global *dsim, -+ unsigned int value); -+extern void s5p_dsim_set_phy_tunning(struct dsim_global *dsim, -+ unsigned int value); -+extern void s5p_dsim_set_main_disp_resol(struct dsim_global *dsim, -+ unsigned short vert_resol, unsigned short hori_resol); -+extern void s5p_dsim_set_main_disp_vporch(struct dsim_global *dsim, -+ unsigned short cmd_allow, unsigned short vfront, unsigned short vback); -+extern void s5p_dsim_set_main_disp_hporch(struct dsim_global *dsim, -+ unsigned short front, unsigned short back); -+extern void s5p_dsim_set_main_disp_sync_area(struct dsim_global *dsim, -+ unsigned short vert, unsigned short hori); -+extern void s5p_dsim_set_sub_disp_resol(struct dsim_global *dsim, -+ unsigned short vert, unsigned short hori); -+extern void s5p_dsim_init_config(struct dsim_global *dsim, -+ struct dsim_lcd_config *main_lcd_info, -+ struct dsim_lcd_config *sub_lcd_info, struct dsim_config *dsim_info); -+extern void s5p_dsim_display_config(struct dsim_global *dsim, -+ struct dsim_lcd_config *main_lcd, struct dsim_lcd_config *sub_lcd); -+extern void s5p_dsim_set_data_lane_number(struct dsim_global *dsim, -+ unsigned char count); -+extern void s5p_dsim_enable_lane(struct dsim_global *dsim, unsigned char lane, -+ unsigned char enable); -+extern void s5p_dsim_enable_afc(struct dsim_global *dsim, unsigned char enable, -+ unsigned char afc_code); -+extern void s5p_dsim_enable_pll_bypass(struct dsim_global *dsim, -+ unsigned char enable); -+extern void s5p_dsim_set_pll_pms(struct dsim_global *dsim, unsigned char p, -+ unsigned short m, unsigned short s); -+extern void s5p_dsim_pll_freq_band(struct dsim_global *dsim, -+ unsigned char freq_band); -+extern void s5p_dsim_pll_freq(struct dsim_global *dsim, -+ unsigned char pre_divider, unsigned short main_divider, -+ unsigned char scaler); -+extern void s5p_dsim_pll_stable_time(struct dsim_global *dsim, -+ unsigned int lock_time); -+extern void s5p_dsim_enable_pll(struct dsim_global *dsim, -+ unsigned char enable); -+extern void s5p_dsim_set_byte_clock_src(struct dsim_global *dsim, -+ unsigned char src); -+extern void s5p_dsim_enable_byte_clock(struct dsim_global *dsim, -+ unsigned char enable); -+extern void s5p_dsim_set_esc_clk_prs(struct dsim_global *dsim, -+ unsigned char enable, unsigned short prs_val); -+extern void s5p_dsim_enable_esc_clk_on_lane(struct dsim_global *dsim, -+ unsigned char lane_sel, unsigned char enable); -+extern void s5p_dsim_force_dphy_stop_state(struct dsim_global *dsim, -+ unsigned char enable); -+extern unsigned char s5p_dsim_is_lane_state(struct dsim_global *dsim, -+ unsigned char lane); -+extern void s5p_dsim_set_stop_state_counter(struct dsim_global *dsim, -+ unsigned short cnt_val); -+extern void s5p_dsim_set_bta_timeout(struct dsim_global *dsim, -+ unsigned char timeout); -+extern void s5p_dsim_set_lpdr_timeout(struct dsim_global *dsim, -+ unsigned short timeout); -+extern void s5p_dsim_set_data_mode(struct dsim_global *dsim, -+ unsigned char data, unsigned char state); -+extern void s5p_dsim_enable_hs_clock(struct dsim_global *dsim, -+ unsigned char enable); -+extern void s5p_dsim_dp_dn_swap(struct dsim_global *dsim, -+ unsigned char swap_en); -+extern void s5p_dsim_hs_zero_ctrl(struct dsim_global *dsim, -+ unsigned char hs_zero); -+extern void s5p_dsim_prep_ctrl(struct dsim_global *dsim, unsigned char prep); -+extern void s5p_dsim_clear_interrupt(struct dsim_global *dsim, -+ unsigned int int_src); -+extern unsigned char s5p_dsim_is_pll_stable(struct dsim_global *dsim); -+extern unsigned int s5p_dsim_get_fifo_state(struct dsim_global *dsim); -+extern unsigned int _s5p_dsim_get_frame_done_status(struct dsim_global *dsim); -+extern void _s5p_dsim_clear_frame_done(struct dsim_global *dsim); -+extern void s5p_dsim_wr_tx_header(struct dsim_global *dsim, -+ unsigned char di, unsigned char data0, unsigned char data1); -+extern void s5p_dsim_wr_tx_data(struct dsim_global *dsim, unsigned int tx_data); -+ -+#endif /* _S5P_DSIM_LOWLEVEL_H */ -</pre> -<br> -</body> -</html> diff --git a/a/1.2.hdr b/a/1.2.hdr deleted file mode 100644 index 17e3fb4..0000000 --- a/a/1.2.hdr +++ /dev/null @@ -1,2 +0,0 @@ -Content-type: text/html; charset=EUC-KR -Content-transfer-encoding: 7BIT diff --git a/a/1.1.txt b/N1/1.txt similarity index 99% rename from a/1.1.txt rename to N1/1.txt index 07a1c47..300bec5 100644 --- a/a/1.1.txt +++ b/N1/1.txt @@ -14,8 +14,8 @@ struct s5p_platform_dsim - define callbacks for initializing D-PHY, MIPI reset and trigger releated interfaces of s3c-fb.c file. -Signed-off-by: InKi Dae <inki.dae@samsung.com <mailto:p.osciak@samsung.com>> -Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com +Signed-off-by: InKi Dae <inki.dae at samsung.com <mailto:p.osciak@samsung.com>> +Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com <mailto:kyungmin.park@samsung.com>> --- @@ -3086,3 +3086,8 @@ index 0000000..ff950ba +extern void s5p_dsim_wr_tx_data(struct dsim_global *dsim, unsigned int tx_data); + +#endif /* _S5P_DSIM_LOWLEVEL_H */ + + +-------------- next part -------------- +An HTML attachment was scrubbed... +URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20100702/2b6784e7/attachment-0001.html> diff --git a/a/2.hdr b/a/2.hdr deleted file mode 100644 index 4b86001..0000000 --- a/a/2.hdr +++ /dev/null @@ -1,4 +0,0 @@ -Content-Type: text/plain; charset="us-ascii" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Content-Disposition: inline diff --git a/a/2.txt b/a/2.txt deleted file mode 100644 index 8133cf0..0000000 --- a/a/2.txt +++ /dev/null @@ -1,4 +0,0 @@ -_______________________________________________ -linux-arm-kernel mailing list -linux-arm-kernel@lists.infradead.org -http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/a/content_digest b/N1/content_digest index c874081..bf18265 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,14 +1,10 @@ "ref\04C29AF72.6090200@samsung.com\0" "ref\04C29C766.7010901@samsung.com\0" - "From\0InKi Dae <inki.dae@samsung.com>\0" + "From\0inki.dae@samsung.com (InKi Dae)\0" "Subject\0[PATCH 2/2] S5PV210: Add MIPI-DSI Driver.\0" "Date\0Fri, 02 Jul 2010 17:51:21 +0900\0" - "To\0linux-arm-kernel@lists.infradead.org" - linux-fbdev-devel@lists.sourceforge.net - akpm@linux-foundation.org - Ben Dooks <ben-linux@fluff.org> - " kmpark@infradead.org\0" - "\02:1.1\0" + "To\0linux-arm-kernel@lists.infradead.org\0" + "\00:1\0" "b\0" "this patch addes MIPI-DSI Driver.\n" "\n" @@ -26,8 +22,8 @@ "- define callbacks for initializing D-PHY, MIPI reset and trigger\n" "releated interfaces of s3c-fb.c file.\n" "\n" - "Signed-off-by: InKi Dae <inki.dae@samsung.com <mailto:p.osciak@samsung.com>>\n" - "Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com\n" + "Signed-off-by: InKi Dae <inki.dae at samsung.com <mailto:p.osciak@samsung.com>>\n" + "Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com\n" "<mailto:kyungmin.park@samsung.com>>\n" "---\n" "\n" @@ -3097,3112 +3093,11 @@ "+\tunsigned char di, unsigned char data0, unsigned char data1);\n" "+extern void s5p_dsim_wr_tx_data(struct dsim_global *dsim, unsigned int tx_data);\n" "+\n" - +#endif /* _S5P_DSIM_LOWLEVEL_H */ - "\02:1.2\0" - "b\0" - "<!DOCTYPE HTML PUBLIC \"-//W3C//DTD HTML 4.01 Transitional//EN\">\n" - "<html>\n" - "<head>\n" - " <meta content=\"text/html; charset=EUC-KR\" http-equiv=\"Content-Type\">\n" - "</head>\n" - "<body bgcolor=\"#ffffff\" text=\"#000000\">\n" - "this patch addes MIPI-DSI Driver.<br>\n" - "<br>\n" - "to use this driver, some structures below should be added to machine\n" - "specific file.<br>\n" - "<br>\n" - "struct dsim_config<br>\n" - "- define clock info, data lane count and video mode info for MIPI-DSI\n" - "Controller.<br>\n" - "<br>\n" - "struct dsim_lcd_config<br>\n" - "- define interface mode, channel ID, Pixel format and so on.<br>\n" - "<br>\n" - "struct s5p_platform_dsim<br>\n" - "- define callbacks for initializing D-PHY, MIPI reset and trigger\n" - "releated interfaces of s3c-fb.c file.<br>\n" - "<br>\n" - "Signed-off-by: InKi Dae <<a href=\"mailto:p.osciak@samsung.com\">inki.dae@samsung.com</a>><br>\n" - "Signed-off-by: Kyungmin Park <<a\n" - " href=\"mailto:kyungmin.park@samsung.com\">kyungmin.park@samsung.com</a>><br>\n" - "---<br>\n" - "<br>\n" - "<pre>diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h\n" - "index 2a25ab4..f716678 100644\n" - "--- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h\n" - "+++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h\n" - "@@ -162,6 +162,7 @@\n" - " \n" - " /* MIPI */\n" - " #define S5P_MIPI_DPHY_EN\t\t(3)\n" - "+#define S5P_MIPI_M_RESETN\t\t(1 << 1)\n" - " \n" - " /* S5P_DAC_CONTROL */\n" - " #define S5P_DAC_ENABLE\t\t\t(1)\n" - "diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile\n" - "index b1d82cc..3cd43f2 100644\n" - "--- a/arch/arm/plat-samsung/Makefile\n" - "+++ b/arch/arm/plat-samsung/Makefile\n" - "@@ -49,6 +49,9 @@ obj-$(CONFIG_S3C_DEV_RTC)\t+= dev-rtc.o\n" - " obj-$(CONFIG_SAMSUNG_DEV_ADC)\t+= dev-adc.o\n" - " obj-$(CONFIG_SAMSUNG_DEV_TS)\t+= dev-ts.o\n" - " \n" - "+# Device setup - MIPI-DSI\n" - "+obj-$(CONFIG_S5P_MIPI_DSI) += setup-dsim.o\n" - "+\n" - " # DMA support\n" - " \n" - " obj-$(CONFIG_S3C_DMA)\t\t+= dma.o\n" - "diff --git a/arch/arm/plat-samsung/include/plat/dsim.h b/arch/arm/plat-samsung/include/plat/dsim.h\n" - "new file mode 100644\n" - "index 0000000..28bc595\n" - "--- /dev/null\n" - "+++ b/arch/arm/plat-samsung/include/plat/dsim.h\n" - "@@ -0,0 +1,470 @@\n" - "+/* linux/arm/arch/mach-s5pc110/include/mach/dsim.h\n" - "+ *\n" - "+ * Platform data header for Samsung MIPI-DSIM.\n" - "+ *\n" - "+ * Copyright (c) 2009 Samsung Electronics\n" - "+ * InKi Dae <a class=\"moz-txt-link-rfc2396E\" href=\"mailto:inki.dae@samsung.com\"><inki.dae@samsung.com></a>\n" - "+ *\n" - "+ * This program is free software; you can redistribute it and/or modify\n" - "+ * it under the terms of the GNU General Public License version 2 as\n" - "+ * published by the Free Software Foundation.\n" - "+*/\n" - "+\n" - "+#ifndef _DSIM_H\n" - "+#define _DSIM_H\n" - "+\n" - "+#include <linux/device.h>\n" - "+\n" - "+/* h/w configuration */\n" - "+#define MIPI_FIN\t\t24000000\n" - "+#define DSIM_TIMEOUT_MS\t\t5000\n" - "+#define DSIM_NO_OF_INTERRUPT\t26\n" - "+#define DSIM_PM_STABLE_TIME\t10\n" - "+\n" - "+#define DSIM_TRUE\t\t1\n" - "+#define DSIM_FALSE\t\t0\n" - "+\n" - "+#define DSIM_HEADER_FIFO_SZ\t16\n" - "+\n" - "+enum dsim_interface_type {\n" - "+\tDSIM_COMMAND = 0,\n" - "+\tDSIM_VIDEO = 1,\n" - "+};\n" - "+\n" - "+enum dsim_state {\n" - "+\tDSIM_STATE_RESET = 0,\n" - "+\tDSIM_STATE_INIT = 1,\n" - "+\tDSIM_STATE_STOP = 2,\n" - "+\tDSIM_STATE_HSCLKEN = 3,\n" - "+\tDSIM_STATE_ULPS = 4,\n" - "+};\n" - "+\n" - "+enum {\n" - "+\tDSIM_NONE_STATE = 0,\n" - "+\tDSIM_RESUME_COMPLETE = 1,\n" - "+\tDSIM_FRAME_DONE = 2,\n" - "+};\n" - "+\n" - "+enum dsim_virtual_ch_no {\n" - "+\tDSIM_VIRTUAL_CH_0 = 0,\n" - "+\tDSIM_VIRTUAL_CH_1 = 1,\n" - "+\tDSIM_VIRTUAL_CH_2 = 2,\n" - "+\tDSIM_VIRTUAL_CH_3 = 3,\n" - "+};\n" - "+\n" - "+enum dsim_video_mode_type {\n" - "+\tDSIM_NON_BURST_SYNC_EVENT = 0,\n" - "+\tDSIM_NON_BURST_SYNC_PULSE = 2,\n" - "+\tDSIM_BURST = 3,\n" - "+\tDSIM_NON_VIDEO_MODE = 4,\n" - "+};\n" - "+\n" - "+enum dsim_fifo_state {\n" - "+\tDSIM_RX_DATA_FULL = (1 << 25),\n" - "+\tDSIM_RX_DATA_EMPTY = (1 << 24),\n" - "+\tSFR_HEADER_FULL = (1 << 23),\n" - "+\tSFR_HEADER_EMPTY = (1 << 22),\n" - "+\tSFR_PAYLOAD_FULL = (1 << 21),\n" - "+\tSFR_PAYLOAD_EMPTY = (1 << 20),\n" - "+\tI80_HEADER_FULL = (1 << 19),\n" - "+\tI80_HEADER_EMPTY = (1 << 18),\n" - "+\tI80_PALOAD_FULL = (1 << 17),\n" - "+\tI80_PALOAD_EMPTY = (1 << 16),\n" - "+\tSUB_DISP_HEADER_FULL = (1 << 15),\n" - "+\tSUB_DISP_HEADER_EMPTY = (1 << 14),\n" - "+\tSUB_DISP_PAYLOAD_FULL = (1 << 13),\n" - "+\tSUB_DISP_PAYLOAD_EMPTY = (1 << 12),\n" - "+\tMAIN_DISP_HEADER_FULL = (1 << 11),\n" - "+\tMAIN_DISP_HEADER_EMPTY = (1 << 10),\n" - "+\tMAIN_DISP_PAYLOAD_FULL = (1 << 9),\n" - "+\tMAIN_DISP_PAYLOAD_EMPTY = (1 << 8),\n" - "+};\n" - "+\n" - "+enum dsim_no_of_data_lane {\n" - "+\tDSIM_DATA_LANE_1 = 0,\n" - "+\tDSIM_DATA_LANE_2 = 1,\n" - "+\tDSIM_DATA_LANE_3 = 2,\n" - "+\tDSIM_DATA_LANE_4 = 3,\n" - "+};\n" - "+\n" - "+enum dsim_byte_clk_src {\n" - "+\tDSIM_PLL_OUT_DIV8 = 0,\n" - "+\tDSIM_EXT_CLK_DIV8 = 1,\n" - "+\tDSIM_EXT_CLK_BYPASS = 2,\n" - "+};\n" - "+\n" - "+enum dsim_lane {\n" - "+\tDSIM_LANE_DATA0 = (1 << 0),\n" - "+\tDSIM_LANE_DATA1 = (1 << 1),\n" - "+\tDSIM_LANE_DATA2 = (1 << 2),\n" - "+\tDSIM_LANE_DATA3 = (1 << 3),\n" - "+\tDSIM_LANE_DATA_ALL = 0xf,\n" - "+\tDSIM_LANE_CLOCK = (1 << 4),\n" - "+\tDSIM_LANE_ALL = DSIM_LANE_CLOCK | DSIM_LANE_DATA_ALL,\n" - "+};\n" - "+\n" - "+enum dsim_pixel_format {\n" - "+\tDSIM_CMD_3BPP = 0,\n" - "+\tDSIM_CMD_8BPP = 1,\n" - "+\tDSIM_CMD_12BPP = 2,\n" - "+\tDSIM_CMD_16BPP = 3,\n" - "+\tDSIM_VID_16BPP_565 = 4,\n" - "+\tDSIM_VID_18BPP_666PACKED = 5,\n" - "+\tDSIM_18BPP_666LOOSELYPACKED = 6,\n" - "+\tDSIM_24BPP_888 = 7,\n" - "+};\n" - "+\n" - "+enum dsim_lane_state {\n" - "+\tDSIM_LANE_STATE_HS_READY,\n" - "+\tDSIM_LANE_STATE_ULPS,\n" - "+\tDSIM_LANE_STATE_STOP,\n" - "+\tDSIM_LANE_STATE_LPDT,\n" - "+};\n" - "+\n" - "+enum dsim_transfer {\n" - "+\tDSIM_TRANSFER_NEITHER\t= 0,\n" - "+\tDSIM_TRANSFER_BYCPU\t= (1 << 7),\n" - "+\tDSIM_TRANSFER_BYLCDC\t= (1 << 6),\n" - "+\tDSIM_TRANSFER_BOTH\t= (0x3 << 6)\n" - "+};\n" - "+\n" - "+enum dsim_lane_change {\n" - "+\tDSIM_NO_CHANGE = 0,\n" - "+\tDSIM_DATA_LANE_CHANGE = 1,\n" - "+\tDSIM_CLOCK_NALE_CHANGE = 2,\n" - "+\tDSIM_ALL_LANE_CHANGE = 3,\n" - "+};\n" - "+\n" - "+enum dsim_int_src {\n" - "+\tDSIM_ALL_OF_INTR = 0xffffffff,\n" - "+\tDSIM_PLL_STABLE = (1 << 31),\n" - "+};\n" - "+\n" - "+enum dsim_data_id {\n" - "+\t/* short packet types of packet types for command */\n" - "+\tGEN_SHORT_WR_NO_PARA\t= 0x03,\n" - "+\tGEN_SHORT_WR_1_PARA\t= 0x13,\n" - "+\tGEN_SHORT_WR_2_PARA\t= 0x23,\n" - "+\tGEN_RD_NO_PARA\t\t= 0x04,\n" - "+\tGEN_RD_1_PARA\t\t= 0x14,\n" - "+\tGEN_RD_2_PARA\t\t= 0x24,\n" - "+\tDCS_WR_NO_PARA\t\t= 0x05,\n" - "+\tDCS_WR_1_PARA\t\t= 0x15,\n" - "+\tDCS_RD_NO_PARA\t\t= 0x06,\n" - "+\tSET_MAX_RTN_PKT_SIZE\t= 0x37,\n" - "+\n" - "+\t/* long packet types of packet types for command */\n" - "+\tNULL_PKT\t\t= 0x09,\n" - "+\tBLANKING_PKT\t\t= 0x19,\n" - "+\tGEN_LONG_WR\t\t= 0x29,\n" - "+\tDCS_LONG_WR\t\t= 0x39,\n" - "+\n" - "+\t/* short packet types of generic command */\n" - "+\tCMD_OFF\t\t\t= 0x02,\n" - "+\tCMD_ON\t\t\t= 0x12,\n" - "+\tSHUT_DOWN\t\t= 0x22,\n" - "+\tTURN_ON\t\t\t= 0x32,\n" - "+\n" - "+\t/* short packet types for video data */\n" - "+\tVSYNC_START\t\t= 0x01,\n" - "+\tVSYNC_END\t\t= 0x11,\n" - "+\tHSYNC_START\t\t= 0x21,\n" - "+\tHSYNC_END\t\t= 0x31,\n" - "+\tEOT_PKT\t\t\t= 0x08,\n" - "+\n" - "+\t/* long packet types for video data */\n" - "+\tRGB565_PACKED\t\t= 0x0e,\n" - "+\tRGB666_PACKED\t\t= 0x1e,\n" - "+\tRGB666_LOOSLY\t\t= 0x2e,\n" - "+\tRGB888_PACKED\t\t= 0x3e,\n" - "+};\n" - "+\n" - "+/**\n" - "+ * struct dsim_config - interface for configuring mipi-dsi controller.\n" - "+ *\n" - "+ * @auto_flush: enable or disable Auto flush of MD FIFO using VSYNC pulse.\n" - "+ * @eot_disable: enable or disable EoT packet in HS mode.\n" - "+ * @auto_vertical_cnt: specifies auto vertical count mode.\n" - "+ *\tin Video mode, the vertical line transition uses line counter\n" - "+ *\tconfigured by VSA, VBP, and Vertical resolution.\n" - "+ *\tIf this bit is set to '1', the line counter does not use VSA and VBP\n" - "+ *\tregisters.(in command mode, this variable is ignored)\n" - "+ * @hse: set horizontal sync event mode.\n" - "+ *\tIn VSYNC pulse and Vporch area, MIPI DSI master transfers only HSYNC\n" - "+ *\tstart packet to MIPI DSI slave at MIPI DSI spec1.1r02.\n" - "+ *\tthis bit transfers HSYNC end packet in VSYNC pulse and Vporch area\n" - "+ *\t(in mommand mode, this variable is ignored)\n" - "+ * @hfp: specifies HFP disable mode.\n" - "+ *\tif this variable is set, DSI master ignores HFP area in VIDEO mode.\n" - "+ *\t(in command mode, this variable is ignored)\n" - "+ * @hbp: specifies HBP disable mode.\n" - "+ *\tif this variable is set, DSI master ignores HBP area in VIDEO mode.\n" - "+ *\t(in command mode, this variable is ignored)\n" - "+ * @hsa: specifies HSA disable mode.\n" - "+ *\tif this variable is set, DSI master ignores HSA area in VIDEO mode.\n" - "+ *\t(in command mode, this variable is ignored)\n" - "+ * @e_no_data_lane: specifies data lane count to be used by Master.\n" - "+ * @e_byte_clk: select byte clock source. (it must be DSIM_PLL_OUT_DIV8)\n" - "+ *\tDSIM_EXT_CLK_DIV8 and DSIM_EXT_CLK_BYPASSS are not supported.\n" - "+ * @pll_stable_time: specifies the PLL Timer for stability of the ganerated\n" - "+ *\tclock(System clock cycle base)\n" - "+ *\tif the timer value goes to 0x00000000, the clock stable bit of status\n" - "+ *\tand interrupt register is set.\n" - "+ * @esc_clk: specifies escape clock frequency for getting the escape clock\n" - "+ *\tprescaler value.\n" - "+ * @stop_holding_cnt: specifies the interval value between transmitting\n" - "+ *\tread packet(or write \"set_tear_on\" command) and BTA request.\n" - "+ *\tafter transmitting read packet or write \"set_tear_on\" command,\n" - "+ *\tBTA requests to D-PHY automatically. this counter value specifies\n" - "+ *\tthe interval between them.\n" - "+ * @bta_timeout: specifies the timer for BTA.\n" - "+ *\tthis register specifies time out from BTA request to change\n" - "+ *\tthe direction with respect to Tx escape clock.\n" - "+ * @rx_timeout: specifies the timer for LP Rx mode timeout.\n" - "+ *\tthis register specifies time out on how long RxValid deasserts,\n" - "+ *\tafter RxLpdt asserts with respect to Tx escape clock.\n" - "+ *\t- RxValid specifies Rx data valid indicator.\n" - "+ *\t- RxLpdt specifies an indicator that D-PHY is under RxLpdt mode.\n" - "+ *\t- RxValid and RxLpdt specifies signal from D-PHY.\n" - "+ * @e_lane_swap: swaps Dp/Dn channel of Clock lane or Data lane.\n" - "+ *\tif this bit is set, Dp and Dn channel would be swapped each other.\n" - "+ */\n" - "+struct dsim_config {\n" - "+\tunsigned char auto_flush;\n" - "+\tunsigned char eot_disable;\n" - "+\n" - "+\tunsigned char auto_vertical_cnt;\n" - "+\tunsigned char hse;\n" - "+\tunsigned char hfp;\n" - "+\tunsigned char hbp;\n" - "+\tunsigned char hsa;\n" - "+\n" - "+\tenum dsim_no_of_data_lane e_no_data_lane;\n" - "+\tenum dsim_byte_clk_src e_byte_clk;\n" - "+\n" - "+\t/*\n" - "+\t * ===========================================\n" - "+\t * | P | M | S | MHz |\n" - "+\t * -------------------------------------------\n" - "+\t * | 3 | 100 | 3 | 100 |\n" - "+\t * | 3 | 100 | 2 | 200 |\n" - "+\t * | 3 | 63 | 1 | 252 |\n" - "+\t * | 4 | 100 | 1 | 300 |\n" - "+\t * | 4 | 110 | 1 | 330 |\n" - "+\t * | 12 | 350 | 1 | 350 |\n" - "+\t * | 3 | 100 | 1 | 400 |\n" - "+\t * | 4 | 150 | 1 | 450 |\n" - "+\t * | 3 | 118 | 1 | 472 |\n" - "+\t * | 12 | 250 | 0 | 500 |\n" - "+\t * | 4 | 100 | 0 | 600 |\n" - "+\t * | 3 | 81 | 0 | 648 |\n" - "+\t * | 3 | 88 | 0 | 704 |\n" - "+\t * | 3 | 90 | 0 | 720 |\n" - "+\t * | 3 | 100 | 0 | 800 |\n" - "+\t * | 12 | 425 | 0 | 850 |\n" - "+\t * | 4 | 150 | 0 | 900 |\n" - "+\t * | 12 | 475 | 0 | 950 |\n" - "+\t * | 6 | 250 | 0 | 1000 |\n" - "+\t * -------------------------------------------\n" - "+\t */\n" - "+\tunsigned char p;\n" - "+\tunsigned short m;\n" - "+\tunsigned char s;\n" - "+\n" - "+\tunsigned int pll_stable_time;\n" - "+\tunsigned long esc_clk;\n" - "+\n" - "+\tunsigned short stop_holding_cnt;\n" - "+\tunsigned char bta_timeout;\n" - "+\tunsigned short rx_timeout;\n" - "+\tenum dsim_video_mode_type e_lane_swap;\n" - "+};\n" - "+\n" - "+/**\n" - "+ * struct dsim_lcd_config - interface for configuring mipi-dsi based lcd panel.\n" - "+ *\n" - "+ * @e_interface: specifies interface to be used.(CPU or RGB interface)\n" - "+ * @parameter[0]: specifies virtual channel number\n" - "+ *\tthat main or sub diaplsy uses.\n" - "+ * @parameter[1]: specifies pixel stream format for main or sub display.\n" - "+ * @parameter[2]: selects Burst mode in Video mode.\n" - "+ *\tin Non-burst mode, RGB data area is filled with RGB data and NULL\n" - "+ *\tpackets, according to input bandwidth of RGB interface.\n" - "+ *\tIn Burst mode, RGB data area is filled with RGB data only.\n" - "+ * @lcd_panel_info: pointer for lcd panel specific structure.\n" - "+ *\tthis structure specifies width, height, timing and polarity and so on.\n" - "+ * @mipi_ddi_pd: pointer for lcd panel platform data.\n" - "+ */\n" - "+struct dsim_lcd_config {\n" - "+\tenum dsim_interface_type e_interface;\n" - "+\tunsigned int parameter[3];\n" - "+\n" - "+\tvoid *lcd_panel_info;\n" - "+\tvoid *mipi_ddi_pd;\n" - "+};\n" - "+\n" - "+struct dsim_global;\n" - "+struct fb_info;\n" - "+\n" - "+/**\n" - "+ * struct s5p_platform_dsim - interface to platform data for mipi-dsi driver.\n" - "+ *\n" - "+ * @clk_name: specifies clock name for mipi-dsi.\n" - "+ * @lcd_panel_name: specifies lcd panel name registered to mipi-dsi driver.\n" - "+ *\tlcd panel driver searched would be actived.\n" - "+ * @platfrom_rev: specifies platform revision number.\n" - "+ *\trevision number should become 1.\n" - "+ * @dsim_config: pointer of structure for configuring mipi-dsi controller.\n" - "+ * @dsim_lcd_info: pointer to structure for configuring\n" - "+ *\tmipi-dsi based lcd panel.\n" - "+ * @mipi_power: callback pointer for enabling or disabling mipi power.\n" - "+ * @part_reset: callback pointer for reseting mipi phy.\n" - "+ * @init_d_phy: callback pointer for enabing d_phy of dsi master.\n" - "+ * @get_fb_frame_done: callback pointer for getting frame done status of the\n" - "+ *\tdisplay controller(FIMD).\n" - "+ * @trigger: callback pointer for triggering display controller(FIMD)\n" - "+ *\tin case of CPU mode.\n" - "+ * @delay_for_stabilization: specifies stable time.\n" - "+ *\tthis delay needs when writing data on SFR\n" - "+ *\tafter mipi mode became LP mode.\n" - "+ */\n" - "+struct s5p_platform_dsim {\n" - "+\tchar\t*clk_name;\n" - "+\tchar\tlcd_panel_name[64];\n" - "+\tunsigned int platform_rev;\n" - "+\n" - "+\tstruct dsim_config *dsim_info;\n" - "+\tstruct dsim_lcd_config *dsim_lcd_info;\n" - "+\n" - "+\tunsigned int delay_for_stabilization;\n" - "+\n" - "+\tint (*mipi_power) (struct dsim_global *dsim, void *p_mipi_1_1v,\n" - "+\t\tvoid *p_mipi_1_8v, int enable);\n" - "+\tint (*part_reset) (struct dsim_global *dsim);\n" - "+\tint (*init_d_phy) (struct dsim_global *dsim);\n" - "+\tint (*get_fb_frame_done) (struct fb_info *info);\n" - "+\tvoid (*trigger) (struct fb_info *info);\n" - "+};\n" - "+\n" - "+/**\n" - "+ * struct dsim_global - global interface for mipi-dsi driver.\n" - "+ *\n" - "+ * @dev: driver model representation of the device.\n" - "+ * @clock: pointer to MIPI-DSI clock of clock framework.\n" - "+ * @irq: interrupt number to MIPI-DSI controller.\n" - "+ * @reg_base: base address to memory mapped SRF of MIPI-DSI controller.\n" - "+ *\t(virtual address)\n" - "+ * @r_mipi_1_1v: pointer to regulator for MIPI 1.1v power.\n" - "+ * @r_mipi_1_8v: pointer to regulator for MIPI 1.8v power.\n" - "+ * @pd: pointer to MIPI-DSI driver platform data.\n" - "+ * @dsim_lcd_info: pointer to structure for configuring\n" - "+ *\tmipi-dsi based lcd panel.\n" - "+ * @lcd_panel_info: pointer for lcd panel specific structure.\n" - "+ *\tthis structure specifies width, height, timing and polarity and so on.\n" - "+ * @mipi_ddi_pd: pointer for lcd panel platform data.\n" - "+ * @mipi_drv: pointer to driver structure for mipi-dsi based lcd panel.\n" - "+ * @s3cfb_notif: kernel notifier structure to be registered\n" - "+ *\tby device specific framebuffer driver.\n" - "+ *\tthis notifier could be used by fb_blank of device specifiec\n" - "+ *\tframebuffer driver.\n" - "+ * @state: specifies status of MIPI-DSI controller.\n" - "+ *\tthe status could be RESET, INIT, STOP, HSCLKEN and ULPS.\n" - "+ * @data_lane: specifiec enabled data lane number.\n" - "+ *\tthis variable would be set by driver according to e_no_data_lane\n" - "+ *\tautomatically.\n" - "+ * @e_clk_src: select byte clock source.\n" - "+ *\tthis variable would be set by driver according to e_byte_clock\n" - "+ *\tautomatically.\n" - "+ * @hs_clk: HS clock rate.\n" - "+ *\tthis variable would be set by driver automatically.\n" - "+ * @byte_clk: Byte clock rate.\n" - "+ *\tthis variable would be set by driver automatically.\n" - "+ * @escape_clk: ESCAPE clock rate.\n" - "+ *\tthis variable would be set by driver automatically.\n" - "+ * @freq_band: indicates Bitclk frequency band for D-PHY global timing.\n" - "+ *\tSerial Clock(=ByteClk X 8)\t\tFreqBand[3:0]\n" - "+ *\t\t~ 99.99 MHz\t\t\t\t0000\n" - "+ *\t\t100 ~ 119.99 MHz\t\t\t0001\n" - "+ *\t\t120 ~ 159.99 MHz\t\t\t0010\n" - "+ *\t\t160 ~ 199.99 MHz\t\t\t0011\n" - "+ *\t\t200 ~ 239.99 MHz\t\t\t0100\n" - "+ *\t\t140 ~ 319.99 MHz\t\t\t0101\n" - "+ *\t\t320 ~ 389.99 MHz\t\t\t0110\n" - "+ *\t\t390 ~ 449.99 MHz\t\t\t0111\n" - "+ *\t\t450 ~ 509.99 MHz\t\t\t1000\n" - "+ *\t\t510 ~ 559.99 MHz\t\t\t1001\n" - "+ *\t\t560 ~ 639.99 MHz\t\t\t1010\n" - "+ *\t\t640 ~ 689.99 MHz\t\t\t1011\n" - "+ *\t\t690 ~ 769.99 MHz\t\t\t1100\n" - "+ *\t\t770 ~ 869.99 MHz\t\t\t1101\n" - "+ *\t\t870 ~ 949.99 MHz\t\t\t1110\n" - "+ *\t\t950 ~ 1000 MHz\t\t\t\t1111\n" - "+ *\tthis variable would be calculated by driver automatically.\n" - "+ *\n" - "+ * @header_fifo_index: specifies header fifo index.\n" - "+ *\tthis variable is not used yet.\n" - "+ */\n" - "+struct dsim_global {\n" - "+\tstruct device *dev;\n" - "+\tstruct clk *clock;\n" - "+\tunsigned int irq;\n" - "+\tunsigned int reg_base;\n" - "+\n" - "+\tstruct regulator *r_mipi_1_1v;\n" - "+\tstruct regulator *r_mipi_1_8v;\n" - "+\n" - "+\tstruct s5p_platform_dsim *pd;\n" - "+\tstruct dsim_config *dsim_info;\n" - "+\tstruct dsim_lcd_config *dsim_lcd_info;\n" - "+\tstruct fb_videomode *lcd_panel_info;\n" - "+\tstruct mipi_ddi_platform_data *mipi_ddi_pd;\n" - "+\tstruct mipi_lcd_driver *mipi_drv;\n" - "+\tstruct notifier_block s3cfb_notif;\n" - "+\n" - "+\tunsigned char state;\n" - "+\tunsigned int data_lane;\n" - "+\tenum dsim_byte_clk_src e_clk_src;\n" - "+\tunsigned long hs_clk;\n" - "+\tunsigned long byte_clk;\n" - "+\tunsigned long escape_clk;\n" - "+\tunsigned char freq_band;\n" - "+\n" - "+\tchar header_fifo_index[DSIM_HEADER_FIFO_SZ];\n" - "+};\n" - "+\n" - "+/*\n" - "+ * driver structure for mipi-dsi based lcd panel.\n" - "+ *\n" - "+ * this structure should be registered by lcd panel driver.\n" - "+ * mipi-dsi driver seeks lcd panel registered through name field\n" - "+ * and calls these callback functions in appropriate time.\n" - "+ */\n" - "+struct mipi_lcd_driver {\n" - "+\ts8\tname[64];\n" - "+\n" - "+\ts32\t(*init)(struct device *dev);\n" - "+\tvoid\t(*display_on)(struct device *dev);\n" - "+\ts32\t(*set_link)(struct mipi_ddi_platform_data *pd);\n" - "+\ts32\t(*probe)(struct device *dev);\n" - "+\ts32\t(*remove)(struct device *dev);\n" - "+\tvoid\t(*shutdown)(struct device *dev);\n" - "+\ts32\t(*suspend)(struct device *dev, pm_message_t mesg);\n" - "+\ts32\t(*resume)(struct device *dev);\n" - "+};\n" - "+\n" - "+/*\n" - "+ * register mipi_lcd_driver object defined by lcd panel driver\n" - "+ * to mipi-dsi driver.\n" - "+ */\n" - "+extern int s5p_dsim_register_lcd_driver(struct mipi_lcd_driver *lcd_drv);\n" - "+\n" - "+/* reset MIPI PHY through MIPI PHY CONTROL REGISTER. */\n" - "+extern int s5p_dsim_part_reset(struct dsim_global *dsim);\n" - "+/* enable MIPI D-PHY and DSI Master block. */\n" - "+extern int s5p_dsim_init_d_phy(struct dsim_global *dsim);\n" - "+\n" - "+/* enable regulators to MIPI-DSI power. */\n" - "+extern int s5p_dsim_mipi_power(struct dsim_global *dsim, void *p_mipi_1_1v,\n" - "+\tvoid *p_mipi_1_8v, int enable);\n" - "+\n" - "+#endif /* _DSIM_H */\n" - "diff --git a/arch/arm/plat-samsung/include/plat/mipi_ddi.h b/arch/arm/plat-samsung/include/plat/mipi_ddi.h\n" - "new file mode 100644\n" - "index 0000000..57ed613\n" - "--- /dev/null\n" - "+++ b/arch/arm/plat-samsung/include/plat/mipi_ddi.h\n" - "@@ -0,0 +1,98 @@\n" - "+/* linux/arm/arch/mach-s5pc110/include/mach/mipi_ddi.h\n" - "+ *\n" - "+ * definitions for DDI based MIPI-DSI.\n" - "+ *\n" - "+ * Copyright (c) 2009 Samsung Electronics\n" - "+ * InKi Dae <a class=\"moz-txt-link-rfc2396E\" href=\"mailto:inki.dae@samsung.com\"><inki.dae@samsung.com></a>\n" - "+ *\n" - "+ * This program is free software; you can redistribute it and/or modify\n" - "+ * it under the terms of the GNU General Public License version 2 as\n" - "+ * published by the Free Software Foundation.\n" - "+*/\n" - "+\n" - "+#ifndef _MIPI_DDI_H\n" - "+#define _MIPI_DDI_H\n" - "+\n" - "+enum mipi_ddi_interface {\n" - "+\tRGB_IF = 0x4000,\n" - "+\tI80_IF = 0x8000,\n" - "+\tYUV_601 = 0x10000,\n" - "+\tYUV_656 = 0x20000,\n" - "+\tMIPI_VIDEO = 0x1000,\n" - "+\tMIPI_COMMAND = 0x2000,\n" - "+};\n" - "+\n" - "+enum mipi_ddi_panel_select {\n" - "+\tDDI_MAIN_LCD = 0,\n" - "+\tDDI_SUB_LCD = 1,\n" - "+};\n" - "+\n" - "+enum mipi_ddi_model {\n" - "+\tS6DR117 = 0,\n" - "+};\n" - "+\n" - "+enum mipi_ddi_parameter {\n" - "+\t/* DSIM video interface parameter */\n" - "+\tDSI_VIRTUAL_CH_ID = 0,\n" - "+\tDSI_FORMAT = 1,\n" - "+\tDSI_VIDEO_MODE_SEL = 2,\n" - "+};\n" - "+\n" - "+struct lcd_device;\n" - "+struct fb_info;\n" - "+\n" - "+struct mipi_ddi_platform_data {\n" - "+\tvoid *dsim_data;\n" - "+\t/*\n" - "+\t * it is used for command mode lcd panel and\n" - "+\t * when all contents of framebuffer in panel module are transfered\n" - "+\t * to lcd panel it occurs te signal.\n" - "+\t *\n" - "+\t * note:\n" - "+\t * - in case of command mode(cpu mode), it should be triggered only\n" - "+\t * when TE signal of lcd panel and frame done interrupt of display\n" - "+\t * controller or mipi controller occurs.\n" - "+\t */\n" - "+\tunsigned int te_irq;\n" - "+\n" - "+\t/*\n" - "+\t * it is used for PM stable time at te interrupt handler and\n" - "+\t * could be used according to lcd panel characteristic or not.\n" - "+\t */\n" - "+\tunsigned int resume_complete;\n" - "+\n" - "+\tint (*lcd_reset) (struct lcd_device *ld);\n" - "+\tint (*lcd_power_on) (struct lcd_device *ld, int enable);\n" - "+\tint (*backlight_on) (int enable);\n" - "+\n" - "+\t/* transfer command to lcd panel at LP mode. */\n" - "+\tint (*cmd_write) (void *dsim_data, unsigned int data_id,\n" - "+\t\tunsigned int data0, unsigned int data1);\n" - "+\tint (*cmd_read) (void *dsim_data, unsigned int data_id,\n" - "+\t\tunsigned int data0, unsigned int data1);\n" - "+\t/*\n" - "+\t * get the status that all screen data have been transferred\n" - "+\t * to mipi-dsi.\n" - "+\t */\n" - "+\tint (*get_dsim_frame_done) (void *dsim_data);\n" - "+\tint (*clear_dsim_frame_done) (void *dsim_data);\n" - "+\n" - "+\t/*\n" - "+\t * changes mipi transfer mode to LP or HS mode.\n" - "+\t *\n" - "+\t * LP mode needs when some commands like gamma values transfers\n" - "+\t * to lcd panel.\n" - "+\t */\n" - "+\tint (*change_dsim_transfer_mode) (int mode);\n" - "+\n" - "+\t/* get frame done status of display controller. */\n" - "+\tint (*get_fb_frame_done) (struct fb_info *info);\n" - "+\t/* trigger display controller in case of cpu mode. */\n" - "+\tvoid (*trigger) (struct fb_info *info);\n" - "+\n" - "+\tunsigned int reset_delay;\n" - "+\tunsigned int power_on_delay;\n" - "+\tunsigned int power_off_delay;\n" - "+};\n" - "+\n" - "+#endif /* _MIPI_DDI_H */\n" - "diff --git a/arch/arm/plat-samsung/include/plat/regs-dsim.h b/arch/arm/plat-samsung/include/plat/regs-dsim.h\n" - "new file mode 100644\n" - "index 0000000..dc83089\n" - "--- /dev/null\n" - "+++ b/arch/arm/plat-samsung/include/plat/regs-dsim.h\n" - "@@ -0,0 +1,281 @@\n" - "+/* linux/arch/arm/plat-s5pc11x/include/plat/regs-dsim.h\n" - "+ *\n" - "+ * Register definition file for Samsung MIPI-DSIM driver\n" - "+ *\n" - "+ * InKi Dae <a class=\"moz-txt-link-rfc2396E\" href=\"mailto:inki.dae@samsung.com\"><inki.dae@samsung.com></a>, Copyright (c) 2009 Samsung Electronics\n" - "+ *\n" - "+ * This program is free software; you can redistribute it and/or modify\n" - "+ * it under the terms of the GNU General Public License version 2 as\n" - "+ * published by the Free Software Foundation.\n" - "+*/\n" - "+\n" - "+#ifndef _REGS_DSIM_H\n" - "+#define _REGS_DSIM_H\n" - "+\n" - "+#define S5P_DSIM_STATUS\t\t(0x0)\t/* Status register */\n" - "+#define S5P_DSIM_SWRST\t\t(0x4)\t/* Software reset register */\n" - "+#define S5P_DSIM_CLKCTRL\t(0x8)\t/* Clock control register */\n" - "+#define S5P_DSIM_TIMEOUT\t(0xc)\t/* Time out register */\n" - "+#define S5P_DSIM_CONFIG\t\t(0x10)\t/* Configuration register */\n" - "+#define S5P_DSIM_ESCMODE\t(0x14)\t/* Escape mode register */\n" - "+\n" - "+/* Main display image resolution register */\n" - "+#define S5P_DSIM_MDRESOL\t(0x18)\n" - "+#define S5P_DSIM_MVPORCH\t(0x1c)\t/* Main display Vporch register */\n" - "+#define S5P_DSIM_MHPORCH\t(0x20)\t/* Main display Hporch register */\n" - "+#define S5P_DSIM_MSYNC\t\t(0x24)\t/* Main display sync area register */\n" - "+\n" - "+/* Sub display image resolution register */\n" - "+#define S5P_DSIM_SDRESOL\t(0x28)\n" - "+#define S5P_DSIM_INTSRC\t\t(0x2c)\t/* Interrupt source register */\n" - "+#define S5P_DSIM_INTMSK\t\t(0x30)\t/* Interrupt mask register */\n" - "+#define S5P_DSIM_PKTHDR\t\t(0x34)\t/* Packet Header FIFO register */\n" - "+#define S5P_DSIM_PAYLOAD\t(0x38)\t/* Payload FIFO register */\n" - "+#define S5P_DSIM_RXFIFO\t\t(0x3c)\t/* Read FIFO register */\n" - "+#define S5P_DSIM_FIFOTHLD\t(0x40)\t/* FIFO threshold level register */\n" - "+#define S5P_DSIM_FIFOCTRL\t(0x44)\t/* FIFO status and control register */\n" - "+\n" - "+/* FIFO memory AC characteristic register */\n" - "+#define S5P_DSIM_MEMACCHR\t(0x48)\n" - "+#define S5P_DSIM_PLLCTRL\t(0x4c)\t/* PLL control register */\n" - "+#define S5P_DSIM_PLLTMR\t\t(0x50)\t/* PLL timer register */\n" - "+#define S5P_DSIM_PHYACCHR\t(0x54)\t/* D-PHY AC characteristic register */\n" - "+#define S5P_DSIM_PHYACCHR1\t(0x58)\t/* D-PHY AC characteristic register1 */\n" - "+\n" - "+/* DSIM_SWRST */\n" - "+#define DSIM_FUNCRST\t\t(1 << 16)\n" - "+#define DSIM_SWRST\t\t(1 << 0)\n" - "+\n" - "+/* S5P_DSIM_TIMEOUT */\n" - "+#define DSIM_LPDR_TOUT_SHIFT\t(0)\n" - "+#define DSIM_BTA_TOUT_SHIFT\t(16)\n" - "+#define DSIM_LPDR_TOUT(x)\t(((x) & 0xffff) << DSIM_LPDR_TOUT_SHIFT)\n" - "+#define DSIM_BTA_TOUT(x)\t(((x) & 0xff) << DSIM_BTA_TOUT_SHIFT)\n" - "+\n" - "+/* S5P_DSIM_CLKCTRL */\n" - "+#define DSIM_ESC_PRESCALER_SHIFT\t(0)\n" - "+#define DSIM_LANE_ESC_CLKEN_SHIFT\t(19)\n" - "+#define DSIM_BYTE_CLKEN_SHIFT\t\t(24)\n" - "+#define DSIM_BYTE_CLK_SRC_SHIFT\t\t(25)\n" - "+#define DSIM_PLL_BYPASS_SHIFT\t\t(27)\n" - "+#define DSIM_ESC_CLKEN_SHIFT\t\t(28)\n" - "+#define DSIM_TX_REQUEST_HSCLK_SHIFT\t(31)\n" - "+#define DSIM_ESC_PRESCALER(x)\t\t(((x) & 0xffff) << \\\n" - "+\t\t\t\t\t\tDSIM_ESC_PRESCALER_SHIFT)\n" - "+#define DSIM_LANE_ESC_CLKEN(x)\t\t(((x) & 0x1f) << \\\n" - "+\t\t\t\t\t\tDSIM_LANE_ESC_CLKEN_SHIFT)\n" - "+#define DSIM_BYTE_CLK_ENABLE\t\t(1 << DSIM_BYTE_CLKEN_SHIFT)\n" - "+#define DSIM_BYTE_CLK_DISABLE\t\t(0 << DSIM_BYTE_CLKEN_SHIFT)\n" - "+#define DSIM_BYTE_CLKSRC(x)\t\t(((x) & 0x3) << DSIM_BYTE_CLK_SRC_SHIFT)\n" - "+#define DSIM_PLL_BYPASS_PLL\t\t(0 << DSIM_PLL_BYPASS_SHIFT)\n" - "+#define DSIM_PLL_BYPASS_EXTERNAL\t(1 << DSIM_PLL_BYPASS_SHIFT)\n" - "+#define DSIM_ESC_CLKEN_ENABLE\t\t(1 << DSIM_ESC_CLKEN_SHIFT)\n" - "+#define DSIM_ESC_CLKEN_DISABLE\t\t(0 << DSIM_ESC_CLKEN_SHIFT)\n" - "+\n" - "+/* S5P_DSIM_CONFIG */\n" - "+#define DSIM_LANE_EN_SHIFT\t\t(0)\n" - "+#define DSIM_NUM_OF_DATALANE_SHIFT\t(5)\n" - "+#define DSIM_SUB_PIX_FORMAT_SHIFT\t(8)\n" - "+#define DSIM_MAIN_PIX_FORMAT_SHIFT\t(12)\n" - "+#define DSIM_SUB_VC_SHIFT\t\t(16)\n" - "+#define DSIM_MAIN_VC_SHIFT\t\t(18)\n" - "+#define DSIM_HSA_MODE_SHIFT\t\t(20)\n" - "+#define DSIM_HBP_MODE_SHIFT\t\t(21)\n" - "+#define DSIM_HFP_MODE_SHIFT\t\t(22)\n" - "+#define DSIM_HSE_MODE_SHIFT\t\t(23)\n" - "+#define DSIM_AUTO_MODE_SHIFT\t\t(24)\n" - "+#define DSIM_VIDEO_MODE_SHIFT\t\t(25)\n" - "+#define DSIM_BURST_MODE_SHIFT\t\t(26)\n" - "+#define DSIM_SYNC_INFORM_SHIFT\t\t(27)\n" - "+#define DSIM_EOT_R03_SHIFT\t\t(28)\n" - "+#define DSIM_LANE_ENx(x)\t\t((1) << x)\n" - "+\n" - "+/* in case of Gemunus, it should be 0x1. */\n" - "+#define DSIM_NUM_OF_DATA_LANE(x)\t((x) << 5)\n" - "+#define DSIM_SUB_PIX_FORMAT_3BPP\t(0 << 8)\t/* command mode only */\n" - "+#define DSIM_SUB_PIX_FORMAT_8BPP\t(1 << 8)\t/* command mode only */\n" - "+#define DSIM_SUB_PIX_FORMAT_12BPP\t(2 << 8)\t/* command mode only */\n" - "+#define DSIM_SUB_PIX_FORMAT_16BPP\t(3 << 8)\t/* command mode only */\n" - "+#define DSIM_SUB_PIX_FORMAT_16BPP_RGB\t(4 << 8)\t/* video mode only */\n" - "+#define DSIM_SUB_PIX_FORMAT_18BPP_PRGB\t(5 << 8)\t/* video mode only */\n" - "+#define DSIM_SUB_PIX_FORMAT_18BPP_LRGB\t(6 << 8)\t/* common */\n" - "+#define DSIM_SUB_PIX_FORMAT_24BPP_RGB\t(7 << 8)\t/* common */\n" - "+#define DSIM_MAIN_PIX_FORMAT_3BPP\t(0 << 12)\t/* command mode only */\n" - "+#define DSIM_MAIN_PIX_FORMAT_8BPP\t(1 << 12)\t/* command mode only */\n" - "+#define DSIM_MAIN_PIX_FORMAT_12BPP\t(2 << 12)\t/* command mode only */\n" - "+#define DSIM_MAIN_PIX_FORMAT_16BPP\t(3 << 12)\t/* command mode only */\n" - "+#define DSIM_MAIN_PIX_FORMAT_16BPP_RGB\t(4 << 12)\t/* video mode only */\n" - "+#define DSIM_MAIN_PIX_FORMAT_18BPP_PRGB\t(5 << 12)\t/* video mode only */\n" - "+#define DSIM_MAIN_PIX_FORMAT_18BPP_LRGB\t(6 << 12)\t/* common */\n" - "+#define DSIM_MAIN_PIX_FORMAT_24BPP_RGB\t(7 << 12)\t/* common */\n" - "+\n" - "+/* Virtual channel number for sub display */\n" - "+#define DSIM_SUB_VC(x)\t\t\t(((x) & 0x3) << 16)\n" - "+/* Virtual channel number for main display */\n" - "+#define DSIM_MAIN_VC(x)\t\t\t(((x) & 0x3) << 18)\n" - "+#define DSIM_HSA_MODE_ENABLE\t\t(1 << 20)\n" - "+#define DSIM_HSA_MODE_DISABLE\t\t(0 << 20)\n" - "+#define DSIM_HBP_MODE_ENABLE\t\t(1 << 21)\n" - "+#define DSIM_HBP_MODE_DISABLE\t\t(0 << 21)\n" - "+#define DSIM_HFP_MODE_ENABLE\t\t(1 << 22)\n" - "+#define DSIM_HFP_MODE_DISABLE\t\t(0 << 22)\n" - "+#define DSIM_HSE_MODE_ENABLE\t\t(1 << 23)\n" - "+#define DSIM_HSE_MODE_DISABLE\t\t(0 << 23)\n" - "+#define DSIM_AUTO_MODE\t\t\t(1 << 24)\n" - "+#define DSIM_CONFIGURATION_MODE\t\t(0 << 24)\n" - "+#define DSIM_VIDEO_MODE\t\t\t(1 << 25)\n" - "+#define DSIM_COMMAND_MODE\t\t(0 << 25)\n" - "+#define DSIM_BURST_MODE\t\t\t(1 << 26)\n" - "+#define DSIM_NON_BURST_MODE\t\t(0 << 26)\n" - "+#define DSIM_SYNC_INFORM_PULSE\t\t(1 << 27)\n" - "+#define DSIM_SYNC_INFORM_EVENT\t\t(0 << 27)\n" - "+/* enable EoT packet generation for V1.01r11 */\n" - "+#define DSIM_EOT_R03_ENABLE\t\t(0 << 28)\n" - "+/* disable EoT packet generation for V1.01r03 */\n" - "+#define DSIM_EOT_R03_DISABLE\t\t(1 << 28)\n" - "+\n" - "+/* S5P_DSIM_ESCMODE */\n" - "+#define DSIM_STOP_STATE_CNT_SHIFT\t(21)\n" - "+#define DSIM_STOP_STATE_CNT(x)\t\t(((x) & 0x3ff) << \\\n" - "+\t\t\t\t\t\tDSIM_STOP_STATE_CNT_SHIFT)\n" - "+#define DSIM_FORCE_STOP_STATE_SHIFT\t(20)\n" - "+#define DSIM_FORCE_BTA_SHIFT\t\t(16)\n" - "+#define DSIM_CMD_LPDT_HS_MODE\t\t(0 << 7)\n" - "+#define DSIM_CMD_LPDT_LP_MODE\t\t(1 << 7)\n" - "+#define DSIM_TX_LPDT_HS_MODE\t\t(0 << 6)\n" - "+#define DSIM_TX_LPDT_LP_MODE\t\t(1 << 6)\n" - "+#define DSIM_TX_TRIGGER_RST_SHIFT\t(4)\n" - "+#define DSIM_TX_UIPS_DAT_SHIFT\t\t(3)\n" - "+#define DSIM_TX_UIPS_EXIT_SHIFT\t\t(2)\n" - "+#define DSIM_TX_UIPS_CLK_SHIFT\t\t(1)\n" - "+#define DSIM_TX_UIPS_CLK_EXIT_SHIFT\t(0)\n" - "+\n" - "+/* S5P_DSIM_MDRESOL */\n" - "+#define DSIM_MAIN_STAND_BY\t\t(1 << 31)\n" - "+#define DSIM_MAIN_NOT_READY\t\t(0 << 31)\n" - "+#define DSIM_MAIN_VRESOL(x)\t\t(((x) & 0x7ff) << 16)\n" - "+#define DSIM_MAIN_HRESOL(x)\t\t(((x) & 0X7ff) << 0)\n" - "+\n" - "+/* S5P_DSIM_MVPORCH */\n" - "+#define DSIM_CMD_ALLOW_SHIFT\t\t(28)\n" - "+#define DSIM_STABLE_VFP_SHIFT\t\t(16)\n" - "+#define DSIM_MAIN_VBP_SHIFT\t\t(0)\n" - "+#define DSIM_CMD_ALLOW_MASK\t\t(0xf << DSIM_CMD_ALLOW_SHIFT)\n" - "+#define DSIM_STABLE_VFP_MASK\t\t(0x7ff << DSIM_STABLE_VFP_SHIFT)\n" - "+#define DSIM_MAIN_VBP_MASK\t\t(0x7ff << DSIM_MAIN_VBP_SHIFT)\n" - "+#define DSIM_CMD_ALLOW(x)\t\t(((x) & 0xf) << DSIM_CMD_ALLOW_SHIFT)\n" - "+#define DSIM_STABLE_VFP(x)\t\t(((x) & 0x7ff) << DSIM_STABLE_VFP_SHIFT)\n" - "+#define DSIM_MAIN_VBP(x)\t\t(((x) & 0x7ff) << DSIM_MAIN_VBP_SHIFT)\n" - "+\n" - "+/* S5P_DSIM_MHPORCH */\n" - "+#define DSIM_MAIN_HFP_SHIFT\t\t(16)\n" - "+#define DSIM_MAIN_HBP_SHIFT\t\t(0)\n" - "+#define DSIM_MAIN_HFP_MASK\t\t((0xffff) << DSIM_MAIN_HFP_SHIFT)\n" - "+#define DSIM_MAIN_HBP_MASK\t\t((0xffff) << DSIM_MAIN_HBP_SHIFT)\n" - "+#define DSIM_MAIN_HFP(x)\t\t(((x) & 0xffff) << DSIM_MAIN_HFP_SHIFT)\n" - "+#define DSIM_MAIN_HBP(x)\t\t(((x) & 0xffff) << DSIM_MAIN_HBP_SHIFT)\n" - "+\n" - "+/* S5P_DSIM_MSYNC */\n" - "+#define DSIM_MAIN_VSA_SHIFT\t\t(22)\n" - "+#define DSIM_MAIN_HSA_SHIFT\t\t(0)\n" - "+#define DSIM_MAIN_VSA_MASK\t\t((0x3ff) << DSIM_MAIN_VSA_SHIFT)\n" - "+#define DSIM_MAIN_HSA_MASK\t\t((0xffff) << DSIM_MAIN_HSA_SHIFT)\n" - "+#define DSIM_MAIN_VSA(x)\t\t(((x) & 0x3ff) << DSIM_MAIN_VSA_SHIFT)\n" - "+#define DSIM_MAIN_HSA(x)\t\t(((x) & 0xffff) << DSIM_MAIN_HSA_SHIFT)\n" - "+\n" - "+/* S5P_DSIM_SDRESOL */\n" - "+#define DSIM_SUB_STANDY_SHIFT\t\t(31)\n" - "+#define DSIM_SUB_VRESOL_SHIFT\t\t(16)\n" - "+#define DSIM_SUB_HRESOL_SHIFT\t\t(0)\n" - "+#define DSIM_SUB_STANDY_MASK\t\t((0x1) << DSIM_SUB_STANDY_SHIFT)\n" - "+#define DSIM_SUB_VRESOL_MASK\t\t((0x7ff) << DSIM_SUB_VRESOL_SHIFT)\n" - "+#define DSIM_SUB_HRESOL_MASK\t\t((0x7ff) << DSIM_SUB_HRESOL_SHIFT)\n" - "+#define DSIM_SUB_STANDY\t\t\t(1 << DSIM_SUB_STANDY_SHIFT)\n" - "+#define DSIM_SUB_NOT_READY\t\t(0 << DSIM_SUB_STANDY_SHIFT)\n" - "+#define DSIM_SUB_VRESOL(x)\t\t(((x) & 0x7ff) << DSIM_SUB_VRESOL_SHIFT)\n" - "+#define DSIM_SUB_HRESOL(x)\t\t(((x) & 0x7ff) << DSIM_SUB_HRESOL_SHIFT)\n" - "+\n" - "+/* S5P_DSIM_INTSRC */\n" - "+#define INTSRC_ERR_CONTENT_LP1\t\t(1 << 0)\n" - "+#define INTSRC_ERR_CONTENT_LP0\t\t(1 << 1)\n" - "+#define INTSRC_ERR_CONTROL0\t\t(1 << 2)\n" - "+#define INTSRC_ERR_CONTROL1\t\t(1 << 3)\n" - "+#define INTSRC_ERR_CONTROL2\t\t(1 << 4)\n" - "+#define INTSRC_ERR_CONTROL3\t\t(1 << 5)\n" - "+#define INTSRC_ERR_SYNC0\t\t(1 << 6)\n" - "+#define INTSRC_ERR_SYNC1\t\t(1 << 7)\n" - "+#define INTSRC_ERR_SYNC2\t\t(1 << 8)\n" - "+#define INTSRC_ERR_SYNC3\t\t(1 << 9)\n" - "+#define INTSRC_ERR_ESC0\t\t\t(1 << 10)\n" - "+#define INTSRC_ERR_ESC1\t\t\t(1 << 11)\n" - "+#define INTSRC_ERR_ESC2\t\t\t(1 << 12)\n" - "+#define INTSRC_ERR_ESC3\t\t\t(1 << 13)\n" - "+#define INTSRC_ERR_RX_CRC\t\t(1 << 14)\n" - "+#define INTSRC_ERR_RX_ECC\t\t(1 << 15)\n" - "+#define INTSRC_RX_ACK\t\t\t(1 << 16)\n" - "+#define INTSRC_RX_TE\t\t\t(1 << 17)\n" - "+#define INTSRC_RX_DAT_DONE\t\t(1 << 18)\n" - "+#define INTSRC_TA_TOUT\t\t\t(1 << 20)\n" - "+#define INTSRC_LPDR_TOUT\t\t(1 << 21)\n" - "+#define INTSRC_FRAME_DONE\t\t(1 << 24)\n" - "+#define INTSRC_BUS_TURN_OVER\t\t(1 << 25)\n" - "+#define INTSRC_SYNC_OVERRIDE\t\t(1 << 28)\n" - "+#define INTSRC_SFR_FIFO_EMPTY\t\t(1 << 29)\n" - "+#define INTSRC_SW_RST_RELEASE\t\t(1 << 30)\n" - "+#define INTSRC_PLL_STABLE\t\t(1 << 31)\n" - "+\n" - "+/* S5P_DSIM_INTMSK */\n" - "+#define INTMSK_ERR_CONTENT_LP1\t\t(1 << 0)\n" - "+#define INTMSK_ERR_CONTENT_LP0\t\t(1 << 1)\n" - "+#define INTMSK_ERR_CONTROL0\t\t(1 << 2)\n" - "+#define INTMSK_ERR_CONTROL1\t\t(1 << 3)\n" - "+#define INTMSK_ERR_CONTROL2\t\t(1 << 4)\n" - "+#define INTMSK_ERR_CONTROL3\t\t(1 << 5)\n" - "+#define INTMSK_ERR_SYNC0\t\t(1 << 6)\n" - "+#define INTMSK_ERR_SYNC1\t\t(1 << 7)\n" - "+#define INTMSK_ERR_SYNC2\t\t(1 << 8)\n" - "+#define INTMSK_ERR_SYNC3\t\t(1 << 9)\n" - "+#define INTMSK_ERR_ESC0\t\t\t(1 << 10)\n" - "+#define INTMSK_ERR_ESC1\t\t\t(1 << 11)\n" - "+#define INTMSK_ERR_ESC2\t\t\t(1 << 12)\n" - "+#define INTMSK_ERR_ESC3\t\t\t(1 << 13)\n" - "+#define INTMSK_ERR_RX_CRC\t\t(1 << 14)\n" - "+#define INTMSK_ERR_RX_ECC\t\t(1 << 15)\n" - "+#define INTMSK_RX_ACK\t\t\t(1 << 16)\n" - "+#define INTMSK_RX_TE\t\t\t(1 << 17)\n" - "+#define INTMSK_RX_DAT_DONE\t\t(1 << 18)\n" - "+#define INTMSK_TA_TOUT\t\t\t(1 << 20)\n" - "+#define INTMSK_LPDR_TOUT\t\t(1 << 21)\n" - "+#define INTMSK_FRAME_DONE\t\t(1 << 24)\n" - "+#define INTMSK_BUS_TURN_OVER\t\t(1 << 25)\n" - "+#define INTMSK_SFR_FIFO_EMPTY\t\t(1 << 29)\n" - "+#define INTMSK_SW_RST_RELEASE\t\t(1 << 30)\n" - "+#define INTMSK_PLL_STABLE\t\t(1 << 31)\n" - "+\n" - "+/* S5P_DSIM_PKTHDR */\n" - "+#define DSIM_PACKET_HEADER_DI(x)\t(((x) & 0xff) << 0)\n" - "+/* Word count lower byte for long packet */\n" - "+#define DSIM_PACKET_HEADER_DAT0(x)\t(((x) & 0xff) << 8)\n" - "+/* Word count upper byte for long packet */\n" - "+#define DSIM_PACKET_HEADER_DAT1(x)\t(((x) & 0xff) << 16)\n" - "+\n" - "+/* S5P_DSIM_FIFOCTRL */\n" - "+#define DSIM_RX_FIFO\t\t\t(1 << 4)\n" - "+#define DSIM_TX_SFR_FIFO\t\t(1 << 3)\n" - "+#define DSIM_I80_FIFO\t\t\t(1 << 2)\n" - "+#define DSIM_SUB_DISP_FIFO\t\t(1 << 1)\n" - "+#define DSIM_MAIN_DISP_FIFO\t\t(1 << 0)\n" - "+\n" - "+/* S5P_DSIM_PHYACCHR */\n" - "+#define DSIM_AFC_CTL(x)\t\t\t(((x) & 0x7) << 5)\n" - "+#define DSIM_AFC_ENABLE\t\t\t(1 << 14)\n" - "+#define DSIM_AFC_DISABLE\t\t(0 << 14)\n" - "+\n" - "+/* S5P_DSIM_PLLCTRL */\n" - "+#define DSIM_PMS_SHIFT\t\t\t(1)\n" - "+#define DSIM_PLL_EN_SHIFT\t\t(23)\n" - "+#define DSIM_FREQ_BAND_SHIFT\t\t(24)\n" - "+#define DSIM_PMS(x)\t\t\t(((x) & 0x7ffff) << DSIM_PMS_SHIFT)\n" - "+#define DSIM_FREQ_BAND(x)\t\t(((x) & 0xf) << DSIM_FREQ_BAND_SHIFT)\n" - "+\n" - "+#endif /* _REGS_DSIM_H */\n" - "diff --git a/arch/arm/plat-samsung/setup-dsim.c b/arch/arm/plat-samsung/setup-dsim.c\n" - "new file mode 100644\n" - "index 0000000..833ade2\n" - "--- /dev/null\n" - "+++ b/arch/arm/plat-samsung/setup-dsim.c\n" - "@@ -0,0 +1,161 @@\n" - "+/*\n" - "+ * S5PC110 MIPI-DSIM driver.\n" - "+ *\n" - "+ * Author: InKi Dae <a class=\"moz-txt-link-rfc2396E\" href=\"mailto:inki.dae@samsung.com\"><inki.dae@samsung.com></a>\n" - "+ *\n" - "+ * This program is free software; you can redistribute it and/or\n" - "+ * modify it under the terms of the GNU General Public License as\n" - "+ * published by the Free Software Foundation; either version 2 of\n" - "+ * the License, or (at your option) any later version.\n" - "+ *\n" - "+ * This program is distributed in the hope that it will be useful,\n" - "+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n" - "+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\t See the\n" - "+ * GNU General Public License for more details.\n" - "+ *\n" - "+ * You should have received a copy of the GNU General Public License\n" - "+ * along with this program; if not, write to the Free Software\n" - "+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,\n" - "+ * MA 02111-1307 USA\n" - "+ */\n" - "+#include <linux/kernel.h>\n" - "+#include <linux/string.h>\n" - "+#include <linux/io.h>\n" - "+#include <linux/err.h>\n" - "+#include <linux/platform_device.h>\n" - "+#include <linux/clk.h>\n" - "+#include <linux/regulator/consumer.h>\n" - "+\n" - "+#include <mach/map.h>\n" - "+#include <mach/regs-clock.h>\n" - "+\n" - "+#include <plat/dsim.h>\n" - "+#include <plat/clock.h>\n" - "+#include <plat/regs-dsim.h>\n" - "+\n" - "+static int s5p_dsim_enable_d_phy(struct dsim_global *dsim, unsigned int enable)\n" - "+{\n" - "+\tunsigned int reg;\n" - "+\n" - "+\tif (dsim == NULL) {\n" - "+\t\tprintk(KERN_ERR \"dsim is NULL.\\n\");\n" - "+\t\treturn -EFAULT;\n" - "+\t}\n" - "+\n" - "+\treg = (readl(S5P_MIPI_CONTROL)) & ~(1 << 0);\n" - "+\treg |= (enable << 0);\n" - "+\twritel(reg, S5P_MIPI_CONTROL);\n" - "+\n" - "+\tdev_dbg(dsim->dev, \"%s : %x\\n\", __func__, reg);\n" - "+\n" - "+\treturn 0;\n" - "+}\n" - "+\n" - "+static int s5p_dsim_enable_dsi_master(struct dsim_global *dsim,\n" - "+\tunsigned int enable)\n" - "+{\n" - "+\tunsigned int reg;\n" - "+\n" - "+\tif (dsim == NULL) {\n" - "+\t\tprintk(KERN_ERR \"dsim is NULL.\\n\");\n" - "+\t\treturn -EFAULT;\n" - "+\t}\n" - "+\n" - "+\treg = (readl(S5P_MIPI_CONTROL)) & ~(1 << 2);\n" - "+\treg |= (enable << 2);\n" - "+\twritel(reg, S5P_MIPI_CONTROL);\n" - "+\n" - "+\tdev_dbg(dsim->dev, \"%s : %x\\n\", __func__, reg);\n" - "+\n" - "+\treturn 0;\n" - "+}\n" - "+\n" - "+int s5p_dsim_part_reset(struct dsim_global *dsim)\n" - "+{\n" - "+\tif (dsim == NULL) {\n" - "+\t\tprintk(KERN_ERR \"dsim is NULL.\\n\");\n" - "+\t\treturn -EFAULT;\n" - "+\t}\n" - "+\n" - "+\twritel(S5P_MIPI_M_RESETN, S5P_MIPI_PHY_CON0);\n" - "+\n" - "+\tdev_dbg(dsim->dev, \"%s\\n\", __func__);\n" - "+\n" - "+\treturn 0;\n" - "+}\n" - "+\n" - "+int s5p_dsim_init_d_phy(struct dsim_global *dsim)\n" - "+{\n" - "+\tif (dsim == NULL) {\n" - "+\t\tprintk(KERN_ERR \"dsim is NULL.\\n\");\n" - "+\t\treturn -EFAULT;\n" - "+\t}\n" - "+\n" - "+\t/* enable D-PHY */\n" - "+\ts5p_dsim_enable_d_phy(dsim, 1);\n" - "+\n" - "+\t/* enable DSI master block */\n" - "+\ts5p_dsim_enable_dsi_master(dsim, 1);\n" - "+\n" - "+\tdev_dbg(dsim->dev, \"%s\\n\", __func__);\n" - "+\n" - "+\treturn 0;\n" - "+}\n" - "+\n" - "+int s5p_dsim_mipi_power(struct dsim_global *dsim, void *p_mipi_1_1v,\n" - "+\tvoid *p_mipi_1_8v, int enable)\n" - "+{\n" - "+\tstruct regulator *r_mipi_1_1v = NULL, *r_mipi_1_8v = NULL;\n" - "+\tint ret = -1;\n" - "+\n" - "+\tr_mipi_1_1v = (struct regulator *) p_mipi_1_1v;\n" - "+\tr_mipi_1_8v = (struct regulator *) p_mipi_1_8v;\n" - "+\n" - "+\tif (dsim == NULL) {\n" - "+\t\tprintk(KERN_ERR \"dsim is NULL.\\n\");\n" - "+\t\treturn -EFAULT;\n" - "+\t}\n" - "+\n" - "+\tif (IS_ERR(r_mipi_1_1v) || IS_ERR(r_mipi_1_8v)) {\n" - "+\t\tdev_err(dsim->dev, \"r_mipi_1_1v or r_mipi_1_8v is NULL.\\n\");\n" - "+\t\treturn -EINVAL;\n" - "+\t}\n" - "+\n" - "+\tif (enable) {\n" - "+\t\tif (r_mipi_1_1v)\n" - "+\t\t\tret = regulator_enable(r_mipi_1_1v);\n" - "+\n" - "+\t\tif (ret < 0) {\n" - "+\t\t\tdev_err(dsim->dev,\n" - "+\t\t\t\t\"failed to enable regulator mipi_1_1v.\\n\");\n" - "+\t\t\treturn ret;\n" - "+\t\t}\n" - "+\n" - "+\t\tif (r_mipi_1_8v)\n" - "+\t\t\tret = regulator_enable(r_mipi_1_8v);\n" - "+\n" - "+\t\tif (ret < 0) {\n" - "+\t\t\tdev_err(dsim->dev,\n" - "+\t\t\t\t\"failed to enable regulator mipi_1_8v.\\n\");\n" - "+\t\t\treturn ret;\n" - "+\t\t}\n" - "+\t} else {\n" - "+\t\tif (r_mipi_1_1v)\n" - "+\t\t\tret = regulator_force_disable(r_mipi_1_1v);\n" - "+\t\tif (ret < 0) {\n" - "+\t\t\tdev_err(dsim->dev,\n" - "+\t\t\t\t\"failed to disable regulator mipi_1_1v.\\n\");\n" - "+\t\t\treturn ret;\n" - "+\t\t}\n" - "+\n" - "+\t\tif (r_mipi_1_8v)\n" - "+\t\t\tret = regulator_force_disable(r_mipi_1_8v);\n" - "+\t\tif (ret < 0) {\n" - "+\t\t\tdev_err(dsim->dev,\n" - "+\t\t\t\t\"failed to disable regulator mipi_1_8v.\\n\");\n" - "+\t\t\treturn ret;\n" - "+\t\t}\n" - "+\t}\n" - "+\n" - "+\treturn ret;\n" - "+}\n" - "diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig\n" - "index 3d94a14..c916ac1 100644\n" - "--- a/drivers/video/Kconfig\n" - "+++ b/drivers/video/Kconfig\n" - "@@ -1930,7 +1930,7 @@ config FB_TMIO_ACCELL\n" - " \n" - " config FB_S3C\n" - " \ttristate \"Samsung S3C framebuffer support\"\n" - "-\tdepends on FB && ARCH_S3C64XX\n" - "+\tdepends on FB && (ARCH_S3C64XX || ARCH_S5PV210)\n" - " \tselect FB_CFB_FILLRECT\n" - " \tselect FB_CFB_COPYAREA\n" - " \tselect FB_CFB_IMAGEBLIT\n" - "@@ -1975,6 +1975,13 @@ config FB_S3C2410_DEBUG\n" - " \t Turn on debugging messages. Note that you can set/unset at run time\n" - " \t through sysfs\n" - " \n" - "+config S5P_MIPI_DSI\n" - "+\ttristate \"Samsung SoC MIPI-DSI support.\"\n" - "+\tdepends on FB_S3C && ARCH_S5PV210\n" - "+\tdefault n\n" - "+\t---help---\n" - "+\t This enables support for MIPI-DSI device.\n" - "+\n" - " config FB_NUC900\n" - " bool \"NUC900 LCD framebuffer support\"\n" - " depends on FB && ARCH_W90X900\n" - "diff --git a/drivers/video/Makefile b/drivers/video/Makefile\n" - "index ddc2af2..d841433 100644\n" - "--- a/drivers/video/Makefile\n" - "+++ b/drivers/video/Makefile\n" - "@@ -115,6 +115,8 @@ obj-$(CONFIG_FB_SH7760)\t\t += sh7760fb.o\n" - " obj-$(CONFIG_FB_IMX) += imxfb.o\n" - " obj-$(CONFIG_FB_S3C)\t\t += s3c-fb.o\n" - " obj-$(CONFIG_FB_S3C2410)\t += s3c2410fb.o\n" - "+obj-$(CONFIG_S5P_MIPI_DSI)\t += s5p-dsim.o s5p_dsim_common.o \\\n" - "+ \t\t\t\t\ts5p_dsim_lowlevel.o\n" - " obj-$(CONFIG_FB_FSL_DIU)\t += fsl-diu-fb.o\n" - " obj-$(CONFIG_FB_COBALT) += cobalt_lcdfb.o\n" - " obj-$(CONFIG_FB_PNX4008_DUM)\t += pnx4008/\n" - "diff --git a/drivers/video/s5p-dsim.c b/drivers/video/s5p-dsim.c\n" - "new file mode 100644\n" - "index 0000000..96893bc\n" - "--- /dev/null\n" - "+++ b/drivers/video/s5p-dsim.c\n" - "@@ -0,0 +1,483 @@\n" - "+/* linux/drivers/video/samsung/s5p-dsim.c\n" - "+ *\n" - "+ * Samsung MIPI-DSIM driver.\n" - "+ *\n" - "+ * InKi Dae, <a class=\"moz-txt-link-rfc2396E\" href=\"mailto:inki.dae@samsung.com\"><inki.dae@samsung.com></a>\n" - "+ *\n" - "+ * This program is free software; you can redistribute it and/or modify\n" - "+ * it under the terms of the GNU General Public License version 2 as\n" - "+ * published by the Free Software Foundation.\n" - "+*/\n" - "+\n" - "+#include <linux/module.h>\n" - "+#include <linux/kernel.h>\n" - "+#include <linux/errno.h>\n" - "+#include <linux/clk.h>\n" - "+#include <linux/mutex.h>\n" - "+#include <linux/wait.h>\n" - "+#include <linux/fs.h>\n" - "+#include <linux/mm.h>\n" - "+#include <linux/fb.h>\n" - "+#include <linux/ctype.h>\n" - "+#include <linux/platform_device.h>\n" - "+#include <linux/io.h>\n" - "+#include <linux/irq.h>\n" - "+#include <linux/memory.h>\n" - "+#include <linux/delay.h>\n" - "+#include <linux/interrupt.h>\n" - "+#include <linux/kthread.h>\n" - "+#include <linux/regulator/consumer.h>\n" - "+#include <linux/notifier.h>\n" - "+\n" - "+#include <plat/fb.h>\n" - "+#include <plat/regs-dsim.h>\n" - "+#include <plat/dsim.h>\n" - "+#include <plat/mipi_ddi.h>\n" - "+\n" - "+#include <mach/map.h>\n" - "+\n" - "+#include \"s5p_dsim_common.h\"\n" - "+\n" - "+struct mipi_lcd_info {\n" - "+\tstruct list_head\tlist;\n" - "+\tstruct mipi_lcd_driver\t*mipi_drv;\n" - "+};\n" - "+\n" - "+static LIST_HEAD(lcd_info_list);\n" - "+static DEFINE_MUTEX(mipi_lock);\n" - "+\n" - "+struct dsim_global dsim;\n" - "+\n" - "+struct s5p_platform_dsim *to_dsim_plat(struct device *dev)\n" - "+{\n" - "+\tstruct platform_device *pdev = to_platform_device(dev);\n" - "+\n" - "+\treturn (struct s5p_platform_dsim *)pdev->dev.platform_data;\n" - "+}\n" - "+\n" - "+/*\n" - "+ * notifier callback function for fb_blank\n" - "+ * - this function would be called by device specific fb_blank.\n" - "+ */\n" - "+static int s5p_dsim_notifier_callback(struct notifier_block *self,\n" - "+\tunsigned long event, void *data)\n" - "+{\n" - "+\tpm_message_t pm;\n" - "+\n" - "+\tpm.event = 0;\n" - "+\n" - "+\tswitch (event) {\n" - "+\tcase FB_BLANK_UNBLANK:\n" - "+\tcase FB_BLANK_NORMAL:\n" - "+\t\tif (dsim.pd->mipi_power)\n" - "+\t\t\tdsim.pd->mipi_power(&dsim, (void *) dsim.r_mipi_1_1v,\n" - "+\t\t\t\t(void *) dsim.r_mipi_1_8v, 1);\n" - "+\n" - "+\t\tclk_enable(dsim.clock);\n" - "+\n" - "+\t\tif (dsim.mipi_drv->resume)\n" - "+\t\t\tdsim.mipi_drv->resume(dsim.dev);\n" - "+\n" - "+\t\ts5p_dsim_init_dsim(&dsim);\n" - "+\t\ts5p_dsim_init_link(&dsim);\n" - "+\n" - "+\t\ts5p_dsim_set_hs_enable(&dsim);\n" - "+\t\ts5p_dsim_set_data_transfer_mode(&dsim,\n" - "+\t\t\tDSIM_TRANSFER_BYCPU, 1);\n" - "+\n" - "+\t\t/* it needs delay for stabilization */\n" - "+\t\tmdelay(dsim.pd->delay_for_stabilization);\n" - "+\n" - "+\t\tif (dsim.mipi_drv->init)\n" - "+\t\t\tdsim.mipi_drv->init(dsim.dev);\n" - "+\t\telse\n" - "+\t\t\tdev_warn(dsim.dev, \"init func is null.\\n\");\n" - "+\n" - "+\t\ts5p_dsim_set_display_mode(&dsim, dsim.dsim_lcd_info, NULL);\n" - "+\n" - "+\t\ts5p_dsim_set_data_transfer_mode(&dsim, DSIM_TRANSFER_BYLCDC, 1);\n" - "+\t\tdsim.mipi_ddi_pd->resume_complete = 1;\n" - "+\n" - "+\t\tdev_dbg(dsim.dev, \"FB_BLANK_NORMAL or UNBLANK.\\n\");\n" - "+\n" - "+\t\tbreak;\n" - "+\tcase FB_BLANK_POWERDOWN:\n" - "+\t\tdsim.mipi_ddi_pd->resume_complete = 0;\n" - "+\n" - "+\t\tif (dsim.mipi_drv->suspend)\n" - "+\t\t\tdsim.mipi_drv->suspend(dsim.dev, pm);\n" - "+\n" - "+\t\tclk_disable(dsim.clock);\n" - "+\n" - "+\t\tif (dsim.pd->mipi_power)\n" - "+\t\t\tdsim.pd->mipi_power(&dsim, (void *) dsim.r_mipi_1_1v,\n" - "+\t\t\t\t(void *) dsim.r_mipi_1_8v, 0);\n" - "+\n" - "+\t\tdev_dbg(dsim.dev, \"FB_BLANK_POWERDOWN.\\n\");\n" - "+\t\tbreak;\n" - "+\tdefault:\n" - "+\t\tdev_warn(dsim.dev, \"unknown FB_BLANK command.\\n\");\n" - "+\t\tbreak;\n" - "+\t}\n" - "+\n" - "+\treturn 0;\n" - "+}\n" - "+\n" - "+static int s5p_dsim_register_notif(struct device *dev)\n" - "+{\n" - "+\tmemset(&dsim.s3cfb_notif, 0, sizeof(struct notifier_block));\n" - "+\tdsim.s3cfb_notif.notifier_call = s5p_dsim_notifier_callback;\n" - "+\n" - "+\treturn 0/*s3cfb_register_client(&dsim.s3cfb_notif)*/;\n" - "+}\n" - "+\n" - "+static irqreturn_t s5p_dsim_interrupt_handler(int irq, void *dev_id)\n" - "+{\n" - "+\tdisable_irq(irq);\n" - "+\n" - "+\t/* additional work. */\n" - "+\n" - "+\tenable_irq(irq);\n" - "+\n" - "+\treturn IRQ_HANDLED;\n" - "+}\n" - "+\n" - "+int s5p_dsim_register_lcd_driver(struct mipi_lcd_driver *lcd_drv)\n" - "+{\n" - "+\tstruct mipi_lcd_info\t*lcd_info = NULL;\n" - "+\n" - "+\tlcd_info = kmalloc(sizeof(struct mipi_lcd_info), GFP_KERNEL);\n" - "+\tif (lcd_info == NULL)\n" - "+\t\treturn -ENOMEM;\n" - "+\n" - "+\tlcd_info->mipi_drv = kmalloc(sizeof(struct mipi_lcd_driver),\n" - "+\t\tGFP_KERNEL);\n" - "+\tif (lcd_info->mipi_drv == NULL)\n" - "+\t\treturn -ENOMEM;\n" - "+\n" - "+\n" - "+\tmemcpy(lcd_info->mipi_drv, lcd_drv, sizeof(struct mipi_lcd_driver));\n" - "+\n" - "+\tmutex_lock(&mipi_lock);\n" - "+\tlist_add_tail(&lcd_info->list, &lcd_info_list);\n" - "+\tmutex_unlock(&mipi_lock);\n" - "+\n" - "+\tdev_dbg(dsim.dev, \"registered panel driver(%s) to mipi-dsi driver.\\n\",\n" - "+\t\tlcd_drv->name);\n" - "+\n" - "+\treturn 0;\n" - "+}\n" - "+\n" - "+/*\n" - "+ * This function is wrapper for changing transfer mode.\n" - "+ * It is used to in panel driver before and after changing gamma value.\n" - "+ */\n" - "+static int s5p_dsim_change_transfer_mode(int mode)\n" - "+{\n" - "+\tif (mode < 0 || mode > 1) {\n" - "+\t\tdev_err(dsim.dev, \"mode range should be 0 or 1.\\n\");\n" - "+\t\treturn -EFAULT;\n" - "+\t}\n" - "+\n" - "+\tif (mode == 0)\n" - "+\t\ts5p_dsim_set_data_transfer_mode(&dsim,\n" - "+\t\t\tDSIM_TRANSFER_BYCPU, mode);\n" - "+\telse\n" - "+\t\ts5p_dsim_set_data_transfer_mode(&dsim,\n" - "+\t\t\tDSIM_TRANSFER_BYLCDC, mode);\n" - "+\n" - "+\treturn 0;\n" - "+}\n" - "+\n" - "+struct mipi_lcd_driver *scan_mipi_driver(const char *name)\n" - "+{\n" - "+\tstruct mipi_lcd_info *lcd_info;\n" - "+\tstruct mipi_lcd_driver *mipi_drv = NULL;\n" - "+\n" - "+\tmutex_lock(&mipi_lock);\n" - "+\n" - "+\tdev_dbg(dsim.dev, \"find lcd panel driver(%s).\\n\",\n" - "+\t\tname);\n" - "+\n" - "+\tlist_for_each_entry(lcd_info, &lcd_info_list, list) {\n" - "+\t\tmipi_drv = lcd_info->mipi_drv;\n" - "+\n" - "+\t\tif ((strcmp(mipi_drv->name, name)) == 0) {\n" - "+\t\t\tmutex_unlock(&mipi_lock);\n" - "+\t\t\tdev_dbg(dsim.dev, \"found!!!(%s).\\n\", mipi_drv->name);\n" - "+\t\t\treturn mipi_drv;\n" - "+\t\t}\n" - "+\t}\n" - "+\n" - "+\tdev_warn(dsim.dev, \"failed to find lcd panel driver(%s).\\n\",\n" - "+\t\tname);\n" - "+\n" - "+\tmutex_unlock(&mipi_lock);\n" - "+\n" - "+\treturn NULL;\n" - "+}\n" - "+\n" - "+static int s5p_dsim_probe(struct platform_device *pdev)\n" - "+{\n" - "+\tstruct resource *res;\n" - "+\tint ret = -1;\n" - "+\n" - "+\tdsim.pd = to_dsim_plat(&pdev->dev);\n" - "+\tdsim.dev = &pdev->dev;\n" - "+\n" - "+\t/* set dsim config data, dsim lcd config data and lcd panel data. */\n" - "+\tdsim.dsim_info = dsim.pd->dsim_info;\n" - "+\tdsim.dsim_lcd_info = dsim.pd->dsim_lcd_info;\n" - "+\tdsim.lcd_panel_info =\n" - "+\t\t(struct fb_videomode *) dsim.dsim_lcd_info->lcd_panel_info;\n" - "+\tdsim.mipi_ddi_pd =\n" - "+\t\t(struct mipi_ddi_platform_data *)\n" - "+\t\t\tdsim.dsim_lcd_info->mipi_ddi_pd;\n" - "+\n" - "+\tdsim.mipi_ddi_pd->resume_complete = 0;\n" - "+\n" - "+\tdsim.r_mipi_1_1v = regulator_get(&pdev->dev, \"VMIPI_1.1V\");\n" - "+\tif (IS_ERR(dsim.r_mipi_1_1v)) {\n" - "+\t\tdev_err(&pdev->dev, \"failed to get regulator VMIPI_1.1V.\\n\");\n" - "+\t\tgoto regulator_get_err;\n" - "+\t}\n" - "+\n" - "+\tdsim.r_mipi_1_8v = regulator_get(&pdev->dev, \"VMIPI_1.8V\");\n" - "+\tif (IS_ERR(dsim.r_mipi_1_8v)) {\n" - "+\t\tdev_err(&pdev->dev, \"failed to get regulator VMIPI_1.8V.\\n\");\n" - "+\t\tgoto regulator_get_err;\n" - "+\t}\n" - "+\n" - "+\t/* clock */\n" - "+\tdsim.clock = clk_get(&pdev->dev, dsim.pd->clk_name);\n" - "+\tif (IS_ERR(dsim.clock)) {\n" - "+\t\tdev_err(&pdev->dev, \"failed to get dsim clock source\\n\");\n" - "+\t\treturn -EINVAL;\n" - "+\t}\n" - "+\n" - "+\tclk_enable(dsim.clock);\n" - "+\n" - "+\t/* io memory */\n" - "+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n" - "+\tif (!res) {\n" - "+\t\tdev_err(&pdev->dev, \"failed to get io memory region\\n\");\n" - "+\t\tret = -EINVAL;\n" - "+\t\tgoto err_clk_disable;\n" - "+\t}\n" - "+\n" - "+\t/* request mem region */\n" - "+\tres = request_mem_region(res->start,\n" - "+\t\t\t\t res->end - res->start + 1, pdev->name);\n" - "+\tif (!res) {\n" - "+\t\tdev_err(&pdev->dev, \"failed to request io memory region\\n\");\n" - "+\t\tret = -EINVAL;\n" - "+\t\tgoto err_clk_disable;\n" - "+\t}\n" - "+\n" - "+\t/* ioremap for register block */\n" - "+\tdsim.reg_base = (unsigned int) ioremap(res->start,\n" - "+\t\tres->end - res->start + 1);\n" - "+\tif (!dsim.reg_base) {\n" - "+\t\tdev_err(&pdev->dev, \"failed to remap io region\\n\");\n" - "+\t\tret = -EINVAL;\n" - "+\t\tgoto err_clk_disable;\n" - "+\t}\n" - "+\n" - "+\t/* it is used for MIPI-DSI based lcd panel driver. */\n" - "+\tdsim.mipi_ddi_pd->dsim_data = (void *)&dsim;\n" - "+\n" - "+\t/*\n" - "+\t * it uses frame done interrupt handler\n" - "+\t * only in case of MIPI Video mode.\n" - "+\t */\n" - "+\tif (dsim.dsim_lcd_info->e_interface == DSIM_VIDEO) {\n" - "+\t\tdsim.irq = platform_get_irq(pdev, 0);\n" - "+\t\tif (request_irq(dsim.irq, s5p_dsim_interrupt_handler,\n" - "+\t\t\t\tIRQF_TRIGGER_RISING, \"mipi-dsi\", &dsim)) {\n" - "+\t\t\tdev_err(&pdev->dev, \"request_irq failed.\\n\");\n" - "+\t\t\tgoto err_trigger_irq;\n" - "+\t\t}\n" - "+\t}\n" - "+\n" - "+\tif (dsim.pd->mipi_power)\n" - "+\t\tdsim.pd->mipi_power(&dsim, (void *) dsim.r_mipi_1_1v,\n" - "+\t\t\t(void *) dsim.r_mipi_1_8v, 1);\n" - "+\telse {\n" - "+\t\tdev_err(&pdev->dev, \"mipi_power is NULL.\\n\");\n" - "+\t\tgoto mipi_power_err;\n" - "+\t}\n" - "+\n" - "+\t/* find lcd panel driver registered to mipi-dsi driver. */\n" - "+\tdsim.mipi_drv = scan_mipi_driver(dsim.pd->lcd_panel_name);\n" - "+\tif (dsim.mipi_drv == NULL) {\n" - "+\t\tdev_err(&pdev->dev, \"mipi_drv is NULL.\\n\");\n" - "+\t\tgoto mipi_drv_err;\n" - "+\t}\n" - "+\n" - "+\t/* register callback functions that lcd panel driver needs. */\n" - "+\tdsim.mipi_ddi_pd->cmd_write = s5p_dsim_wr_data;\n" - "+\tdsim.mipi_ddi_pd->cmd_read = NULL;\n" - "+\tdsim.mipi_ddi_pd->get_dsim_frame_done =\n" - "+\t\ts5p_dsim_get_frame_done_status;\n" - "+\tdsim.mipi_ddi_pd->clear_dsim_frame_done = s5p_dsim_clear_frame_done;\n" - "+\tdsim.mipi_ddi_pd->change_dsim_transfer_mode =\n" - "+\t\ts5p_dsim_change_transfer_mode;\n" - "+\tdsim.mipi_ddi_pd->get_fb_frame_done = dsim.pd->get_fb_frame_done;\n" - "+\tdsim.mipi_ddi_pd->trigger = dsim.pd->trigger;\n" - "+\n" - "+\t/* set lcd panel driver link */\n" - "+\tret = dsim.mipi_drv->set_link(dsim.mipi_ddi_pd);\n" - "+\tif (ret < 0) {\n" - "+\t\tdev_err(&pdev->dev, \"failed to set link.\\n\");\n" - "+\t\tgoto mipi_drv_err;\n" - "+\t}\n" - "+\n" - "+\tdsim.mipi_drv->probe(&pdev->dev);\n" - "+\n" - "+\ts5p_dsim_init_dsim(&dsim);\n" - "+\ts5p_dsim_init_link(&dsim);\n" - "+\n" - "+\ts5p_dsim_set_hs_enable(&dsim);\n" - "+\ts5p_dsim_set_data_transfer_mode(&dsim, DSIM_TRANSFER_BYCPU, 1);\n" - "+\n" - "+\t/* it needs delay for stabilization */\n" - "+\tmdelay(dsim.pd->delay_for_stabilization);\n" - "+\n" - "+\t/* initialize lcd panel */\n" - "+\tif (dsim.mipi_drv->init)\n" - "+\t\tdsim.mipi_drv->init(&pdev->dev);\n" - "+\telse\n" - "+\t\tdev_warn(&pdev->dev, \"init func is null.\\n\");\n" - "+\n" - "+\tif (dsim.mipi_drv->display_on)\n" - "+\t\tdsim.mipi_drv->display_on(&pdev->dev);\n" - "+\telse\n" - "+\t\tdev_warn(&pdev->dev, \"display_on func is null.\\n\");\n" - "+\n" - "+\ts5p_dsim_set_display_mode(&dsim, dsim.dsim_lcd_info, NULL);\n" - "+\n" - "+\ts5p_dsim_set_data_transfer_mode(&dsim, DSIM_TRANSFER_BYLCDC, 1);\n" - "+\n" - "+\ts5p_dsim_register_notif(&pdev->dev);\n" - "+\n" - "+\t/* in case of command mode, trigger. */\n" - "+\tif (dsim.dsim_lcd_info->e_interface == DSIM_COMMAND) {\n" - "+\t\tif (dsim.pd->trigger)\n" - "+\t\t\tdsim.pd->trigger(registered_fb[0]);\n" - "+\t\telse\n" - "+\t\t\tdev_warn(&pdev->dev, \"trigger is null.\\n\");\n" - "+\t}\n" - "+\n" - "+\tdev_info(&pdev->dev, \"mipi-dsi driver(%s mode) has been probed.\\n\",\n" - "+\t\t(dsim.dsim_lcd_info->e_interface == DSIM_COMMAND) ?\n" - "+\t\t\t\"CPU\" : \"RGB\");\n" - "+\n" - "+\treturn 0;\n" - "+\n" - "+err_trigger_irq:\n" - "+mipi_drv_err:\n" - "+\tdsim.pd->mipi_power(&dsim, (void *) dsim.r_mipi_1_1v,\n" - "+\t\t(void *) dsim.r_mipi_1_8v, 0);\n" - "+\n" - "+mipi_power_err:\n" - "+\tiounmap((void __iomem *) dsim.reg_base);\n" - "+\n" - "+err_clk_disable:\n" - "+\tclk_disable(dsim.clock);\n" - "+\n" - "+regulator_get_err:\n" - "+\n" - "+\treturn ret;\n" - "+\n" - "+}\n" - "+\n" - "+static int s5p_dsim_remove(struct platform_device *pdev)\n" - "+{\n" - "+\treturn 0;\n" - "+}\n" - "+\n" - "+#ifdef CONFIG_PM\n" - "+int s5p_dsim_suspend(struct platform_device *pdev, pm_message_t state)\n" - "+{\n" - "+\tdsim.mipi_ddi_pd->resume_complete = 0;\n" - "+\n" - "+\tif (dsim.mipi_drv->suspend)\n" - "+\t\tdsim.mipi_drv->suspend(&pdev->dev, state);\n" - "+\n" - "+\tclk_disable(dsim.clock);\n" - "+\n" - "+\tif (dsim.pd->mipi_power)\n" - "+\t\tdsim.pd->mipi_power(&dsim, (void *) dsim.r_mipi_1_1v,\n" - "+\t\t\t(void *) dsim.r_mipi_1_8v, 0);\n" - "+\n" - "+\treturn 0;\n" - "+}\n" - "+\n" - "+int s5p_dsim_resume(struct platform_device *pdev)\n" - "+{\n" - "+\tif (dsim.pd->mipi_power)\n" - "+\t\tdsim.pd->mipi_power(&dsim, (void *) dsim.r_mipi_1_1v,\n" - "+\t\t\t(void *) dsim.r_mipi_1_8v, 1);\n" - "+\n" - "+\tclk_enable(dsim.clock);\n" - "+\n" - "+\tif (dsim.mipi_drv->resume)\n" - "+\t\tdsim.mipi_drv->resume(&pdev->dev);\n" - "+\n" - "+\ts5p_dsim_init_dsim(&dsim);\n" - "+\ts5p_dsim_init_link(&dsim);\n" - "+\n" - "+\ts5p_dsim_set_hs_enable(&dsim);\n" - "+\ts5p_dsim_set_data_transfer_mode(&dsim, DSIM_TRANSFER_BYCPU, 1);\n" - "+\n" - "+\t/* it needs delay for stabilization */\n" - "+\tmdelay(dsim.pd->delay_for_stabilization);\n" - "+\n" - "+\t/* initialize lcd panel */\n" - "+\tif (dsim.mipi_drv->init)\n" - "+\t\tdsim.mipi_drv->init(&pdev->dev);\n" - "+\telse\n" - "+\t\tdev_warn(&pdev->dev, \"init func is null.\\n\");\n" - "+\n" - "+\ts5p_dsim_set_display_mode(&dsim, dsim.dsim_lcd_info, NULL);\n" - "+\n" - "+\ts5p_dsim_set_data_transfer_mode(&dsim, DSIM_TRANSFER_BYLCDC, 1);\n" - "+\n" - "+\tdsim.mipi_ddi_pd->resume_complete = 1;\n" - "+\n" - "+\treturn 0;\n" - "+}\n" - "+#else\n" - "+#define s5p_dsim_suspend NULL\n" - "+#define s5p_dsim_resume NULL\n" - "+#endif\n" - "+\n" - "+static struct platform_driver s5p_dsim_driver = {\n" - "+\t.probe = s5p_dsim_probe,\n" - "+\t.remove = s5p_dsim_remove,\n" - "+\t.suspend = s5p_dsim_suspend,\n" - "+\t.resume = s5p_dsim_resume,\n" - "+\t.driver = {\n" - "+\t\t .name = \"s5p-dsim\",\n" - "+\t\t .owner = THIS_MODULE,\n" - "+\t},\n" - "+};\n" - "+\n" - "+static int s5p_dsim_register(void)\n" - "+{\n" - "+\tplatform_driver_register(&s5p_dsim_driver);\n" - "+\n" - "+\treturn 0;\n" - "+}\n" - "+\n" - "+static void s5p_dsim_unregister(void)\n" - "+{\n" - "+\tplatform_driver_unregister(&s5p_dsim_driver);\n" - "+}\n" - "+\n" - "+module_init(s5p_dsim_register);\n" - "+module_exit(s5p_dsim_unregister);\n" - "+\n" - "+MODULE_AUTHOR(\"InKi Dae <a class=\"moz-txt-link-rfc2396E\" href=\"mailto:inki.dae@samsung.com\"><inki.dae@samsung.com></a>\");\n" - "+MODULE_DESCRIPTION(\"Samusung MIPI-DSIM driver\");\n" - "+MODULE_LICENSE(\"GPL\");\n" - "diff --git a/drivers/video/s5p_dsim_common.c b/drivers/video/s5p_dsim_common.c\n" - "new file mode 100644\n" - "index 0000000..77724dc\n" - "--- /dev/null\n" - "+++ b/drivers/video/s5p_dsim_common.c\n" - "@@ -0,0 +1,753 @@\n" - "+/* linux/drivers/video/samsung/s5p_dsim_common.c\n" - "+ *\n" - "+ * Samsung MIPI-DSIM common driver.\n" - "+ *\n" - "+ * InKi Dae, <a class=\"moz-txt-link-rfc2396E\" href=\"mailto:inki.dae@samsung.com\"><inki.dae@samsung.com></a>\n" - "+ *\n" - "+ * This program is free software; you can redistribute it and/or modify\n" - "+ * it under the terms of the GNU General Public License version 2 as\n" - "+ * published by the Free Software Foundation.\n" - "+*/\n" - "+\n" - "+#include <linux/module.h>\n" - "+#include <linux/kernel.h>\n" - "+#include <linux/errno.h>\n" - "+#include <linux/mutex.h>\n" - "+#include <linux/wait.h>\n" - "+#include <linux/fs.h>\n" - "+#include <linux/mm.h>\n" - "+#include <linux/fb.h>\n" - "+#include <linux/ctype.h>\n" - "+#include <linux/platform_device.h>\n" - "+#include <linux/io.h>\n" - "+#include <linux/memory.h>\n" - "+#include <linux/delay.h>\n" - "+#include <linux/kthread.h>\n" - "+\n" - "+#include <plat/fb.h>\n" - "+#include <plat/regs-dsim.h>\n" - "+\n" - "+#include <mach/map.h>\n" - "+#include <plat/dsim.h>\n" - "+#include <plat/mipi_ddi.h>\n" - "+\n" - "+#include \"s5p_dsim_lowlevel.h\"\n" - "+\n" - "+static void s5p_dsim_long_data_wr(struct dsim_global *dsim, unsigned int data0,\n" - "+\tunsigned int data1)\n" - "+{\n" - "+\tunsigned int data_cnt = 0, payload = 0;\n" - "+\n" - "+\t/* in case that data count is more then 4 */\n" - "+\tfor (data_cnt = 0; data_cnt < data1; data_cnt += 4) {\n" - "+\t\t/*\n" - "+\t\t * after sending 4bytes per one time,\n" - "+\t\t * send remainder data less then 4.\n" - "+\t\t */\n" - "+\t\tif ((data1 - data_cnt) < 4) {\n" - "+\t\t\tif ((data1 - data_cnt) == 3) {\n" - "+\t\t\t\tpayload = *(u8 *)(data0 + data_cnt) |\n" - "+\t\t\t\t (*(u8 *)(data0 + (data_cnt + 1))) << 8 |\n" - "+\t\t\t\t\t(*(u8 *)(data0 + (data_cnt + 2))) << 16;\n" - "+\t\t\tdev_dbg(dsim->dev, \"count = 3 payload = %x, %x %x %x\\n\",\n" - "+\t\t\t\tpayload, *(u8 *)(data0 + data_cnt),\n" - "+\t\t\t\t*(u8 *)(data0 + (data_cnt + 1)),\n" - "+\t\t\t\t*(u8 *)(data0 + (data_cnt + 2)));\n" - "+\t\t\t} else if ((data1 - data_cnt) == 2) {\n" - "+\t\t\t\tpayload = *(u8 *)(data0 + data_cnt) |\n" - "+\t\t\t\t\t(*(u8 *)(data0 + (data_cnt + 1))) << 8;\n" - "+\t\t\tdev_dbg(dsim->dev,\n" - "+\t\t\t\t\"count = 2 payload = %x, %x %x\\n\", payload,\n" - "+\t\t\t\t*(u8 *)(data0 + data_cnt),\n" - "+\t\t\t\t*(u8 *)(data0 + (data_cnt + 1)));\n" - "+\t\t\t} else if ((data1 - data_cnt) == 1) {\n" - "+\t\t\t\tpayload = *(u8 *)(data0 + data_cnt);\n" - "+\t\t\t}\n" - "+\n" - "+\t\t\ts5p_dsim_wr_tx_data(dsim, payload);\n" - "+\t\t/* send 4bytes per one time. */\n" - "+\t\t} else {\n" - "+\t\t\tpayload = *(u8 *)(data0 + data_cnt) |\n" - "+\t\t\t\t(*(u8 *)(data0 + (data_cnt + 1))) << 8 |\n" - "+\t\t\t\t(*(u8 *)(data0 + (data_cnt + 2))) << 16 |\n" - "+\t\t\t\t(*(u8 *)(data0 + (data_cnt + 3))) << 24;\n" - "+\n" - "+\t\t\tdev_dbg(dsim->dev,\n" - "+\t\t\t\t\"count = 4 payload = %x, %x %x %x %x\\n\",\n" - "+\t\t\t\tpayload, *(u8 *)(data0 + data_cnt),\n" - "+\t\t\t\t*(u8 *)(data0 + (data_cnt + 1)),\n" - "+\t\t\t\t*(u8 *)(data0 + (data_cnt + 2)),\n" - "+\t\t\t\t*(u8 *)(data0 + (data_cnt + 3)));\n" - "+\n" - "+\t\t\ts5p_dsim_wr_tx_data(dsim, payload);\n" - "+\t\t}\n" - "+\t}\n" - "+}\n" - "+\n" - "+int s5p_dsim_wr_data(void *dsim_data, unsigned int data_id,\n" - "+\tunsigned int data0, unsigned int data1)\n" - "+{\n" - "+\tstruct dsim_global *dsim = NULL;\n" - "+\tunsigned int timeout = 5000 * 2;\n" - "+\tunsigned long delay_val, udelay;\n" - "+\tunsigned char check_rx_ack = 0;\n" - "+\n" - "+\tdsim = (struct dsim_global *)dsim_data;\n" - "+\n" - "+\tif (dsim == NULL) {\n" - "+\t\tdev_err(dsim->dev, \"dsim_data is NULL.\\n\");\n" - "+\t\treturn -EFAULT;\n" - "+\t}\n" - "+\n" - "+\n" - "+\tif (dsim->state == DSIM_STATE_ULPS) {\n" - "+\t\tdev_err(dsim->dev, \"state is ULPS.\\n\");\n" - "+\n" - "+\t\treturn -EINVAL;\n" - "+\t}\n" - "+\n" - "+\tdelay_val = 1000000 / dsim->dsim_info->esc_clk;\n" - "+\tudelay = 10 * delay_val;\n" - "+\n" - "+\tmdelay(udelay);\n" - "+\n" - "+\t/* only if transfer mode is LPDT, wait SFR becomes empty. */\n" - "+\tif (dsim->state == DSIM_STATE_STOP) {\n" - "+\t\twhile (!(s5p_dsim_get_fifo_state(dsim) &\n" - "+\t\t\t\tSFR_HEADER_EMPTY)) {\n" - "+\t\t\tif ((timeout--) > 0)\n" - "+\t\t\t\tmdelay(1);\n" - "+\t\t\telse {\n" - "+\t\t\t\tdev_err(dsim->dev,\n" - "+\t\t\t\t\t\"SRF header fifo is not empty.\\n\");\n" - "+\t\t\t\treturn -EINVAL;\n" - "+\t\t\t}\n" - "+\t\t}\n" - "+\t}\n" - "+\n" - "+\tswitch (data_id) {\n" - "+\t/* short packet types of packet types for command. */\n" - "+\tcase GEN_SHORT_WR_NO_PARA:\n" - "+\tcase GEN_SHORT_WR_1_PARA:\n" - "+\tcase GEN_SHORT_WR_2_PARA:\n" - "+\tcase DCS_WR_NO_PARA:\n" - "+\tcase DCS_WR_1_PARA:\n" - "+\tcase SET_MAX_RTN_PKT_SIZE:\n" - "+\t\ts5p_dsim_wr_tx_header(dsim, (unsigned char) data_id,\n" - "+\t\t\t(unsigned char) data0, (unsigned char) data1);\n" - "+\t\tif (check_rx_ack)\n" - "+\t\t\t/* process response func should be implemented */\n" - "+\t\t\treturn 0;\n" - "+\t\telse\n" - "+\t\t\treturn -EINVAL;\n" - "+\n" - "+\t/* general command */\n" - "+\tcase CMD_OFF:\n" - "+\tcase CMD_ON:\n" - "+\tcase SHUT_DOWN:\n" - "+\tcase TURN_ON:\n" - "+\t\ts5p_dsim_wr_tx_header(dsim, (unsigned char) data_id,\n" - "+\t\t\t(unsigned char) data0, (unsigned char) data1);\n" - "+\t\tif (check_rx_ack)\n" - "+\t\t\t/* process response func should be implemented. */\n" - "+\t\t\treturn 0;\n" - "+\t\telse\n" - "+\t\t\treturn -EINVAL;\n" - "+\n" - "+\t/* packet types for video data */\n" - "+\tcase VSYNC_START:\n" - "+\tcase VSYNC_END:\n" - "+\tcase HSYNC_START:\n" - "+\tcase HSYNC_END:\n" - "+\tcase EOT_PKT:\n" - "+\t\treturn 0;\n" - "+\n" - "+\t/* short and response packet types for command */\n" - "+\tcase GEN_RD_1_PARA:\n" - "+\tcase GEN_RD_2_PARA:\n" - "+\tcase GEN_RD_NO_PARA:\n" - "+\tcase DCS_RD_NO_PARA:\n" - "+\t\ts5p_dsim_clear_interrupt(dsim, 0xffffffff);\n" - "+\t\ts5p_dsim_wr_tx_header(dsim, (unsigned char) data_id,\n" - "+\t\t\t(unsigned char) data0, (unsigned char) data1);\n" - "+\t\t/* process response func should be implemented. */\n" - "+\t\treturn 0;\n" - "+\n" - "+\t/* long packet type and null packet */\n" - "+\tcase NULL_PKT:\n" - "+\tcase BLANKING_PKT:\n" - "+\t\treturn 0;\n" - "+\tcase GEN_LONG_WR:\n" - "+\tcase DCS_LONG_WR:\n" - "+\t{\n" - "+\t\tunsigned int size, data_cnt = 0, payload = 0;\n" - "+\n" - "+\t\tsize = data1 * 4;\n" - "+\n" - "+\t\t/* if data count is less then 4, then send 3bytes data. */\n" - "+\t\tif (data1 < 4) {\n" - "+\t\t\tpayload = *(u8 *)(data0) |\n" - "+\t\t\t\t*(u8 *)(data0 + 1) << 8 |\n" - "+\t\t\t\t*(u8 *)(data0 + 2) << 16;\n" - "+\n" - "+\t\t\ts5p_dsim_wr_tx_data(dsim, payload);\n" - "+\n" - "+\t\t\tdev_dbg(dsim->dev, \"count = %d payload = %x,%x %x %x\\n\",\n" - "+\t\t\t\tdata1, payload,\n" - "+\t\t\t\t*(u8 *)(data0 + data_cnt),\n" - "+\t\t\t\t*(u8 *)(data0 + (data_cnt + 1)),\n" - "+\t\t\t\t*(u8 *)(data0 + (data_cnt + 2)));\n" - "+\t\t/* in case that data count is more then 4 */\n" - "+\t\t} else\n" - "+\t\t\ts5p_dsim_long_data_wr(dsim, data0, data1);\n" - "+\n" - "+\t\t/* put data into header fifo */\n" - "+\t\ts5p_dsim_wr_tx_header(dsim, (unsigned char) data_id,\n" - "+\t\t\t(unsigned char) (((unsigned short) data1) & 0xff),\n" - "+\t\t\t(unsigned char) ((((unsigned short) data1) & 0xff00) >>\n" - "+\t\t\t\t8));\n" - "+\n" - "+\t}\n" - "+\tif (check_rx_ack)\n" - "+\t\t/* process response func should be implemented. */\n" - "+\t\treturn 0;\n" - "+\telse\n" - "+\t\treturn -EINVAL;\n" - "+\n" - "+\t/* packet typo for video data */\n" - "+\tcase RGB565_PACKED:\n" - "+\tcase RGB666_PACKED:\n" - "+\tcase RGB666_LOOSLY:\n" - "+\tcase RGB888_PACKED:\n" - "+\t\tif (check_rx_ack)\n" - "+\t\t\t/* process response func should be implemented. */\n" - "+\t\t\treturn 0;\n" - "+\t\telse\n" - "+\t\t\treturn -EINVAL;\n" - "+\tdefault:\n" - "+\t\tdev_warn(dsim->dev,\n" - "+\t\t\t\"data id %x is not supported current DSI spec.\\n\",\n" - "+\t\t\tdata_id);\n" - "+\n" - "+\t\treturn -EINVAL;\n" - "+\t}\n" - "+\n" - "+\treturn 0;\n" - "+}\n" - "+\n" - "+int s5p_dsim_init_header_fifo(struct dsim_global *dsim)\n" - "+{\n" - "+\tunsigned int cnt;\n" - "+\n" - "+\tif (dsim == NULL) {\n" - "+\t\tprintk(KERN_ERR \"dsim_global pointer is NULL.\\n\");\n" - "+\t\treturn -EFAULT;\n" - "+\t}\n" - "+\n" - "+\tfor (cnt = 0; cnt < DSIM_HEADER_FIFO_SZ; cnt++)\n" - "+\t\tdsim->header_fifo_index[cnt] = -1;\n" - "+\treturn 0;\n" - "+}\n" - "+\n" - "+int s5p_dsim_pll_on(struct dsim_global *dsim, unsigned char enable)\n" - "+{\n" - "+\tif (dsim == NULL) {\n" - "+\t\tprintk(KERN_ERR \"dsim_global pointer is NULL.\\n\");\n" - "+\t\treturn -EFAULT;\n" - "+\t}\n" - "+\n" - "+\tif (enable) {\n" - "+\t\tint sw_timeout = 1000;\n" - "+\t\ts5p_dsim_clear_interrupt(dsim, DSIM_PLL_STABLE);\n" - "+\t\ts5p_dsim_enable_pll(dsim, 1);\n" - "+\t\twhile (1) {\n" - "+\t\t\tsw_timeout--;\n" - "+\t\t\tif (s5p_dsim_is_pll_stable(dsim))\n" - "+\t\t\t\treturn 0;\n" - "+\t\t\tif (sw_timeout == 0)\n" - "+\t\t\t\treturn -EINVAL;\n" - "+\t\t}\n" - "+\t} else\n" - "+\t\ts5p_dsim_enable_pll(dsim, 0);\n" - "+\n" - "+\treturn 0;\n" - "+}\n" - "+\n" - "+unsigned long s5p_dsim_change_pll(struct dsim_global *dsim,\n" - "+\tunsigned char pre_divider, unsigned short main_divider,\n" - "+\tunsigned char scaler)\n" - "+{\n" - "+\tunsigned long dfin_pll, dfvco, dpll_out;\n" - "+\tunsigned char freq_band;\n" - "+\n" - "+\tif (dsim == NULL) {\n" - "+\t\tprintk(KERN_ERR \"dsim_global pointer is NULL.\\n\");\n" - "+\t\treturn 0;\n" - "+\t}\n" - "+\n" - "+\tdfin_pll = (MIPI_FIN / pre_divider);\n" - "+\n" - "+\tif (dfin_pll < 6 * 1000 * 1000 || dfin_pll > 12 * 1000 * 1000) {\n" - "+\t\tdev_warn(dsim->dev, \"warning!!\\n\");\n" - "+\t\tdev_warn(dsim->dev, \"fin_pll range is 6MHz ~ 12MHz\\n\");\n" - "+\t\tdev_warn(dsim->dev, \"fin_pll of mipi dphy pll is %luMHz\\n\",\n" - "+\t\t\t(dfin_pll / 1000000));\n" - "+\n" - "+\t\ts5p_dsim_enable_afc(dsim, 0, 0);\n" - "+\t} else {\n" - "+\t\tif (dfin_pll < 7 * 1000000)\n" - "+\t\t\ts5p_dsim_enable_afc(dsim, 1, 0x1);\n" - "+\t\telse if (dfin_pll < 8 * 1000000)\n" - "+\t\t\ts5p_dsim_enable_afc(dsim, 1, 0x0);\n" - "+\t\telse if (dfin_pll < 9 * 1000000)\n" - "+\t\t\ts5p_dsim_enable_afc(dsim, 1, 0x3);\n" - "+\t\telse if (dfin_pll < 10 * 1000000)\n" - "+\t\t\ts5p_dsim_enable_afc(dsim, 1, 0x2);\n" - "+\t\telse if (dfin_pll < 11 * 1000000)\n" - "+\t\t\ts5p_dsim_enable_afc(dsim, 1, 0x5);\n" - "+\t\telse\n" - "+\t\t\ts5p_dsim_enable_afc(dsim, 1, 0x4);\n" - "+\t}\n" - "+\n" - "+\tdfvco = dfin_pll * main_divider;\n" - "+\tdev_dbg(dsim->dev, \"dfvco = %lu, dfin_pll = %lu, main_divider = %d\\n\",\n" - "+\t\tdfvco, dfin_pll, main_divider);\n" - "+\tif (dfvco < 500000000 || dfvco > 1000000000) {\n" - "+\t\tdev_warn(dsim->dev, \"Caution!!\\n\");\n" - "+\t\tdev_warn(dsim->dev, \"fvco range is 500MHz ~ 1000MHz\\n\");\n" - "+\t\tdev_warn(dsim->dev, \"fvco of mipi dphy pll is %luMHz\\n\",\n" - "+\t\t\t(dfvco / 1000000));\n" - "+\t}\n" - "+\n" - "+\tdpll_out = dfvco / (1 << scaler);\n" - "+\tdev_dbg(dsim->dev, \"dpll_out = %lu, dfvco = %lu, scaler = %d\\n\",\n" - "+\t\tdpll_out, dfvco, scaler);\n" - "+\tif (dpll_out < 100 * 1000000)\n" - "+\t\tfreq_band = 0x0;\n" - "+\telse if (dpll_out < 120 * 1000000)\n" - "+\t\tfreq_band = 0x1;\n" - "+\telse if (dpll_out < 170 * 1000000)\n" - "+\t\tfreq_band = 0x2;\n" - "+\telse if (dpll_out < 220 * 1000000)\n" - "+\t\tfreq_band = 0x3;\n" - "+\telse if (dpll_out < 270 * 1000000)\n" - "+\t\tfreq_band = 0x4;\n" - "+\telse if (dpll_out < 320 * 1000000)\n" - "+\t\tfreq_band = 0x5;\n" - "+\telse if (dpll_out < 390 * 1000000)\n" - "+\t\tfreq_band = 0x6;\n" - "+\telse if (dpll_out < 450 * 1000000)\n" - "+\t\tfreq_band = 0x7;\n" - "+\telse if (dpll_out < 510 * 1000000)\n" - "+\t\tfreq_band = 0x8;\n" - "+\telse if (dpll_out < 560 * 1000000)\n" - "+\t\tfreq_band = 0x9;\n" - "+\telse if (dpll_out < 640 * 1000000)\n" - "+\t\tfreq_band = 0xa;\n" - "+\telse if (dpll_out < 690 * 1000000)\n" - "+\t\tfreq_band = 0xb;\n" - "+\telse if (dpll_out < 770 * 1000000)\n" - "+\t\tfreq_band = 0xc;\n" - "+\telse if (dpll_out < 870 * 1000000)\n" - "+\t\tfreq_band = 0xd;\n" - "+\telse if (dpll_out < 950 * 1000000)\n" - "+\t\tfreq_band = 0xe;\n" - "+\telse\n" - "+\t\tfreq_band = 0xf;\n" - "+\n" - "+\tdev_dbg(dsim->dev, \"freq_band = %d\\n\", freq_band);\n" - "+\n" - "+\ts5p_dsim_pll_freq(dsim, pre_divider, main_divider, scaler);\n" - "+\n" - "+\t{\n" - "+\t unsigned char temp0, temp1;\n" - "+\n" - "+\t temp0 = 0;\n" - "+\t s5p_dsim_hs_zero_ctrl(dsim, temp0);\n" - "+\t temp1 = 0;\n" - "+\t s5p_dsim_prep_ctrl(dsim, temp1);\n" - "+\t}\n" - "+\n" - "+\t/* Freq Band */\n" - "+\ts5p_dsim_pll_freq_band(dsim, freq_band);\n" - "+\n" - "+\t/* Stable time */\n" - "+\ts5p_dsim_pll_stable_time(dsim,\n" - "+\t\tdsim->dsim_info->pll_stable_time);\n" - "+\n" - "+\t/* Enable PLL */\n" - "+\tdev_dbg(dsim->dev, \"FOUT of mipi dphy pll is %luMHz\\n\",\n" - "+\t\t(dpll_out / 1000000));\n" - "+\n" - "+\treturn dpll_out;\n" - "+}\n" - "+\n" - "+int s5p_dsim_set_clock(struct dsim_global *dsim,\n" - "+\tunsigned char byte_clk_sel, unsigned char enable)\n" - "+{\n" - "+\tunsigned int esc_div;\n" - "+\tunsigned long esc_clk_error_rate;\n" - "+\n" - "+\tif (dsim == NULL) {\n" - "+\t\tprintk(KERN_ERR \"dsim_global pointer is NULL.\\n\");\n" - "+\t\treturn -EINVAL;\n" - "+\t}\n" - "+\n" - "+\tif (enable) {\n" - "+\t\tdsim->e_clk_src = byte_clk_sel;\n" - "+\n" - "+\t\t/* Escape mode clock and byte clock source */\n" - "+\t\ts5p_dsim_set_byte_clock_src(dsim, byte_clk_sel);\n" - "+\n" - "+\t\t/* DPHY, DSIM Link : D-PHY clock out */\n" - "+\t\tif (byte_clk_sel == DSIM_PLL_OUT_DIV8) {\n" - "+\t\t\tdsim->hs_clk = s5p_dsim_change_pll(dsim,\n" - "+\t\t\t\tdsim->dsim_info->p, dsim->dsim_info->m,\n" - "+\t\t\t\tdsim->dsim_info->s);\n" - "+\t\t\tif (dsim->hs_clk == 0) {\n" - "+\t\t\t\tdev_err(dsim->dev,\n" - "+\t\t\t\t\t\"failed to get hs clock.\\n\");\n" - "+\t\t\t\treturn -EINVAL;\n" - "+\t\t\t}\n" - "+\n" - "+\t\t\tdsim->byte_clk = dsim->hs_clk / 8;\n" - "+\t\t\ts5p_dsim_enable_pll_bypass(dsim, 0);\n" - "+\t\t\ts5p_dsim_pll_on(dsim, 1);\n" - "+\t\t/* DPHY : D-PHY clock out, DSIM link : external clock out */\n" - "+\t\t} else if (byte_clk_sel == DSIM_EXT_CLK_DIV8)\n" - "+\t\t\tdev_warn(dsim->dev,\n" - "+\t\t\t\t\"this project is not support \\\n" - "+\t\t\t\texternal clock source for MIPI DSIM\\n\");\n" - "+\t\telse if (byte_clk_sel == DSIM_EXT_CLK_BYPASS)\n" - "+\t\t\tdev_warn(dsim->dev,\n" - "+\t\t\t\t\"this project is not support \\\n" - "+\t\t\t\texternal clock source for MIPI DSIM\\n\");\n" - "+\n" - "+\t\t/* escape clock divider */\n" - "+\t\tesc_div = dsim->byte_clk / (dsim->dsim_info->esc_clk);\n" - "+\t\tdev_dbg(dsim->dev,\n" - "+\t\t\t\"esc_div = %d, byte_clk = %lu, esc_clk = %lu\\n\",\n" - "+\t\t\tesc_div, dsim->byte_clk, dsim->dsim_info->esc_clk);\n" - "+\t\tif ((dsim->byte_clk / esc_div) >= 20000000 ||\n" - "+\t\t\t(dsim->byte_clk / esc_div) > dsim->dsim_info->esc_clk)\n" - "+\t\t\tesc_div += 1;\n" - "+\n" - "+\t\tdsim->escape_clk = dsim->byte_clk / esc_div;\n" - "+\t\tdev_dbg(dsim->dev,\n" - "+\t\t\t\"escape_clk = %lu, byte_clk = %lu, esc_div = %d\\n\",\n" - "+\t\t\tdsim->escape_clk, dsim->byte_clk, esc_div);\n" - "+\n" - "+\t\t/*\n" - "+\t\t * enable escclk on lane\n" - "+\t\t *\n" - "+\t\t * in case of evt0, DSIM_TRUE is enable and\n" - "+\t\t * DSIM_FALSE is enable for evt1.\n" - "+\t\t */\n" - "+\t\tif (dsim->pd->platform_rev == 1)\n" - "+\t\t\ts5p_dsim_enable_byte_clock(dsim, DSIM_FALSE);\n" - "+\t\telse\n" - "+\t\t\ts5p_dsim_enable_byte_clock(dsim, DSIM_TRUE);\n" - "+\n" - "+\t\t/* enable byte clk and escape clock */\n" - "+\t\ts5p_dsim_set_esc_clk_prs(dsim, 1, esc_div);\n" - "+\t\t/* escape clock on lane */\n" - "+\t\ts5p_dsim_enable_esc_clk_on_lane(dsim,\n" - "+\t\t\t(DSIM_LANE_CLOCK | dsim->data_lane), 1);\n" - "+\n" - "+\t\tdev_dbg(dsim->dev, \"byte clock is %luMHz\\n\",\n" - "+\t\t\t(dsim->byte_clk / 1000000));\n" - "+\t\tdev_dbg(dsim->dev, \"escape clock that user's need is %lu\\n\",\n" - "+\t\t\t(dsim->dsim_info->esc_clk / 1000000));\n" - "+\t\tdev_dbg(dsim->dev, \"escape clock divider is %x\\n\", esc_div);\n" - "+\t\tdev_dbg(dsim->dev, \"escape clock is %luMHz\\n\",\n" - "+\t\t\t((dsim->byte_clk / esc_div) / 1000000));\n" - "+\n" - "+\t\tif ((dsim->byte_clk / esc_div) > dsim->escape_clk) {\n" - "+\t\t\tesc_clk_error_rate = dsim->escape_clk /\n" - "+\t\t\t\t(dsim->byte_clk / esc_div);\n" - "+\t\t\tdev_warn(dsim->dev, \"error rate is %lu over.\\n\",\n" - "+\t\t\t\t(esc_clk_error_rate / 100));\n" - "+\t\t} else if ((dsim->byte_clk / esc_div) < (dsim->escape_clk)) {\n" - "+\t\t\tesc_clk_error_rate = (dsim->byte_clk / esc_div) /\n" - "+\t\t\t\tdsim->escape_clk;\n" - "+\t\t\tdev_warn(dsim->dev, \"error rate is %lu under.\\n\",\n" - "+\t\t\t\t(esc_clk_error_rate / 100));\n" - "+\t\t}\n" - "+\t} else {\n" - "+\t\ts5p_dsim_enable_esc_clk_on_lane(dsim,\n" - "+\t\t\t(DSIM_LANE_CLOCK | dsim->data_lane), 0);\n" - "+\t\ts5p_dsim_set_esc_clk_prs(dsim, 0, 0);\n" - "+\n" - "+\t\t/*\n" - "+\t\t * in case of evt0, DSIM_FALSE is disable and\n" - "+\t\t * DSIM_TRUE is disable for evt1.\n" - "+\t\t */\n" - "+\t\tif (dsim->pd->platform_rev == 1)\n" - "+\t\t\ts5p_dsim_enable_byte_clock(dsim, DSIM_TRUE);\n" - "+\t\telse\n" - "+\t\t\ts5p_dsim_enable_byte_clock(dsim, DSIM_FALSE);\n" - "+\n" - "+\t\tif (byte_clk_sel == DSIM_PLL_OUT_DIV8)\n" - "+\t\t\ts5p_dsim_pll_on(dsim, 0);\n" - "+\t}\n" - "+\n" - "+\treturn 0;\n" - "+}\n" - "+\n" - "+int s5p_dsim_init_dsim(struct dsim_global *dsim)\n" - "+{\n" - "+\tif (dsim == NULL) {\n" - "+\t\tprintk(KERN_ERR \"dsim_global pointer is NULL.\\n\");\n" - "+\t\treturn -EFAULT;\n" - "+\t}\n" - "+\n" - "+\tif (dsim->pd->init_d_phy)\n" - "+\t\tdsim->pd->init_d_phy(dsim);\n" - "+\n" - "+\tdsim->state = DSIM_STATE_RESET;\n" - "+\n" - "+\tswitch (dsim->dsim_info->e_no_data_lane) {\n" - "+\tcase DSIM_DATA_LANE_1:\n" - "+\t\tdsim->data_lane = DSIM_LANE_DATA0;\n" - "+\t\tbreak;\n" - "+\tcase DSIM_DATA_LANE_2:\n" - "+\t\tdsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1;\n" - "+\t\tbreak;\n" - "+\tcase DSIM_DATA_LANE_3:\n" - "+\t\tdsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |\n" - "+\t\t\tDSIM_LANE_DATA2;\n" - "+\t\tbreak;\n" - "+\tcase DSIM_DATA_LANE_4:\n" - "+\t\tdsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |\n" - "+\t\t\tDSIM_LANE_DATA2 | DSIM_LANE_DATA3;\n" - "+\t\tbreak;\n" - "+\tdefault:\n" - "+\t\tdev_info(dsim->dev, \"data lane is invalid.\\n\");\n" - "+\t\treturn -EINVAL;\n" - "+\t};\n" - "+\n" - "+\ts5p_dsim_init_header_fifo(dsim);\n" - "+\ts5p_dsim_sw_reset(dsim);\n" - "+\ts5p_dsim_dp_dn_swap(dsim, dsim->dsim_info->e_lane_swap);\n" - "+\n" - "+\treturn 0;\n" - "+}\n" - "+\n" - "+int s5p_dsim_enable_frame_done_int(struct dsim_global *dsim, int enable)\n" - "+{\n" - "+\t/* enable only frame done interrupt */\n" - "+\ts5p_dsim_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable);\n" - "+\n" - "+\treturn 0;\n" - "+}\n" - "+\n" - "+int s5p_dsim_set_display_mode(struct dsim_global *dsim,\n" - "+\tstruct dsim_lcd_config *main_lcd, struct dsim_lcd_config *sub_lcd)\n" - "+{\n" - "+\tstruct fb_videomode *mlcd_video = NULL;\n" - "+\tstruct fb_cmdmode *mlcd_command = NULL;\n" - "+\tstruct s3c_fb_pd_win *pd;\n" - "+\tunsigned int width = 0, height = 0;\n" - "+\n" - "+\tif (dsim == NULL) {\n" - "+\t\tprintk(KERN_ERR \"dsim_global pointer is NULL.\\n\");\n" - "+\t\treturn -EFAULT;\n" - "+\t}\n" - "+\n" - "+\tpd = (struct s3c_fb_pd_win *)main_lcd->lcd_panel_info;\n" - "+\n" - "+\t/* in case of VIDEO MODE (RGB INTERFACE) */\n" - "+\tif (dsim->dsim_lcd_info->e_interface == (u32) DSIM_VIDEO) {\n" - "+\t\tmlcd_video = (struct fb_videomode *)&pd->win_mode;\n" - "+\t\twidth = mlcd_video->xres;\n" - "+\t\theight = mlcd_video->yres;\n" - "+\n" - "+\t\tif (dsim->dsim_info->auto_vertical_cnt == DSIM_FALSE) {\n" - "+\t\t\ts5p_dsim_set_main_disp_vporch(dsim,\n" - "+\t\t\t\tmlcd_video->upper_margin,\n" - "+\t\t\t\tmlcd_video->lower_margin, 0);\n" - "+\t\t\ts5p_dsim_set_main_disp_hporch(dsim,\n" - "+\t\t\t\tmlcd_video->left_margin,\n" - "+\t\t\t\tmlcd_video->right_margin);\n" - "+\t\t\ts5p_dsim_set_main_disp_sync_area(dsim,\n" - "+\t\t\t\tmlcd_video->vsync_len,\n" - "+\t\t\t\tmlcd_video->hsync_len);\n" - "+\t\t}\n" - "+\t} else {\t/* in case of COMMAND MODE (CPU or I80 INTERFACE) */\n" - "+\t\tmlcd_command = (struct fb_cmdmode *)&pd->cmd_mode;\n" - "+\t\twidth = mlcd_command->xres;\n" - "+\t\theight = mlcd_command->yres;\n" - "+\t}\n" - "+\n" - "+\ts5p_dsim_set_main_disp_resol(dsim, height, width);\n" - "+\n" - "+\tif (sub_lcd != NULL)\n" - "+\t\t\tdev_warn(dsim->dev, \"sub lcd isn't supported yet.\\n\");\n" - "+\n" - "+\ts5p_dsim_display_config(dsim, dsim->dsim_lcd_info, NULL);\n" - "+\n" - "+\treturn 0;\n" - "+}\n" - "+\n" - "+int s5p_dsim_init_link(struct dsim_global *dsim)\n" - "+{\n" - "+\tunsigned int time_out = 100;\n" - "+\n" - "+\tif (dsim == NULL) {\n" - "+\t\tprintk(KERN_ERR \"dsim_global pointer is NULL.\\n\");\n" - "+\t\treturn -EFAULT;\n" - "+\t}\n" - "+\n" - "+\tswitch (dsim->state) {\n" - "+\tcase DSIM_STATE_RESET:\n" - "+\t\ts5p_dsim_sw_reset(dsim);\n" - "+\tcase DSIM_STATE_INIT:\n" - "+\t\ts5p_dsim_init_fifo_pointer(dsim, 0x1f);\n" - "+\n" - "+\t\t/* dsi configuration */\n" - "+\t\ts5p_dsim_init_config(dsim, dsim->dsim_lcd_info,\n" - "+\t\t\tNULL, dsim->dsim_info);\n" - "+\t\ts5p_dsim_enable_lane(dsim, DSIM_LANE_CLOCK, 1);\n" - "+\t\ts5p_dsim_enable_lane(dsim, dsim->data_lane, 1);\n" - "+\n" - "+\t\t/* set clock configuration */\n" - "+\t\ts5p_dsim_set_clock(dsim, dsim->dsim_info->e_byte_clk,\n" - "+\t\t\t1);\n" - "+\n" - "+\t\t/* check clock and data lane state is stop state */\n" - "+\t\twhile (!(s5p_dsim_is_lane_state(dsim, DSIM_LANE_CLOCK)\n" - "+\t\t\t == DSIM_LANE_STATE_STOP) &&\n" - "+\t\t\t!(s5p_dsim_is_lane_state(dsim,\n" - "+\t\t\t\tdsim->data_lane) == DSIM_LANE_STATE_STOP)) {\n" - "+\t\t\ttime_out--;\n" - "+\t\t\tif (time_out == 0) {\n" - "+\t\t\t\tdev_info(dsim->dev,\n" - "+\t\t\t\t\t\"DSI Master is not stop state.\\n\");\n" - "+\t\t\t\tdev_info(dsim->dev,\n" - "+\t\t\t\t\t\"Check initialization process\\n\");\n" - "+\n" - "+\t\t\t\treturn -EINVAL;\n" - "+\t\t\t}\n" - "+\t\t}\n" - "+\n" - "+\t\tif (time_out != 0) {\n" - "+\t\t\tdev_info(dsim->dev,\n" - "+\t\t\t\t\"initialization of DSI Master is successful\\n\");\n" - "+\t\t\tdev_info(dsim->dev, \"DSI Master state is stop state\\n\");\n" - "+\t\t}\n" - "+\n" - "+\t\tdsim->state = DSIM_STATE_STOP;\n" - "+\n" - "+\t\t/* BTA sequence counters */\n" - "+\t\ts5p_dsim_set_stop_state_counter(dsim,\n" - "+\t\t\tdsim->dsim_info->stop_holding_cnt);\n" - "+\t\ts5p_dsim_set_bta_timeout(dsim,\n" - "+\t\t\tdsim->dsim_info->bta_timeout);\n" - "+\t\ts5p_dsim_set_lpdr_timeout(dsim,\n" - "+\t\t\tdsim->dsim_info->rx_timeout);\n" - "+\n" - "+\t\t/* default LPDT by both cpu and lcd controller */\n" - "+\t\ts5p_dsim_set_data_mode(dsim, DSIM_TRANSFER_BOTH,\n" - "+\t\t\tDSIM_STATE_STOP);\n" - "+\n" - "+\t\treturn 0;\n" - "+\tdefault:\n" - "+\t\tdev_info(dsim->dev, \"DSI Master is already init.\\n\");\n" - "+\t\treturn 0;\n" - "+\t}\n" - "+\n" - "+\treturn 0;\n" - "+}\n" - "+\n" - "+int s5p_dsim_set_hs_enable(struct dsim_global *dsim)\n" - "+{\n" - "+\tif (dsim == NULL) {\n" - "+\t\tprintk(KERN_ERR \"dsim_global pointer is NULL.\\n\");\n" - "+\t\treturn -EFAULT;\n" - "+\t}\n" - "+\n" - "+\tif (dsim->state == DSIM_STATE_STOP) {\n" - "+\t\tif (dsim->e_clk_src != DSIM_EXT_CLK_BYPASS) {\n" - "+\t\t\tdsim->state = DSIM_STATE_HSCLKEN;\n" - "+\t\t\ts5p_dsim_set_data_mode(dsim,\n" - "+\t\t\t\tDSIM_TRANSFER_BOTH, DSIM_STATE_HSCLKEN);\n" - "+\t\t\ts5p_dsim_enable_hs_clock(dsim, 1);\n" - "+\n" - "+\t\t\treturn 0;\n" - "+\t\t} else\n" - "+\t\t\tdev_warn(dsim->dev,\n" - "+\t\t\t\t\"clock source is external bypass.\\n\");\n" - "+\t} else\n" - "+\t\tdev_warn(dsim->dev, \"DSIM is not stop state.\\n\");\n" - "+\n" - "+\treturn 0;\n" - "+}\n" - "+\n" - "+int s5p_dsim_set_data_transfer_mode(struct dsim_global *dsim,\n" - "+\tunsigned char data_path, unsigned char hs_enable)\n" - "+{\n" - "+\tint ret = -1;\n" - "+\n" - "+\tif (dsim == NULL) {\n" - "+\t\tprintk(KERN_ERR \"dsim_global pointer is NULL.\\n\");\n" - "+\t\treturn -EFAULT;\n" - "+\t}\n" - "+\n" - "+\tif (hs_enable) {\n" - "+\t\tif (dsim->state == DSIM_STATE_HSCLKEN) {\n" - "+\t\t\ts5p_dsim_set_data_mode(dsim, data_path,\n" - "+\t\t\t\tDSIM_STATE_HSCLKEN);\n" - "+\t\t\tret = 0;\n" - "+\t\t} else {\n" - "+\t\t\tdev_err(dsim->dev, \"HS Clock lane is not enabled.\\n\");\n" - "+\t\t\tret = -EINVAL;\n" - "+\t\t}\n" - "+\t} else {\n" - "+\t\tif (dsim->state == DSIM_STATE_INIT || dsim->state ==\n" - "+\t\t\tDSIM_STATE_ULPS) {\n" - "+\t\t\tdev_err(dsim->dev,\n" - "+\t\t\t\t\"DSI Master is not STOP or HSDT state.\\n\");\n" - "+\t\t\tret = -EINVAL;\n" - "+\t\t} else {\n" - "+\t\t\ts5p_dsim_set_data_mode(dsim, data_path,\n" - "+\t\t\t\tDSIM_STATE_STOP);\n" - "+\t\t\tret = 0;\n" - "+\t\t}\n" - "+\t}\n" - "+\n" - "+\treturn ret;\n" - "+}\n" - "+\n" - "+int s5p_dsim_get_frame_done_status(void *dsim_data)\n" - "+{\n" - "+\tstruct dsim_global *dsim = NULL;\n" - "+\n" - "+\tdsim = (struct dsim_global *)dsim_data;\n" - "+\n" - "+\tif (dsim == NULL) {\n" - "+\t\tdev_err(dsim->dev, \"dsim_global pointer is NULL.\\n\");\n" - "+\t\treturn -EFAULT;\n" - "+\t}\n" - "+\n" - "+\treturn _s5p_dsim_get_frame_done_status(dsim);\n" - "+}\n" - "+\n" - "+int s5p_dsim_clear_frame_done(void *dsim_data)\n" - "+{\n" - "+\tstruct dsim_global *dsim = NULL;\n" - "+\n" - "+\tdsim = (struct dsim_global *)dsim_data;\n" - "+\n" - "+\tif (dsim == NULL) {\n" - "+\t\tdev_err(dsim->dev, \"dsim_global pointer is NULL.\\n\");\n" - "+\t\treturn -EFAULT;\n" - "+\t}\n" - "+\n" - "+\t_s5p_dsim_clear_frame_done(dsim);\n" - "+\n" - "+\treturn 0;\n" - "+}\n" - "+\n" - "+MODULE_AUTHOR(\"InKi Dae <a class=\"moz-txt-link-rfc2396E\" href=\"mailto:inki.dae@samsung.com\"><inki.dae@samsung.com></a>\");\n" - "+MODULE_DESCRIPTION(\"Samusung MIPI-DSIM common driver\");\n" - "+MODULE_LICENSE(\"GPL\");\n" - "diff --git a/drivers/video/s5p_dsim_common.h b/drivers/video/s5p_dsim_common.h\n" - "new file mode 100644\n" - "index 0000000..deefca1\n" - "--- /dev/null\n" - "+++ b/drivers/video/s5p_dsim_common.h\n" - "@@ -0,0 +1,38 @@\n" - "+/* linux/drivers/video/samsung/s5p_dsim_common.h\n" - "+ *\n" - "+ * Header file for Samsung MIPI-DSI common driver.\n" - "+ *\n" - "+ * Copyright (c) 2009 Samsung Electronics\n" - "+ * InKi Dae <a class=\"moz-txt-link-rfc2396E\" href=\"mailto:inki.dae@samsung.com\"><inki.dae@samsung.com></a>\n" - "+ *\n" - "+ * This program is free software; you can redistribute it and/or modify\n" - "+ * it under the terms of the GNU General Public License version 2 as\n" - "+ * published by the Free Software Foundation.\n" - "+*/\n" - "+\n" - "+#ifndef _S5P_DSIM_COMMON_H\n" - "+#define _S5P_DSIM_COMMON_H\n" - "+\n" - "+extern int s5p_dsim_wr_data(void *dsim_data, unsigned int data_id,\n" - "+\tunsigned int data0, unsigned int data1);\n" - "+extern int s5p_dsim_init_header_fifo(struct dsim_global *dsim);\n" - "+extern int s5p_dsim_pll_on(struct dsim_global *dsim, unsigned char enable);\n" - "+extern unsigned long s5p_dsim_change_pll(struct dsim_global *dsim,\n" - "+\tunsigned char pre_divider, unsigned short main_divider,\n" - "+\tunsigned char scaler);\n" - "+extern int s5p_dsim_set_clock(struct dsim_global *dsim,\n" - "+\tunsigned char byte_clk_sel, unsigned char enable);\n" - "+extern int s5p_dsim_init_dsim(struct dsim_global *dsim);\n" - "+extern int s5p_dsim_set_display_mode(struct dsim_global *dsim,\n" - "+\tstruct dsim_lcd_config *main_lcd, struct dsim_lcd_config *sub_lcd);\n" - "+extern int s5p_dsim_init_link(struct dsim_global *dsim);\n" - "+extern int s5p_dsim_set_hs_enable(struct dsim_global *dsim);\n" - "+extern int s5p_dsim_set_data_transfer_mode(struct dsim_global *dsim,\n" - "+\tunsigned char data_path, unsigned char hs_enable);\n" - "+extern int s5p_dsim_get_frame_done_status(void *dsim_data);\n" - "+extern int s5p_dsim_clear_frame_done(void *dsim_data);\n" - "+extern int s5p_dsim_enable_frame_done_int(struct dsim_global *dsim, int enable);\n" - "+\n" - "+extern struct fb_info *registered_fb[FB_MAX] __read_mostly;\n" - "+\n" - "+#endif /* _S5P_DSIM_COMMON_H */\n" - "diff --git a/drivers/video/s5p_dsim_lowlevel.c b/drivers/video/s5p_dsim_lowlevel.c\n" - "new file mode 100644\n" - "index 0000000..6a27395\n" - "--- /dev/null\n" - "+++ b/drivers/video/s5p_dsim_lowlevel.c\n" - "@@ -0,0 +1,562 @@\n" - "+/* linux/drivers/video/samsung/s5p-dsim.c\n" - "+ *\n" - "+ * Samsung MIPI-DSIM lowlevel driver.\n" - "+ *\n" - "+ * InKi Dae, <a class=\"moz-txt-link-rfc2396E\" href=\"mailto:inki.dae@samsung.com\"><inki.dae@samsung.com></a>\n" - "+ *\n" - "+ * This program is free software; you can redistribute it and/or modify\n" - "+ * it under the terms of the GNU General Public License version 2 as\n" - "+ * published by the Free Software Foundation.\n" - "+*/\n" - "+\n" - "+#include <linux/module.h>\n" - "+#include <linux/kernel.h>\n" - "+#include <linux/errno.h>\n" - "+#include <linux/mutex.h>\n" - "+#include <linux/wait.h>\n" - "+#include <linux/delay.h>\n" - "+#include <linux/fs.h>\n" - "+#include <linux/mm.h>\n" - "+#include <linux/ctype.h>\n" - "+#include <linux/io.h>\n" - "+\n" - "+#include <mach/map.h>\n" - "+\n" - "+#include <plat/dsim.h>\n" - "+#include <plat/mipi_ddi.h>\n" - "+#include <plat/regs-dsim.h>\n" - "+\n" - "+void s5p_dsim_func_reset(struct dsim_global *dsim)\n" - "+{\n" - "+\tunsigned int cfg = 0;\n" - "+\n" - "+\tcfg = DSIM_FUNCRST;\n" - "+\n" - "+\twritel(cfg, dsim->reg_base + S5P_DSIM_SWRST);\n" - "+}\n" - "+\n" - "+void s5p_dsim_sw_reset(struct dsim_global *dsim)\n" - "+{\n" - "+\tunsigned int cfg = 0;\n" - "+\n" - "+\tcfg = DSIM_SWRST;\n" - "+\n" - "+\twritel(cfg, dsim->reg_base + S5P_DSIM_SWRST);\n" - "+}\n" - "+\n" - "+void s5p_dsim_set_interrupt_mask(struct dsim_global *dsim, unsigned int mode,\n" - "+\tunsigned int mask)\n" - "+{\n" - "+\tunsigned int reg = readl(dsim->reg_base + S5P_DSIM_INTMSK);\n" - "+\n" - "+\tif (mask)\n" - "+\t\treg |= mode;\n" - "+\telse\n" - "+\t\treg &= ~(mode);\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_INTMSK);\n" - "+}\n" - "+\n" - "+void s5p_dsim_init_fifo_pointer(struct dsim_global *dsim, unsigned char cfg)\n" - "+{\n" - "+\tunsigned int reg;\n" - "+\n" - "+\treg = readl(dsim->reg_base + S5P_DSIM_FIFOCTRL);\n" - "+\n" - "+\twritel(reg & ~(cfg), dsim->reg_base + S5P_DSIM_FIFOCTRL);\n" - "+\tmdelay(10);\n" - "+\treg |= cfg;\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_FIFOCTRL);\n" - "+}\n" - "+\n" - "+/*\n" - "+ * this function set PLL P, M and S value in D-PHY\n" - "+ */\n" - "+void s5p_dsim_set_phy_tunning(struct dsim_global *dsim, unsigned int value)\n" - "+{\n" - "+\twritel(DSIM_AFC_CTL(value), dsim->reg_base + S5P_DSIM_PHYACCHR);\n" - "+}\n" - "+\n" - "+void s5p_dsim_set_main_disp_resol(struct dsim_global *dsim,\n" - "+\tunsigned short vert_resol, unsigned short hori_resol)\n" - "+{\n" - "+\tunsigned int reg;\n" - "+\n" - "+\t/* standby should be set after configuration so set to not ready*/\n" - "+\treg = (readl(dsim->reg_base + S5P_DSIM_MDRESOL)) &\n" - "+\t\t~(DSIM_MAIN_STAND_BY);\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_MDRESOL);\n" - "+\n" - "+\treg &= ~(0x7ff << 16) & ~(0x7ff << 0);\n" - "+\treg |= DSIM_MAIN_VRESOL(vert_resol) | DSIM_MAIN_HRESOL(hori_resol);\n" - "+\n" - "+\treg |= DSIM_MAIN_STAND_BY;\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_MDRESOL);\n" - "+}\n" - "+\n" - "+void s5p_dsim_set_main_disp_vporch(struct dsim_global *dsim,\n" - "+\tunsigned int cmd_allow, unsigned int vfront, unsigned int vback)\n" - "+{\n" - "+\tunsigned int reg;\n" - "+\n" - "+\treg = (readl(dsim->reg_base + S5P_DSIM_MVPORCH)) &\n" - "+\t\t~(DSIM_CMD_ALLOW_MASK) & ~(DSIM_STABLE_VFP_MASK) &\n" - "+\t\t~(DSIM_MAIN_VBP_MASK);\n" - "+\n" - "+\treg |= ((cmd_allow & 0xf) << DSIM_CMD_ALLOW_SHIFT) |\n" - "+\t\t((vfront & 0x7ff) << DSIM_STABLE_VFP_SHIFT) |\n" - "+\t\t((vback & 0x7ff) << DSIM_MAIN_VBP_SHIFT);\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_MVPORCH);\n" - "+}\n" - "+\n" - "+void s5p_dsim_set_main_disp_hporch(struct dsim_global *dsim,\n" - "+\tunsigned short front, unsigned short back)\n" - "+{\n" - "+\tunsigned int reg;\n" - "+\n" - "+\treg = (readl(dsim->reg_base + S5P_DSIM_MHPORCH)) &\n" - "+\t\t~(DSIM_MAIN_HFP_MASK) & ~(DSIM_MAIN_HBP_MASK);\n" - "+\n" - "+\treg |= (front << DSIM_MAIN_HFP_SHIFT) | (back << DSIM_MAIN_HBP_SHIFT);\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_MHPORCH);\n" - "+}\n" - "+\n" - "+void s5p_dsim_set_main_disp_sync_area(struct dsim_global *dsim,\n" - "+\tunsigned short vert, unsigned short hori)\n" - "+{\n" - "+\tunsigned int reg;\n" - "+\n" - "+\treg = (readl(dsim->reg_base + S5P_DSIM_MSYNC)) &\n" - "+\t\t~(DSIM_MAIN_VSA_MASK) & ~(DSIM_MAIN_HSA_MASK);\n" - "+\n" - "+\treg |= ((vert & 0x3ff) << DSIM_MAIN_VSA_SHIFT) |\n" - "+\t\t(hori << DSIM_MAIN_HSA_SHIFT);\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_MSYNC);\n" - "+}\n" - "+\n" - "+void s5p_dsim_set_sub_disp_resol(struct dsim_global *dsim,\n" - "+\tunsigned short vert, unsigned short hori)\n" - "+{\n" - "+\tunsigned int reg;\n" - "+\n" - "+\treg = (readl(dsim->reg_base + S5P_DSIM_SDRESOL)) &\n" - "+\t\t~(DSIM_SUB_STANDY_MASK);\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_SDRESOL);\n" - "+\n" - "+\treg &= ~(DSIM_SUB_VRESOL_MASK) | ~(DSIM_SUB_HRESOL_MASK);\n" - "+\treg |= ((vert & 0x7ff) << DSIM_SUB_VRESOL_SHIFT) |\n" - "+\t\t((hori & 0x7ff) << DSIM_SUB_HRESOL_SHIFT);\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_SDRESOL);\n" - "+\n" - "+\treg |= (1 << DSIM_SUB_STANDY_SHIFT);\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_SDRESOL);\n" - "+}\n" - "+\n" - "+void s5p_dsim_init_config(struct dsim_global *dsim,\n" - "+\tstruct dsim_lcd_config *main_lcd_info,\n" - "+\tstruct dsim_lcd_config *sub_lcd_info, struct dsim_config *dsim_info)\n" - "+{\n" - "+\tunsigned int cfg = (readl(dsim->reg_base + S5P_DSIM_CONFIG)) &\n" - "+\t\t~(1 << 28) & ~(0x1f << 20) & ~(0x3 << 5);\n" - "+\n" - "+\tcfg =\t(dsim_info->auto_flush << 29) |\n" - "+\t\t(dsim_info->eot_disable << 28) |\n" - "+\t\t(dsim_info->auto_vertical_cnt << DSIM_AUTO_MODE_SHIFT) |\n" - "+\t\t(dsim_info->hse << DSIM_HSE_MODE_SHIFT) |\n" - "+\t\t(dsim_info->hfp << DSIM_HFP_MODE_SHIFT) |\n" - "+\t\t(dsim_info->hbp << DSIM_HBP_MODE_SHIFT) |\n" - "+\t\t(dsim_info->hsa << DSIM_HSA_MODE_SHIFT) |\n" - "+\t\t(dsim_info->e_no_data_lane << DSIM_NUM_OF_DATALANE_SHIFT);\n" - "+\n" - "+\twritel(cfg, dsim->reg_base + S5P_DSIM_CONFIG);\n" - "+}\n" - "+\n" - "+void s5p_dsim_display_config(struct dsim_global *dsim,\n" - "+\tstruct dsim_lcd_config *main_lcd, struct dsim_lcd_config *sub_lcd)\n" - "+{\n" - "+\tu32 reg = (readl(dsim->reg_base + S5P_DSIM_CONFIG)) &\n" - "+\t\t~(0x3 << 26) & ~(1 << 25) & ~(0x3 << 18) & ~(0x7 << 12) &\n" - "+\t\t~(0x3 << 16) & ~(0x7 << 8);\n" - "+\n" - "+\tif (main_lcd->e_interface == DSIM_VIDEO)\n" - "+\t\treg |= (1 << 25);\n" - "+\telse if (main_lcd->e_interface == DSIM_COMMAND)\n" - "+\t\treg &= ~(1 << 25);\n" - "+\telse {\n" - "+\t\tdev_err(dsim->dev, \"this ddi is not MIPI interface.\\n\");\n" - "+\t\treturn;\n" - "+\t}\n" - "+\n" - "+\t/* main lcd */\n" - "+\treg |= ((u8) (main_lcd->parameter[DSI_VIDEO_MODE_SEL]) & 0x3) << 26 |\n" - "+\t\t((u8) (main_lcd->parameter[DSI_VIRTUAL_CH_ID]) & 0x3) << 18 |\n" - "+\t\t((u8) (main_lcd->parameter[DSI_FORMAT]) & 0x7) << 12;\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_CONFIG);\n" - "+}\n" - "+\n" - "+void s5p_dsim_enable_lane(struct dsim_global *dsim, unsigned char lane,\n" - "+\tunsigned char enable)\n" - "+{\n" - "+\tunsigned int reg;\n" - "+\n" - "+\treg = readl(dsim->reg_base + S5P_DSIM_CONFIG);\n" - "+\n" - "+\tif (lane == DSIM_LANE_CLOCK) {\n" - "+\t\tif (enable)\n" - "+\t\t\treg |= (1 << 0);\n" - "+\t\telse\n" - "+\t\t\treg &= ~(1 << 0);\n" - "+\t} else {\n" - "+\t\tif (enable)\n" - "+\t\t\treg |= (lane << 1);\n" - "+\t\telse\n" - "+\t\t\treg &= ~(lane << 1);\n" - "+\t}\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_CONFIG);\n" - "+}\n" - "+\n" - "+\n" - "+void s5p_dsim_set_data_lane_number(struct dsim_global *dsim,\n" - "+\tunsigned char count)\n" - "+{\n" - "+\tunsigned int cfg = 0;\n" - "+\n" - "+\t/* get the data lane number. */\n" - "+\tcfg = DSIM_NUM_OF_DATA_LANE(count);\n" - "+\n" - "+\twritel(cfg, dsim->reg_base + S5P_DSIM_CONFIG);\n" - "+}\n" - "+\n" - "+void s5p_dsim_enable_afc(struct dsim_global *dsim, unsigned char enable,\n" - "+\tunsigned char afc_code)\n" - "+{\n" - "+\tunsigned int reg = readl(dsim->reg_base + S5P_DSIM_PHYACCHR);\n" - "+\n" - "+\tif (enable) {\n" - "+\t\treg |= (1 << 14);\n" - "+\t\treg &= ~(0x7 << 5);\n" - "+\t\treg |= (afc_code & 0x7) << 5;\n" - "+\t} else\n" - "+\t\treg &= ~(1 << 14);\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_PHYACCHR);\n" - "+}\n" - "+\n" - "+void s5p_dsim_enable_pll_bypass(struct dsim_global *dsim,\n" - "+\tunsigned char enable)\n" - "+{\n" - "+\tunsigned int reg = (readl(dsim->reg_base + S5P_DSIM_CLKCTRL)) &\n" - "+\t\t~(DSIM_PLL_BYPASS_EXTERNAL);\n" - "+\n" - "+\treg |= enable << DSIM_PLL_BYPASS_SHIFT;\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL);\n" - "+}\n" - "+\n" - "+void s5p_dsim_set_pll_pms(struct dsim_global *dsim, unsigned char p,\n" - "+\tunsigned short m, unsigned short s)\n" - "+{\n" - "+\tunsigned int reg = readl(dsim->reg_base + S5P_DSIM_PLLCTRL);\n" - "+\n" - "+\treg |= ((p & 0x3f) << 13) | ((m & 0x1ff) << 4) | ((s & 0x7) << 1);\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL);\n" - "+}\n" - "+\n" - "+void s5p_dsim_pll_freq_band(struct dsim_global *dsim, unsigned char freq_band)\n" - "+{\n" - "+\tunsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) &\n" - "+\t\t~(0x1f << DSIM_FREQ_BAND_SHIFT);\n" - "+\n" - "+\treg |= ((freq_band & 0x1f) << DSIM_FREQ_BAND_SHIFT);\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL);\n" - "+}\n" - "+\n" - "+void s5p_dsim_pll_freq(struct dsim_global *dsim, unsigned char pre_divider,\n" - "+\tunsigned short main_divider, unsigned char scaler)\n" - "+{\n" - "+\tunsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) &\n" - "+\t\t~(0x7ffff << 1);\n" - "+\n" - "+\treg |= (pre_divider & 0x3f) << 13 | (main_divider & 0x1ff) << 4 |\n" - "+\t\t(scaler & 0x7) << 1;\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL);\n" - "+}\n" - "+\n" - "+void s5p_dsim_pll_stable_time(struct dsim_global *dsim,\n" - "+\tunsigned int lock_time)\n" - "+{\n" - "+\twritel(lock_time, dsim->reg_base + S5P_DSIM_PLLTMR);\n" - "+}\n" - "+\n" - "+void s5p_dsim_enable_pll(struct dsim_global *dsim, unsigned char enable)\n" - "+{\n" - "+\tunsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) &\n" - "+\t\t~(0x1 << DSIM_PLL_EN_SHIFT);\n" - "+\n" - "+\treg |= ((enable & 0x1) << DSIM_PLL_EN_SHIFT);\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL);\n" - "+}\n" - "+\n" - "+void s5p_dsim_set_byte_clock_src(struct dsim_global *dsim, unsigned char src)\n" - "+{\n" - "+\tunsigned int reg = (readl(dsim->reg_base + S5P_DSIM_CLKCTRL)) &\n" - "+\t\t~(0x3 << DSIM_BYTE_CLK_SRC_SHIFT);\n" - "+\n" - "+\treg |= ((unsigned int) src) << DSIM_BYTE_CLK_SRC_SHIFT;\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL);\n" - "+}\n" - "+\n" - "+void s5p_dsim_enable_byte_clock(struct dsim_global *dsim,\n" - "+\tunsigned char enable)\n" - "+{\n" - "+\tunsigned int reg = (readl(dsim->reg_base + S5P_DSIM_CLKCTRL)) &\n" - "+\t\t~(1 << DSIM_BYTE_CLKEN_SHIFT);\n" - "+\n" - "+\treg |= enable << DSIM_BYTE_CLKEN_SHIFT;\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL);\n" - "+}\n" - "+\n" - "+void s5p_dsim_set_esc_clk_prs(struct dsim_global *dsim, unsigned char enable,\n" - "+\tunsigned short prs_val)\n" - "+{\n" - "+\tunsigned int reg = (readl(dsim->reg_base + S5P_DSIM_CLKCTRL)) &\n" - "+\t\t~(1 << DSIM_ESC_CLKEN_SHIFT) & ~(0xffff);\n" - "+\n" - "+\treg |= enable << DSIM_ESC_CLKEN_SHIFT;\n" - "+\tif (enable)\n" - "+\t\treg |= prs_val;\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL);\n" - "+}\n" - "+\n" - "+void s5p_dsim_enable_esc_clk_on_lane(struct dsim_global *dsim,\n" - "+\tunsigned char lane_sel, unsigned char enable)\n" - "+{\n" - "+\tunsigned int reg = readl(dsim->reg_base + S5P_DSIM_CLKCTRL);\n" - "+\n" - "+\tif (enable) {\n" - "+\t\tif (lane_sel & DSIM_LANE_CLOCK)\n" - "+\t\t\treg |= 1 << DSIM_LANE_ESC_CLKEN_SHIFT;\n" - "+\t\tif (lane_sel & DSIM_LANE_DATA0)\n" - "+\t\t\treg |= 1 << (DSIM_LANE_ESC_CLKEN_SHIFT + 1);\n" - "+\t\tif (lane_sel & DSIM_LANE_DATA1)\n" - "+\t\t\treg |= 1 << (DSIM_LANE_ESC_CLKEN_SHIFT + 2);\n" - "+\t\tif (lane_sel & DSIM_LANE_DATA2)\n" - "+\t\t\treg |= 1 << (DSIM_LANE_ESC_CLKEN_SHIFT + 3);\n" - "+\t\tif (lane_sel & DSIM_LANE_DATA2)\n" - "+\t\t\treg |= 1 << (DSIM_LANE_ESC_CLKEN_SHIFT + 4);\n" - "+\t} else {\n" - "+\t\tif (lane_sel & DSIM_LANE_CLOCK)\n" - "+\t\t\treg &= ~(1 << DSIM_LANE_ESC_CLKEN_SHIFT);\n" - "+\t\tif (lane_sel & DSIM_LANE_DATA0)\n" - "+\t\t\treg &= ~(1 << (DSIM_LANE_ESC_CLKEN_SHIFT + 1));\n" - "+\t\tif (lane_sel & DSIM_LANE_DATA1)\n" - "+\t\t\treg &= ~(1 << (DSIM_LANE_ESC_CLKEN_SHIFT + 2));\n" - "+\t\tif (lane_sel & DSIM_LANE_DATA2)\n" - "+\t\t\treg &= ~(1 << (DSIM_LANE_ESC_CLKEN_SHIFT + 3));\n" - "+\t\tif (lane_sel & DSIM_LANE_DATA2)\n" - "+\t\t\treg &= ~(1 << (DSIM_LANE_ESC_CLKEN_SHIFT + 4));\n" - "+\t}\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL);\n" - "+}\n" - "+\n" - "+void s5p_dsim_force_dphy_stop_state(struct dsim_global *dsim,\n" - "+\tunsigned char enable)\n" - "+{\n" - "+\tunsigned int reg = (readl(dsim->reg_base + S5P_DSIM_ESCMODE)) &\n" - "+\t\t~(0x1 << DSIM_FORCE_STOP_STATE_SHIFT);\n" - "+\n" - "+\treg |= ((enable & 0x1) << DSIM_FORCE_STOP_STATE_SHIFT);\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_ESCMODE);\n" - "+}\n" - "+\n" - "+unsigned char s5p_dsim_is_lane_state(struct dsim_global *dsim,\n" - "+\tunsigned char lane)\n" - "+{\n" - "+\tunsigned int reg = readl(dsim->reg_base + S5P_DSIM_STATUS);\n" - "+\n" - "+\tif ((lane & DSIM_LANE_ALL) > DSIM_LANE_CLOCK) { /* all lane state */\n" - "+\t\tif ((reg & 0x7ff) ^ (((lane & 0xf) << 4) | (1 << 9)))\n" - "+\t\t\treturn DSIM_LANE_STATE_ULPS;\n" - "+\t\telse if ((reg & 0x7ff) ^ (((lane & 0xf) << 0) | (1 << 8)))\n" - "+\t\t\treturn DSIM_LANE_STATE_STOP;\n" - "+\t\telse {\n" - "+\t\t\tdev_err(dsim->dev, \"land state is unknown.\\n\");\n" - "+\t\t\treturn -1;\n" - "+\t\t}\n" - "+\t} else if (lane & DSIM_LANE_DATA_ALL) {\t/* data lane */\n" - "+\t\tif (reg & (lane << 4))\n" - "+\t\t\treturn DSIM_LANE_STATE_ULPS;\n" - "+\t\telse if (reg & (lane << 0))\n" - "+\t\t\treturn DSIM_LANE_STATE_STOP;\n" - "+\t\telse {\n" - "+\t\t\tdev_err(dsim->dev, \"data lane state is unknown.\\n\");\n" - "+\t\t\treturn -1;\n" - "+\t\t}\n" - "+\t} else if (lane & DSIM_LANE_CLOCK) { /* clock lane */\n" - "+\t\tif (reg & (1 << 9))\n" - "+\t\t\treturn DSIM_LANE_STATE_ULPS;\n" - "+\t\telse if (reg & (1 << 8))\n" - "+\t\t\treturn DSIM_LANE_STATE_STOP;\n" - "+\t\telse if (reg & (1 << 10))\n" - "+\t\t\treturn DSIM_LANE_STATE_HS_READY;\n" - "+\t\telse {\n" - "+\t\t\tdev_err(dsim->dev, \"data lane state is unknown.\\n\");\n" - "+\t\t\treturn -1;\n" - "+\t\t}\n" - "+\t}\n" - "+\n" - "+\treturn 0;\n" - "+}\n" - "+\n" - "+void s5p_dsim_set_stop_state_counter(struct dsim_global *dsim,\n" - "+\tunsigned short cnt_val)\n" - "+{\n" - "+\tunsigned int reg = (readl(dsim->reg_base + S5P_DSIM_ESCMODE)) &\n" - "+\t\t~(0x7ff << DSIM_STOP_STATE_CNT_SHIFT);\n" - "+\n" - "+\treg |= ((cnt_val & 0x7ff) << DSIM_STOP_STATE_CNT_SHIFT);\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_ESCMODE);\n" - "+}\n" - "+\n" - "+void s5p_dsim_set_bta_timeout(struct dsim_global *dsim, unsigned char timeout)\n" - "+{\n" - "+\tunsigned int reg = (readl(dsim->reg_base + S5P_DSIM_TIMEOUT)) &\n" - "+\t\t~(0xff << DSIM_BTA_TOUT_SHIFT);\n" - "+\n" - "+\treg |= (timeout << DSIM_BTA_TOUT_SHIFT);\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_TIMEOUT);\n" - "+}\n" - "+\n" - "+void s5p_dsim_set_lpdr_timeout(struct dsim_global *dsim,\n" - "+\tunsigned short timeout)\n" - "+{\n" - "+\tunsigned int reg = (readl(dsim->reg_base + S5P_DSIM_TIMEOUT)) &\n" - "+\t\t~(0xffff << DSIM_LPDR_TOUT_SHIFT);\n" - "+\n" - "+\treg |= (timeout << DSIM_LPDR_TOUT_SHIFT);\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_TIMEOUT);\n" - "+}\n" - "+\n" - "+void s5p_dsim_set_data_mode(struct dsim_global *dsim, unsigned char data,\n" - "+\tunsigned char state)\n" - "+{\n" - "+\tunsigned int reg = readl(dsim->reg_base + S5P_DSIM_ESCMODE);\n" - "+\n" - "+\tif (state == DSIM_STATE_HSCLKEN)\n" - "+\t\treg &= ~data;\n" - "+\telse\n" - "+\t\treg |= data;\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_ESCMODE);\n" - "+}\n" - "+\n" - "+void s5p_dsim_enable_hs_clock(struct dsim_global *dsim, unsigned char enable)\n" - "+{\n" - "+\tunsigned int reg = (readl(dsim->reg_base + S5P_DSIM_CLKCTRL)) &\n" - "+\t\t~(1 << DSIM_TX_REQUEST_HSCLK_SHIFT);\n" - "+\n" - "+\treg |= enable << DSIM_TX_REQUEST_HSCLK_SHIFT;\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL);\n" - "+}\n" - "+\n" - "+void s5p_dsim_dp_dn_swap(struct dsim_global *dsim, unsigned char swap_en)\n" - "+{\n" - "+\tunsigned int reg = readl(dsim->reg_base + S5P_DSIM_PHYACCHR1);\n" - "+\n" - "+\treg &= ~(0x3 << 0);\n" - "+\treg |= (swap_en & 0x3) << 0;\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_PHYACCHR1);\n" - "+}\n" - "+\n" - "+void s5p_dsim_hs_zero_ctrl(struct dsim_global *dsim, unsigned char hs_zero)\n" - "+{\n" - "+\tunsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) &\n" - "+\t\t~(0xf << 28);\n" - "+\n" - "+\treg |= ((hs_zero & 0xf) << 28);\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL);\n" - "+}\n" - "+\n" - "+void s5p_dsim_prep_ctrl(struct dsim_global *dsim, unsigned char prep)\n" - "+{\n" - "+\tunsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) &\n" - "+\t\t~(0x7 << 20);\n" - "+\n" - "+\treg |= ((prep & 0x7) << 20);\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL);\n" - "+}\n" - "+\n" - "+void s5p_dsim_clear_interrupt(struct dsim_global *dsim, unsigned int int_src)\n" - "+{\n" - "+\tunsigned int reg = readl(dsim->reg_base + S5P_DSIM_INTSRC);\n" - "+\n" - "+\treg |= int_src;\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_INTSRC);\n" - "+}\n" - "+\n" - "+unsigned char s5p_dsim_is_pll_stable(struct dsim_global *dsim)\n" - "+{\n" - "+\treturn (unsigned char) ((readl(dsim->reg_base + S5P_DSIM_STATUS) &\n" - "+\t\t (1 << 31)) >> 31);\n" - "+}\n" - "+\n" - "+unsigned int s5p_dsim_get_fifo_state(struct dsim_global *dsim)\n" - "+{\n" - "+\tunsigned int ret = 0;\n" - "+\n" - "+\tret = (readl(dsim->reg_base + S5P_DSIM_FIFOCTRL) & ~(0x1f));\n" - "+\n" - "+\treturn ret;\n" - "+}\n" - "+\n" - "+void s5p_dsim_wr_tx_header(struct dsim_global *dsim,\n" - "+\tunsigned char di, unsigned char data0, unsigned char data1)\n" - "+{\n" - "+\tunsigned int reg = (data1 << 16) | (data0 << 8) | ((di & 0x3f) << 0);\n" - "+\n" - "+\twritel(reg, dsim->reg_base + S5P_DSIM_PKTHDR);\n" - "+}\n" - "+\n" - "+unsigned int _s5p_dsim_get_frame_done_status(struct dsim_global *dsim)\n" - "+{\n" - "+\tunsigned int reg = readl(dsim->reg_base + S5P_DSIM_INTSRC);\n" - "+\n" - "+\treturn (reg & INTSRC_FRAME_DONE) ? 1 : 0;\n" - "+}\n" - "+\n" - "+void _s5p_dsim_clear_frame_done(struct dsim_global *dsim)\n" - "+{\n" - "+\tunsigned int reg = readl(dsim->reg_base + S5P_DSIM_INTSRC);\n" - "+\n" - "+\twritel(reg | INTSRC_FRAME_DONE, dsim->reg_base +\n" - "+\t\tS5P_DSIM_INTSRC);\n" - "+}\n" - "+\n" - "+void s5p_dsim_wr_tx_data(struct dsim_global *dsim, unsigned int tx_data)\n" - "+{\n" - "+\twritel(tx_data, dsim->reg_base + S5P_DSIM_PAYLOAD);\n" - "+}\n" - "diff --git a/drivers/video/s5p_dsim_lowlevel.h b/drivers/video/s5p_dsim_lowlevel.h\n" - "new file mode 100644\n" - "index 0000000..ff950ba\n" - "--- /dev/null\n" - "+++ b/drivers/video/s5p_dsim_lowlevel.h\n" - "@@ -0,0 +1,101 @@\n" - "+/* linux/drivers/video/samsung/s5p_dsim_lowlevel.h\n" - "+ *\n" - "+ * Header file for Samsung MIPI-DSIM lowlevel driver.\n" - "+ *\n" - "+ * Copyright (c) 2009 Samsung Electronics\n" - "+ * InKi Dae <a class=\"moz-txt-link-rfc2396E\" href=\"mailto:inki.dae@samsung.com\"><inki.dae@samsung.com></a>\n" - "+ *\n" - "+ * This program is free software; you can redistribute it and/or modify\n" - "+ * it under the terms of the GNU General Public License version 2 as\n" - "+ * published by the Free Software Foundation.\n" - "+*/\n" - "+\n" - "+#ifndef _S5P_DSIM_LOWLEVEL_H\n" - "+#define _S5P_DSIM_LOWLEVEL_H\n" - "+\n" - "+struct dsim_global;\n" - "+\n" - "+extern void s5p_dsim_func_reset(struct dsim_global *dsim);\n" - "+extern void s5p_dsim_sw_reset(struct dsim_global *dsim);\n" - "+extern void s5p_dsim_set_interrupt_mask(struct dsim_global *dsim,\n" - "+\tunsigned int mode, unsigned int mask);\n" - "+extern void s5p_dsim_set_data_lane_number(struct dsim_global *dsim,\n" - "+\tunsigned char count);\n" - "+extern void s5p_dsim_init_fifo_pointer(struct dsim_global *dsim,\n" - "+\tunsigned char cfg);\n" - "+extern void s5p_dsim_set_phy_tunning(struct dsim_global *dsim,\n" - "+\tunsigned int value);\n" - "+extern void s5p_dsim_set_phy_tunning(struct dsim_global *dsim,\n" - "+\tunsigned int value);\n" - "+extern void s5p_dsim_set_main_disp_resol(struct dsim_global *dsim,\n" - "+\tunsigned short vert_resol, unsigned short hori_resol);\n" - "+extern void s5p_dsim_set_main_disp_vporch(struct dsim_global *dsim,\n" - "+\tunsigned short cmd_allow, unsigned short vfront, unsigned short vback);\n" - "+extern void s5p_dsim_set_main_disp_hporch(struct dsim_global *dsim,\n" - "+\tunsigned short front, unsigned short back);\n" - "+extern void s5p_dsim_set_main_disp_sync_area(struct dsim_global *dsim,\n" - "+\tunsigned short vert, unsigned short hori);\n" - "+extern void s5p_dsim_set_sub_disp_resol(struct dsim_global *dsim,\n" - "+\tunsigned short vert, unsigned short hori);\n" - "+extern void s5p_dsim_init_config(struct dsim_global *dsim,\n" - "+\tstruct dsim_lcd_config *main_lcd_info,\n" - "+\tstruct dsim_lcd_config *sub_lcd_info, struct dsim_config *dsim_info);\n" - "+extern void s5p_dsim_display_config(struct dsim_global *dsim,\n" - "+\tstruct dsim_lcd_config *main_lcd, struct dsim_lcd_config *sub_lcd);\n" - "+extern void s5p_dsim_set_data_lane_number(struct dsim_global *dsim,\n" - "+\tunsigned char count);\n" - "+extern void s5p_dsim_enable_lane(struct dsim_global *dsim, unsigned char lane,\n" - "+\tunsigned char enable);\n" - "+extern void s5p_dsim_enable_afc(struct dsim_global *dsim, unsigned char enable,\n" - "+\tunsigned char afc_code);\n" - "+extern void s5p_dsim_enable_pll_bypass(struct dsim_global *dsim,\n" - "+\tunsigned char enable);\n" - "+extern void s5p_dsim_set_pll_pms(struct dsim_global *dsim, unsigned char p,\n" - "+\tunsigned short m, unsigned short s);\n" - "+extern void s5p_dsim_pll_freq_band(struct dsim_global *dsim,\n" - "+\tunsigned char freq_band);\n" - "+extern void s5p_dsim_pll_freq(struct dsim_global *dsim,\n" - "+\tunsigned char pre_divider, unsigned short main_divider,\n" - "+\tunsigned char scaler);\n" - "+extern void s5p_dsim_pll_stable_time(struct dsim_global *dsim,\n" - "+\tunsigned int lock_time);\n" - "+extern void s5p_dsim_enable_pll(struct dsim_global *dsim,\n" - "+\tunsigned char enable);\n" - "+extern void s5p_dsim_set_byte_clock_src(struct dsim_global *dsim,\n" - "+\tunsigned char src);\n" - "+extern void s5p_dsim_enable_byte_clock(struct dsim_global *dsim,\n" - "+\tunsigned char enable);\n" - "+extern void s5p_dsim_set_esc_clk_prs(struct dsim_global *dsim,\n" - "+\tunsigned char enable, unsigned short prs_val);\n" - "+extern void s5p_dsim_enable_esc_clk_on_lane(struct dsim_global *dsim,\n" - "+\tunsigned char lane_sel, unsigned char enable);\n" - "+extern void s5p_dsim_force_dphy_stop_state(struct dsim_global *dsim,\n" - "+\tunsigned char enable);\n" - "+extern unsigned char s5p_dsim_is_lane_state(struct dsim_global *dsim,\n" - "+\tunsigned char lane);\n" - "+extern void s5p_dsim_set_stop_state_counter(struct dsim_global *dsim,\n" - "+\tunsigned short cnt_val);\n" - "+extern void s5p_dsim_set_bta_timeout(struct dsim_global *dsim,\n" - "+\tunsigned char timeout);\n" - "+extern void s5p_dsim_set_lpdr_timeout(struct dsim_global *dsim,\n" - "+\tunsigned short timeout);\n" - "+extern void s5p_dsim_set_data_mode(struct dsim_global *dsim,\n" - "+\tunsigned char data, unsigned char state);\n" - "+extern void s5p_dsim_enable_hs_clock(struct dsim_global *dsim,\n" - "+\tunsigned char enable);\n" - "+extern void s5p_dsim_dp_dn_swap(struct dsim_global *dsim,\n" - "+\tunsigned char swap_en);\n" - "+extern void s5p_dsim_hs_zero_ctrl(struct dsim_global *dsim,\n" - "+\tunsigned char hs_zero);\n" - "+extern void s5p_dsim_prep_ctrl(struct dsim_global *dsim, unsigned char prep);\n" - "+extern void s5p_dsim_clear_interrupt(struct dsim_global *dsim,\n" - "+\tunsigned int int_src);\n" - "+extern unsigned char s5p_dsim_is_pll_stable(struct dsim_global *dsim);\n" - "+extern unsigned int s5p_dsim_get_fifo_state(struct dsim_global *dsim);\n" - "+extern unsigned int _s5p_dsim_get_frame_done_status(struct dsim_global *dsim);\n" - "+extern void _s5p_dsim_clear_frame_done(struct dsim_global *dsim);\n" - "+extern void s5p_dsim_wr_tx_header(struct dsim_global *dsim,\n" - "+\tunsigned char di, unsigned char data0, unsigned char data1);\n" - "+extern void s5p_dsim_wr_tx_data(struct dsim_global *dsim, unsigned int tx_data);\n" - "+\n" "+#endif /* _S5P_DSIM_LOWLEVEL_H */\n" - "</pre>\n" - "<br>\n" - "</body>\n" - "</html>\n" - "\01:2\0" - "b\0" - "_______________________________________________\n" - "linux-arm-kernel mailing list\n" - "linux-arm-kernel@lists.infradead.org\n" - http://lists.infradead.org/mailman/listinfo/linux-arm-kernel + "\n" + "\n" + "-------------- next part --------------\n" + "An HTML attachment was scrubbed...\n" + URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20100702/2b6784e7/attachment-0001.html> -5eaedf4d450a70003a749efbc1aedf28719b439406d11f7c51f46d58846ffad0 +b686b82bc94e0af2e3632beb13625a1903263adb04266c7425c16d04d5d9fd3e
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