diff for duplicates of <4C3421E1.2070609@samsung.com> diff --git a/a/1.txt b/N1/1.txt index 1a9ff47..de53359 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -258,7 +258,8 @@ index 0000000..9c1d6a3 + enum dsim_byte_clk_src e_byte_clk; + + /* -+ * =====================+ * | P | M | S | MHz | ++ * =========================================== ++ * | P | M | S | MHz | + * ------------------------------------------- + * | 3 | 100 | 3 | 100 | + * | 3 | 100 | 2 | 200 | @@ -941,7 +942,7 @@ index 0000000..874efa0 +{ + unsigned int reg; + -+ WARN_ON(dsim = NULL); ++ WARN_ON(dsim == NULL); + + reg = readl(S5P_MIPI_CONTROL) & ~(1 << 0); + reg |= (enable << 0); @@ -957,7 +958,7 @@ index 0000000..874efa0 +{ + unsigned int reg; + -+ WARN_ON(dsim = NULL); ++ WARN_ON(dsim == NULL); + + reg = readl(S5P_MIPI_CONTROL) & ~(1 << 2); + reg |= (enable << 2); @@ -970,7 +971,7 @@ index 0000000..874efa0 + +int s5p_dsim_part_reset(struct dsim_global *dsim) +{ -+ WARN_ON(dsim = NULL); ++ WARN_ON(dsim == NULL); + + writel(S5P_MIPI_M_RESETN, S5P_MIPI_PHY_CON0); + @@ -981,7 +982,7 @@ index 0000000..874efa0 + +int s5p_dsim_init_d_phy(struct dsim_global *dsim) +{ -+ WARN_ON(dsim = NULL); ++ WARN_ON(dsim == NULL); + + /** + * DPHY and Master block must be enabled at the system initialization @@ -1001,7 +1002,7 @@ index 0000000..874efa0 +{ + int ret = -1; + -+ WARN_ON(dsim = NULL); ++ WARN_ON(dsim == NULL); + + if (IS_ERR(p_mipi_1_1v) || IS_ERR(p_mipi_1_8v)) { + dev_err(dsim->dev, "p_mipi_1_1v or p_mipi_1_8v is NULL.\n"); @@ -1237,12 +1238,12 @@ index 0000000..1ffc1e0 + struct mipi_lcd_info *lcd_info = NULL; + + lcd_info = kmalloc(sizeof(struct mipi_lcd_info), GFP_KERNEL); -+ if (lcd_info = NULL) ++ if (lcd_info == NULL) + return -ENOMEM; + + lcd_info->mipi_drv = kmalloc(sizeof(struct mipi_lcd_driver), + GFP_KERNEL); -+ if (lcd_info->mipi_drv = NULL) ++ if (lcd_info->mipi_drv == NULL) + return -ENOMEM; + + @@ -1269,7 +1270,7 @@ index 0000000..1ffc1e0 + return -EFAULT; + } + -+ if (mode = 0) ++ if (mode == 0) + s5p_dsim_set_data_transfer_mode(&dsim, + DSIM_TRANSFER_BYCPU, mode); + else @@ -1292,7 +1293,7 @@ index 0000000..1ffc1e0 + list_for_each_entry(lcd_info, &lcd_info_list, list) { + mipi_drv = lcd_info->mipi_drv; + -+ if ((strcmp(mipi_drv->name, name)) = 0) { ++ if ((strcmp(mipi_drv->name, name)) == 0) { + mutex_unlock(&mipi_lock); + dev_dbg(dsim.dev, "found!!!(%s).\n", mipi_drv->name); + return mipi_drv; @@ -1318,13 +1319,15 @@ index 0000000..1ffc1e0 + /* set dsim config data, dsim lcd config data and lcd panel data. */ + dsim.dsim_info = dsim.pd->dsim_info; + dsim.dsim_lcd_info = dsim.pd->dsim_lcd_info; -+ dsim.lcd_panel_info + (struct fb_videomode *) dsim.dsim_lcd_info->lcd_panel_info; -+ dsim.mipi_ddi_pd + (struct mipi_ddi_platform_data *) ++ dsim.lcd_panel_info = ++ (struct fb_videomode *) dsim.dsim_lcd_info->lcd_panel_info; ++ dsim.mipi_ddi_pd = ++ (struct mipi_ddi_platform_data *) + dsim.dsim_lcd_info->mipi_ddi_pd; + + dsim.mipi_ddi_pd->resume_complete = 0; + -+ WARN_ON(dsim.pd->mipi_1_1v_name = NULL); ++ WARN_ON(dsim.pd->mipi_1_1v_name == NULL); + + dsim.r_mipi_1_1v = regulator_get(&pdev->dev, dsim.pd->mipi_1_1v_name); + if (IS_ERR(dsim.r_mipi_1_1v)) { @@ -1333,7 +1336,7 @@ index 0000000..1ffc1e0 + goto regulator_get_err; + } + -+ WARN_ON(dsim.pd->mipi_1_8v_name = NULL); ++ WARN_ON(dsim.pd->mipi_1_8v_name == NULL); + + dsim.r_mipi_1_8v = regulator_get(&pdev->dev, dsim.pd->mipi_1_8v_name); + if (IS_ERR(dsim.r_mipi_1_8v)) { @@ -1382,7 +1385,7 @@ index 0000000..1ffc1e0 + * it uses frame done interrupt handler + * only in case of MIPI Video mode. + */ -+ if (dsim.dsim_lcd_info->e_interface = DSIM_VIDEO) { ++ if (dsim.dsim_lcd_info->e_interface == DSIM_VIDEO) { + dsim.irq = platform_get_irq(pdev, 0); + if (request_irq(dsim.irq, s5p_dsim_interrupt_handler, + IRQF_DISABLED, "mipi-dsi", &dsim)) { @@ -1401,7 +1404,7 @@ index 0000000..1ffc1e0 + + /* find lcd panel driver registered to mipi-dsi driver. */ + dsim.mipi_drv = scan_mipi_driver(dsim.pd->lcd_panel_name); -+ if (dsim.mipi_drv = NULL) { ++ if (dsim.mipi_drv == NULL) { + dev_err(&pdev->dev, "mipi_drv is NULL.\n"); + goto mipi_drv_err; + } @@ -1442,7 +1445,7 @@ index 0000000..1ffc1e0 + s5p_dsim_register_notif(&pdev->dev); + + /* in case of command mode, trigger. */ -+ if (dsim.dsim_lcd_info->e_interface = DSIM_COMMAND) { ++ if (dsim.dsim_lcd_info->e_interface == DSIM_COMMAND) { + if (dsim.pd->trigger) + dsim.pd->trigger(registered_fb[0]); + else @@ -1450,7 +1453,7 @@ index 0000000..1ffc1e0 + } + + dev_info(&pdev->dev, "mipi-dsi driver(%s mode) has been probed.\n", -+ (dsim.dsim_lcd_info->e_interface = DSIM_COMMAND) ? ++ (dsim.dsim_lcd_info->e_interface == DSIM_COMMAND) ? + "CPU" : "RGB"); + + return 0; @@ -1614,7 +1617,7 @@ index 0000000..696faf3 +{ + unsigned int data_cnt = 0, payload = 0; + -+ WARN_ON(dsim = NULL); ++ WARN_ON(dsim == NULL); + + /* in case that data count is more then 4 */ + for (data_cnt = 0; data_cnt < data1; data_cnt += 4) { @@ -1623,7 +1626,7 @@ index 0000000..696faf3 + * send remainder data less then 4. + */ + if ((data1 - data_cnt) < 4) { -+ if ((data1 - data_cnt) = 3) { ++ if ((data1 - data_cnt) == 3) { + payload = *(u8 *)(data0 + data_cnt) | + (*(u8 *)(data0 + (data_cnt + 1))) << 8 | + (*(u8 *)(data0 + (data_cnt + 2))) << 16; @@ -1631,14 +1634,14 @@ index 0000000..696faf3 + payload, *(u8 *)(data0 + data_cnt), + *(u8 *)(data0 + (data_cnt + 1)), + *(u8 *)(data0 + (data_cnt + 2))); -+ } else if ((data1 - data_cnt) = 2) { ++ } else if ((data1 - data_cnt) == 2) { + payload = *(u8 *)(data0 + data_cnt) | + (*(u8 *)(data0 + (data_cnt + 1))) << 8; + dev_dbg(dsim->dev, + "count = 2 payload = %x, %x %x\n", payload, + *(u8 *)(data0 + data_cnt), + *(u8 *)(data0 + (data_cnt + 1))); -+ } else if ((data1 - data_cnt) = 1) { ++ } else if ((data1 - data_cnt) == 1) { + payload = *(u8 *)(data0 + data_cnt); + } + @@ -1672,9 +1675,9 @@ index 0000000..696faf3 + + dsim = (struct dsim_global *)dsim_data; + -+ WARN_ON(dsim = NULL); ++ WARN_ON(dsim == NULL); + -+ if (dsim->state = DSIM_STATE_ULPS) { ++ if (dsim->state == DSIM_STATE_ULPS) { + dev_err(dsim->dev, "state is ULPS.\n"); + + return -EINVAL; @@ -1686,7 +1689,7 @@ index 0000000..696faf3 + mdelay(udelay); + + /* only if transfer mode is LPDT, wait SFR becomes empty. */ -+ if (dsim->state = DSIM_STATE_STOP) { ++ if (dsim->state == DSIM_STATE_STOP) { + while (!(s5p_dsim_get_fifo_state(dsim) & + SFR_HEADER_EMPTY)) { + if ((timeout--) > 0) @@ -1808,7 +1811,7 @@ index 0000000..696faf3 +{ + unsigned int cnt; + -+ WARN_ON(dsim = NULL); ++ WARN_ON(dsim == NULL); + + for (cnt = 0; cnt < DSIM_HEADER_FIFO_SZ; cnt++) + dsim->header_fifo_index[cnt] = -1; @@ -1818,7 +1821,7 @@ index 0000000..696faf3 + +int s5p_dsim_pll_on(struct dsim_global *dsim, unsigned int enable) +{ -+ WARN_ON(dsim = NULL); ++ WARN_ON(dsim == NULL); + + if (enable) { + int sw_timeout = 1000; @@ -1828,7 +1831,7 @@ index 0000000..696faf3 + sw_timeout--; + if (s5p_dsim_is_pll_stable(dsim)) + return 0; -+ if (sw_timeout = 0) ++ if (sw_timeout == 0) + return -EINVAL; + } + } else @@ -1844,7 +1847,7 @@ index 0000000..696faf3 + unsigned long dfin_pll, dfvco, dpll_out; + unsigned int i, freq_band = 0xf; + -+ WARN_ON(dsim = NULL); ++ WARN_ON(dsim == NULL); + + dfin_pll = (MIPI_FIN / pre_divider); + @@ -1918,7 +1921,7 @@ index 0000000..696faf3 + unsigned int esc_div; + unsigned long esc_clk_error_rate; + -+ WARN_ON(dsim = NULL); ++ WARN_ON(dsim == NULL); + + if (enable) { + dsim->e_clk_src = byte_clk_sel; @@ -1927,11 +1930,11 @@ index 0000000..696faf3 + s5p_dsim_set_byte_clock_src(dsim, byte_clk_sel); + + /* DPHY, DSIM Link : D-PHY clock out */ -+ if (byte_clk_sel = DSIM_PLL_OUT_DIV8) { ++ if (byte_clk_sel == DSIM_PLL_OUT_DIV8) { + dsim->hs_clk = s5p_dsim_change_pll(dsim, + dsim->dsim_info->p, dsim->dsim_info->m, + dsim->dsim_info->s); -+ if (dsim->hs_clk = 0) { ++ if (dsim->hs_clk == 0) { + dev_err(dsim->dev, + "failed to get hs clock.\n"); + return -EINVAL; @@ -1941,11 +1944,11 @@ index 0000000..696faf3 + s5p_dsim_enable_pll_bypass(dsim, 0); + s5p_dsim_pll_on(dsim, 1); + /* DPHY : D-PHY clock out, DSIM link : external clock out */ -+ } else if (byte_clk_sel = DSIM_EXT_CLK_DIV8) ++ } else if (byte_clk_sel == DSIM_EXT_CLK_DIV8) + dev_warn(dsim->dev, + "this project is not support \ + external clock source for MIPI DSIM\n"); -+ else if (byte_clk_sel = DSIM_EXT_CLK_BYPASS) ++ else if (byte_clk_sel == DSIM_EXT_CLK_BYPASS) + dev_warn(dsim->dev, + "this project is not support \ + external clock source for MIPI DSIM\n"); @@ -1970,7 +1973,7 @@ index 0000000..696faf3 + * in case of evt0, DSIM_TRUE is enable and + * DSIM_FALSE is enable for evt1. + */ -+ if (dsim->pd->platform_rev = 1) ++ if (dsim->pd->platform_rev == 1) + s5p_dsim_enable_byte_clock(dsim, DSIM_FALSE); + else + s5p_dsim_enable_byte_clock(dsim, DSIM_TRUE); @@ -2009,12 +2012,12 @@ index 0000000..696faf3 + * in case of evt0, DSIM_FALSE is disable and + * DSIM_TRUE is disable for evt1. + */ -+ if (dsim->pd->platform_rev = 1) ++ if (dsim->pd->platform_rev == 1) + s5p_dsim_enable_byte_clock(dsim, DSIM_TRUE); + else + s5p_dsim_enable_byte_clock(dsim, DSIM_FALSE); + -+ if (byte_clk_sel = DSIM_PLL_OUT_DIV8) ++ if (byte_clk_sel == DSIM_PLL_OUT_DIV8) + s5p_dsim_pll_on(dsim, 0); + } + @@ -2023,7 +2026,7 @@ index 0000000..696faf3 + +int s5p_dsim_init_dsim(struct dsim_global *dsim) +{ -+ WARN_ON(dsim = NULL); ++ WARN_ON(dsim == NULL); + + if (dsim->pd->init_d_phy) + dsim->pd->init_d_phy(dsim); @@ -2074,17 +2077,17 @@ index 0000000..696faf3 + struct s3c_fb_pd_win *pd; + unsigned int width = 0, height = 0; + -+ WARN_ON(dsim = NULL); ++ WARN_ON(dsim == NULL); + + pd = (struct s3c_fb_pd_win *)main_lcd->lcd_panel_info; + + /* in case of VIDEO MODE (RGB INTERFACE) */ -+ if (dsim->dsim_lcd_info->e_interface = (u32) DSIM_VIDEO) { ++ if (dsim->dsim_lcd_info->e_interface == (u32) DSIM_VIDEO) { + mlcd_video = (struct fb_videomode *)&pd->win_mode; + width = mlcd_video->xres; + height = mlcd_video->yres; + -+ if (dsim->dsim_info->auto_vertical_cnt = DSIM_FALSE) { ++ if (dsim->dsim_info->auto_vertical_cnt == DSIM_FALSE) { + s5p_dsim_set_main_disp_vporch(dsim, + mlcd_video->upper_margin, + mlcd_video->lower_margin, 0); @@ -2115,7 +2118,7 @@ index 0000000..696faf3 +{ + unsigned int time_out = 100; + -+ WARN_ON(dsim = NULL); ++ WARN_ON(dsim == NULL); + + switch (dsim->state) { + case DSIM_STATE_RESET: @@ -2135,11 +2138,11 @@ index 0000000..696faf3 + + /* check clock and data lane state is stop state */ + while (!(s5p_dsim_is_lane_state(dsim, DSIM_LANE_CLOCK) -+ = DSIM_LANE_STATE_STOP) && ++ == DSIM_LANE_STATE_STOP) && + !(s5p_dsim_is_lane_state(dsim, -+ dsim->data_lane) = DSIM_LANE_STATE_STOP)) { ++ dsim->data_lane) == DSIM_LANE_STATE_STOP)) { + time_out--; -+ if (time_out = 0) { ++ if (time_out == 0) { + dev_info(dsim->dev, + "DSI Master is not stop state.\n"); + dev_info(dsim->dev, @@ -2180,9 +2183,9 @@ index 0000000..696faf3 + +int s5p_dsim_set_hs_enable(struct dsim_global *dsim) +{ -+ WARN_ON(dsim = NULL); ++ WARN_ON(dsim == NULL); + -+ if (dsim->state = DSIM_STATE_STOP) { ++ if (dsim->state == DSIM_STATE_STOP) { + if (dsim->e_clk_src != DSIM_EXT_CLK_BYPASS) { + dsim->state = DSIM_STATE_HSCLKEN; + s5p_dsim_set_data_mode(dsim, @@ -2204,10 +2207,10 @@ index 0000000..696faf3 +{ + int ret = -1; + -+ WARN_ON(dsim = NULL); ++ WARN_ON(dsim == NULL); + + if (hs_enable) { -+ if (dsim->state = DSIM_STATE_HSCLKEN) { ++ if (dsim->state == DSIM_STATE_HSCLKEN) { + s5p_dsim_set_data_mode(dsim, data_path, + DSIM_STATE_HSCLKEN); + ret = 0; @@ -2216,7 +2219,7 @@ index 0000000..696faf3 + ret = -EINVAL; + } + } else { -+ if (dsim->state = DSIM_STATE_INIT || dsim->state = ++ if (dsim->state == DSIM_STATE_INIT || dsim->state == + DSIM_STATE_ULPS) { + dev_err(dsim->dev, + "DSI Master is not STOP or HSDT state.\n"); @@ -2237,7 +2240,7 @@ index 0000000..696faf3 + + dsim = (struct dsim_global *)dsim_data; + -+ WARN_ON(dsim = NULL); ++ WARN_ON(dsim == NULL); + + return _s5p_dsim_get_frame_done_status(dsim); +} @@ -2248,7 +2251,7 @@ index 0000000..696faf3 + + dsim = (struct dsim_global *)dsim_data; + -+ WARN_ON(dsim = NULL); ++ WARN_ON(dsim == NULL); + + _s5p_dsim_clear_frame_done(dsim); + @@ -2494,9 +2497,9 @@ index 0000000..b2fc249 + ~(0x3 << 26) & ~(1 << 25) & ~(0x3 << 18) & ~(0x7 << 12) & + ~(0x3 << 16) & ~(0x7 << 8); + -+ if (main_lcd->e_interface = DSIM_VIDEO) ++ if (main_lcd->e_interface == DSIM_VIDEO) + reg |= (1 << 25); -+ else if (main_lcd->e_interface = DSIM_COMMAND) ++ else if (main_lcd->e_interface == DSIM_COMMAND) + reg &= ~(1 << 25); + else { + dev_err(dsim->dev, "this ddi is not MIPI interface.\n"); @@ -2518,7 +2521,7 @@ index 0000000..b2fc249 + + reg = readl(dsim->reg_base + S5P_DSIM_CONFIG); + -+ if (lane = DSIM_LANE_CLOCK) { ++ if (lane == DSIM_LANE_CLOCK) { + if (enable) + reg |= (1 << 0); + else @@ -2772,7 +2775,7 @@ index 0000000..b2fc249 +{ + unsigned int reg = readl(dsim->reg_base + S5P_DSIM_ESCMODE); + -+ if (state = DSIM_STATE_HSCLKEN) ++ if (state == DSIM_STATE_HSCLKEN) + reg &= ~data; + else + reg |= data; diff --git a/a/content_digest b/N1/content_digest index 55542e8..abe363e 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,7 +1,7 @@ "ref\04C341FFD.6010405@samsung.com\0" - "From\0InKi Dae <inki.dae@samsung.com>\0" + "From\0inki.dae@samsung.com (InKi Dae)\0" "Subject\0[PATCH v2 2/2] S5PV210: Add MIPI-DSI Driver.\0" - "Date\0Wed, 07 Jul 2010 06:42:41 +0000\0" + "Date\0Wed, 07 Jul 2010 15:42:41 +0900\0" "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" @@ -265,7 +265,8 @@ "+\tenum dsim_byte_clk_src e_byte_clk;\n" "+\n" "+\t/*\n" - "+\t * =====================+\t * | P | M | S | MHz |\n" + "+\t * ===========================================\n" + "+\t * | P | M | S | MHz |\n" "+\t * -------------------------------------------\n" "+\t * | 3 | 100 | 3 | 100 |\n" "+\t * | 3 | 100 | 2 | 200 |\n" @@ -948,7 +949,7 @@ "+{\n" "+\tunsigned int reg;\n" "+\n" - "+\tWARN_ON(dsim = NULL);\n" + "+\tWARN_ON(dsim == NULL);\n" "+\n" "+\treg = readl(S5P_MIPI_CONTROL) & ~(1 << 0);\n" "+\treg |= (enable << 0);\n" @@ -964,7 +965,7 @@ "+{\n" "+\tunsigned int reg;\n" "+\n" - "+\tWARN_ON(dsim = NULL);\n" + "+\tWARN_ON(dsim == NULL);\n" "+\n" "+\treg = readl(S5P_MIPI_CONTROL) & ~(1 << 2);\n" "+\treg |= (enable << 2);\n" @@ -977,7 +978,7 @@ "+\n" "+int s5p_dsim_part_reset(struct dsim_global *dsim)\n" "+{\n" - "+\tWARN_ON(dsim = NULL);\n" + "+\tWARN_ON(dsim == NULL);\n" "+\n" "+\twritel(S5P_MIPI_M_RESETN, S5P_MIPI_PHY_CON0);\n" "+\n" @@ -988,7 +989,7 @@ "+\n" "+int s5p_dsim_init_d_phy(struct dsim_global *dsim)\n" "+{\n" - "+\tWARN_ON(dsim = NULL);\n" + "+\tWARN_ON(dsim == NULL);\n" "+\n" "+\t/**\n" "+\t * DPHY and Master block must be enabled at the system initialization\n" @@ -1008,7 +1009,7 @@ "+{\n" "+\tint ret = -1;\n" "+\n" - "+\tWARN_ON(dsim = NULL);\n" + "+\tWARN_ON(dsim == NULL);\n" "+\n" "+\tif (IS_ERR(p_mipi_1_1v) || IS_ERR(p_mipi_1_8v)) {\n" "+\t\tdev_err(dsim->dev, \"p_mipi_1_1v or p_mipi_1_8v is NULL.\\n\");\n" @@ -1244,12 +1245,12 @@ "+\tstruct mipi_lcd_info\t*lcd_info = NULL;\n" "+\n" "+\tlcd_info = kmalloc(sizeof(struct mipi_lcd_info), GFP_KERNEL);\n" - "+\tif (lcd_info = NULL)\n" + "+\tif (lcd_info == NULL)\n" "+\t\treturn -ENOMEM;\n" "+\n" "+\tlcd_info->mipi_drv = kmalloc(sizeof(struct mipi_lcd_driver),\n" "+\t\tGFP_KERNEL);\n" - "+\tif (lcd_info->mipi_drv = NULL)\n" + "+\tif (lcd_info->mipi_drv == NULL)\n" "+\t\treturn -ENOMEM;\n" "+\n" "+\n" @@ -1276,7 +1277,7 @@ "+\t\treturn -EFAULT;\n" "+\t}\n" "+\n" - "+\tif (mode = 0)\n" + "+\tif (mode == 0)\n" "+\t\ts5p_dsim_set_data_transfer_mode(&dsim,\n" "+\t\t\tDSIM_TRANSFER_BYCPU, mode);\n" "+\telse\n" @@ -1299,7 +1300,7 @@ "+\tlist_for_each_entry(lcd_info, &lcd_info_list, list) {\n" "+\t\tmipi_drv = lcd_info->mipi_drv;\n" "+\n" - "+\t\tif ((strcmp(mipi_drv->name, name)) = 0) {\n" + "+\t\tif ((strcmp(mipi_drv->name, name)) == 0) {\n" "+\t\t\tmutex_unlock(&mipi_lock);\n" "+\t\t\tdev_dbg(dsim.dev, \"found!!!(%s).\\n\", mipi_drv->name);\n" "+\t\t\treturn mipi_drv;\n" @@ -1325,13 +1326,15 @@ "+\t/* set dsim config data, dsim lcd config data and lcd panel data. */\n" "+\tdsim.dsim_info = dsim.pd->dsim_info;\n" "+\tdsim.dsim_lcd_info = dsim.pd->dsim_lcd_info;\n" - "+\tdsim.lcd_panel_info +\t\t(struct fb_videomode *) dsim.dsim_lcd_info->lcd_panel_info;\n" - "+\tdsim.mipi_ddi_pd +\t\t(struct mipi_ddi_platform_data *)\n" + "+\tdsim.lcd_panel_info =\n" + "+\t\t(struct fb_videomode *) dsim.dsim_lcd_info->lcd_panel_info;\n" + "+\tdsim.mipi_ddi_pd =\n" + "+\t\t(struct mipi_ddi_platform_data *)\n" "+\t\t\tdsim.dsim_lcd_info->mipi_ddi_pd;\n" "+\n" "+\tdsim.mipi_ddi_pd->resume_complete = 0;\n" "+\n" - "+\tWARN_ON(dsim.pd->mipi_1_1v_name = NULL);\n" + "+\tWARN_ON(dsim.pd->mipi_1_1v_name == NULL);\n" "+\n" "+\tdsim.r_mipi_1_1v = regulator_get(&pdev->dev, dsim.pd->mipi_1_1v_name);\n" "+\tif (IS_ERR(dsim.r_mipi_1_1v)) {\n" @@ -1340,7 +1343,7 @@ "+\t\tgoto regulator_get_err;\n" "+\t}\n" "+\n" - "+\tWARN_ON(dsim.pd->mipi_1_8v_name = NULL);\n" + "+\tWARN_ON(dsim.pd->mipi_1_8v_name == NULL);\n" "+\n" "+\tdsim.r_mipi_1_8v = regulator_get(&pdev->dev, dsim.pd->mipi_1_8v_name);\n" "+\tif (IS_ERR(dsim.r_mipi_1_8v)) {\n" @@ -1389,7 +1392,7 @@ "+\t * it uses frame done interrupt handler\n" "+\t * only in case of MIPI Video mode.\n" "+\t */\n" - "+\tif (dsim.dsim_lcd_info->e_interface = DSIM_VIDEO) {\n" + "+\tif (dsim.dsim_lcd_info->e_interface == DSIM_VIDEO) {\n" "+\t\tdsim.irq = platform_get_irq(pdev, 0);\n" "+\t\tif (request_irq(dsim.irq, s5p_dsim_interrupt_handler,\n" "+\t\t\t\tIRQF_DISABLED, \"mipi-dsi\", &dsim)) {\n" @@ -1408,7 +1411,7 @@ "+\n" "+\t/* find lcd panel driver registered to mipi-dsi driver. */\n" "+\tdsim.mipi_drv = scan_mipi_driver(dsim.pd->lcd_panel_name);\n" - "+\tif (dsim.mipi_drv = NULL) {\n" + "+\tif (dsim.mipi_drv == NULL) {\n" "+\t\tdev_err(&pdev->dev, \"mipi_drv is NULL.\\n\");\n" "+\t\tgoto mipi_drv_err;\n" "+\t}\n" @@ -1449,7 +1452,7 @@ "+\ts5p_dsim_register_notif(&pdev->dev);\n" "+\n" "+\t/* in case of command mode, trigger. */\n" - "+\tif (dsim.dsim_lcd_info->e_interface = DSIM_COMMAND) {\n" + "+\tif (dsim.dsim_lcd_info->e_interface == DSIM_COMMAND) {\n" "+\t\tif (dsim.pd->trigger)\n" "+\t\t\tdsim.pd->trigger(registered_fb[0]);\n" "+\t\telse\n" @@ -1457,7 +1460,7 @@ "+\t}\n" "+\n" "+\tdev_info(&pdev->dev, \"mipi-dsi driver(%s mode) has been probed.\\n\",\n" - "+\t\t(dsim.dsim_lcd_info->e_interface = DSIM_COMMAND) ?\n" + "+\t\t(dsim.dsim_lcd_info->e_interface == DSIM_COMMAND) ?\n" "+\t\t\t\"CPU\" : \"RGB\");\n" "+\n" "+\treturn 0;\n" @@ -1621,7 +1624,7 @@ "+{\n" "+\tunsigned int data_cnt = 0, payload = 0;\n" "+\n" - "+\tWARN_ON(dsim = NULL);\n" + "+\tWARN_ON(dsim == NULL);\n" "+\n" "+\t/* in case that data count is more then 4 */\n" "+\tfor (data_cnt = 0; data_cnt < data1; data_cnt += 4) {\n" @@ -1630,7 +1633,7 @@ "+\t\t * send remainder data less then 4.\n" "+\t\t */\n" "+\t\tif ((data1 - data_cnt) < 4) {\n" - "+\t\t\tif ((data1 - data_cnt) = 3) {\n" + "+\t\t\tif ((data1 - data_cnt) == 3) {\n" "+\t\t\t\tpayload = *(u8 *)(data0 + data_cnt) |\n" "+\t\t\t\t (*(u8 *)(data0 + (data_cnt + 1))) << 8 |\n" "+\t\t\t\t\t(*(u8 *)(data0 + (data_cnt + 2))) << 16;\n" @@ -1638,14 +1641,14 @@ "+\t\t\t\tpayload, *(u8 *)(data0 + data_cnt),\n" "+\t\t\t\t*(u8 *)(data0 + (data_cnt + 1)),\n" "+\t\t\t\t*(u8 *)(data0 + (data_cnt + 2)));\n" - "+\t\t\t} else if ((data1 - data_cnt) = 2) {\n" + "+\t\t\t} else if ((data1 - data_cnt) == 2) {\n" "+\t\t\t\tpayload = *(u8 *)(data0 + data_cnt) |\n" "+\t\t\t\t\t(*(u8 *)(data0 + (data_cnt + 1))) << 8;\n" "+\t\t\tdev_dbg(dsim->dev,\n" "+\t\t\t\t\"count = 2 payload = %x, %x %x\\n\", payload,\n" "+\t\t\t\t*(u8 *)(data0 + data_cnt),\n" "+\t\t\t\t*(u8 *)(data0 + (data_cnt + 1)));\n" - "+\t\t\t} else if ((data1 - data_cnt) = 1) {\n" + "+\t\t\t} else if ((data1 - data_cnt) == 1) {\n" "+\t\t\t\tpayload = *(u8 *)(data0 + data_cnt);\n" "+\t\t\t}\n" "+\n" @@ -1679,9 +1682,9 @@ "+\n" "+\tdsim = (struct dsim_global *)dsim_data;\n" "+\n" - "+\tWARN_ON(dsim = NULL);\n" + "+\tWARN_ON(dsim == NULL);\n" "+\n" - "+\tif (dsim->state = DSIM_STATE_ULPS) {\n" + "+\tif (dsim->state == DSIM_STATE_ULPS) {\n" "+\t\tdev_err(dsim->dev, \"state is ULPS.\\n\");\n" "+\n" "+\t\treturn -EINVAL;\n" @@ -1693,7 +1696,7 @@ "+\tmdelay(udelay);\n" "+\n" "+\t/* only if transfer mode is LPDT, wait SFR becomes empty. */\n" - "+\tif (dsim->state = DSIM_STATE_STOP) {\n" + "+\tif (dsim->state == DSIM_STATE_STOP) {\n" "+\t\twhile (!(s5p_dsim_get_fifo_state(dsim) &\n" "+\t\t\t\tSFR_HEADER_EMPTY)) {\n" "+\t\t\tif ((timeout--) > 0)\n" @@ -1815,7 +1818,7 @@ "+{\n" "+\tunsigned int cnt;\n" "+\n" - "+\tWARN_ON(dsim = NULL);\n" + "+\tWARN_ON(dsim == NULL);\n" "+\n" "+\tfor (cnt = 0; cnt < DSIM_HEADER_FIFO_SZ; cnt++)\n" "+\t\tdsim->header_fifo_index[cnt] = -1;\n" @@ -1825,7 +1828,7 @@ "+\n" "+int s5p_dsim_pll_on(struct dsim_global *dsim, unsigned int enable)\n" "+{\n" - "+\tWARN_ON(dsim = NULL);\n" + "+\tWARN_ON(dsim == NULL);\n" "+\n" "+\tif (enable) {\n" "+\t\tint sw_timeout = 1000;\n" @@ -1835,7 +1838,7 @@ "+\t\t\tsw_timeout--;\n" "+\t\t\tif (s5p_dsim_is_pll_stable(dsim))\n" "+\t\t\t\treturn 0;\n" - "+\t\t\tif (sw_timeout = 0)\n" + "+\t\t\tif (sw_timeout == 0)\n" "+\t\t\t\treturn -EINVAL;\n" "+\t\t}\n" "+\t} else\n" @@ -1851,7 +1854,7 @@ "+\tunsigned long dfin_pll, dfvco, dpll_out;\n" "+\tunsigned int i, freq_band = 0xf;\n" "+\n" - "+\tWARN_ON(dsim = NULL);\n" + "+\tWARN_ON(dsim == NULL);\n" "+\n" "+\tdfin_pll = (MIPI_FIN / pre_divider);\n" "+\n" @@ -1925,7 +1928,7 @@ "+\tunsigned int esc_div;\n" "+\tunsigned long esc_clk_error_rate;\n" "+\n" - "+\tWARN_ON(dsim = NULL);\n" + "+\tWARN_ON(dsim == NULL);\n" "+\n" "+\tif (enable) {\n" "+\t\tdsim->e_clk_src = byte_clk_sel;\n" @@ -1934,11 +1937,11 @@ "+\t\ts5p_dsim_set_byte_clock_src(dsim, byte_clk_sel);\n" "+\n" "+\t\t/* DPHY, DSIM Link : D-PHY clock out */\n" - "+\t\tif (byte_clk_sel = DSIM_PLL_OUT_DIV8) {\n" + "+\t\tif (byte_clk_sel == DSIM_PLL_OUT_DIV8) {\n" "+\t\t\tdsim->hs_clk = s5p_dsim_change_pll(dsim,\n" "+\t\t\t\tdsim->dsim_info->p, dsim->dsim_info->m,\n" "+\t\t\t\tdsim->dsim_info->s);\n" - "+\t\t\tif (dsim->hs_clk = 0) {\n" + "+\t\t\tif (dsim->hs_clk == 0) {\n" "+\t\t\t\tdev_err(dsim->dev,\n" "+\t\t\t\t\t\"failed to get hs clock.\\n\");\n" "+\t\t\t\treturn -EINVAL;\n" @@ -1948,11 +1951,11 @@ "+\t\t\ts5p_dsim_enable_pll_bypass(dsim, 0);\n" "+\t\t\ts5p_dsim_pll_on(dsim, 1);\n" "+\t\t/* DPHY : D-PHY clock out, DSIM link : external clock out */\n" - "+\t\t} else if (byte_clk_sel = DSIM_EXT_CLK_DIV8)\n" + "+\t\t} else if (byte_clk_sel == DSIM_EXT_CLK_DIV8)\n" "+\t\t\tdev_warn(dsim->dev,\n" "+\t\t\t\t\"this project is not support \\\n" "+\t\t\t\texternal clock source for MIPI DSIM\\n\");\n" - "+\t\telse if (byte_clk_sel = DSIM_EXT_CLK_BYPASS)\n" + "+\t\telse if (byte_clk_sel == DSIM_EXT_CLK_BYPASS)\n" "+\t\t\tdev_warn(dsim->dev,\n" "+\t\t\t\t\"this project is not support \\\n" "+\t\t\t\texternal clock source for MIPI DSIM\\n\");\n" @@ -1977,7 +1980,7 @@ "+\t\t * in case of evt0, DSIM_TRUE is enable and\n" "+\t\t * DSIM_FALSE is enable for evt1.\n" "+\t\t */\n" - "+\t\tif (dsim->pd->platform_rev = 1)\n" + "+\t\tif (dsim->pd->platform_rev == 1)\n" "+\t\t\ts5p_dsim_enable_byte_clock(dsim, DSIM_FALSE);\n" "+\t\telse\n" "+\t\t\ts5p_dsim_enable_byte_clock(dsim, DSIM_TRUE);\n" @@ -2016,12 +2019,12 @@ "+\t\t * in case of evt0, DSIM_FALSE is disable and\n" "+\t\t * DSIM_TRUE is disable for evt1.\n" "+\t\t */\n" - "+\t\tif (dsim->pd->platform_rev = 1)\n" + "+\t\tif (dsim->pd->platform_rev == 1)\n" "+\t\t\ts5p_dsim_enable_byte_clock(dsim, DSIM_TRUE);\n" "+\t\telse\n" "+\t\t\ts5p_dsim_enable_byte_clock(dsim, DSIM_FALSE);\n" "+\n" - "+\t\tif (byte_clk_sel = DSIM_PLL_OUT_DIV8)\n" + "+\t\tif (byte_clk_sel == DSIM_PLL_OUT_DIV8)\n" "+\t\t\ts5p_dsim_pll_on(dsim, 0);\n" "+\t}\n" "+\n" @@ -2030,7 +2033,7 @@ "+\n" "+int s5p_dsim_init_dsim(struct dsim_global *dsim)\n" "+{\n" - "+\tWARN_ON(dsim = NULL);\n" + "+\tWARN_ON(dsim == NULL);\n" "+\n" "+\tif (dsim->pd->init_d_phy)\n" "+\t\tdsim->pd->init_d_phy(dsim);\n" @@ -2081,17 +2084,17 @@ "+\tstruct s3c_fb_pd_win *pd;\n" "+\tunsigned int width = 0, height = 0;\n" "+\n" - "+\tWARN_ON(dsim = NULL);\n" + "+\tWARN_ON(dsim == NULL);\n" "+\n" "+\tpd = (struct s3c_fb_pd_win *)main_lcd->lcd_panel_info;\n" "+\n" "+\t/* in case of VIDEO MODE (RGB INTERFACE) */\n" - "+\tif (dsim->dsim_lcd_info->e_interface = (u32) DSIM_VIDEO) {\n" + "+\tif (dsim->dsim_lcd_info->e_interface == (u32) DSIM_VIDEO) {\n" "+\t\tmlcd_video = (struct fb_videomode *)&pd->win_mode;\n" "+\t\twidth = mlcd_video->xres;\n" "+\t\theight = mlcd_video->yres;\n" "+\n" - "+\t\tif (dsim->dsim_info->auto_vertical_cnt = DSIM_FALSE) {\n" + "+\t\tif (dsim->dsim_info->auto_vertical_cnt == DSIM_FALSE) {\n" "+\t\t\ts5p_dsim_set_main_disp_vporch(dsim,\n" "+\t\t\t\tmlcd_video->upper_margin,\n" "+\t\t\t\tmlcd_video->lower_margin, 0);\n" @@ -2122,7 +2125,7 @@ "+{\n" "+\tunsigned int time_out = 100;\n" "+\n" - "+\tWARN_ON(dsim = NULL);\n" + "+\tWARN_ON(dsim == NULL);\n" "+\n" "+\tswitch (dsim->state) {\n" "+\tcase DSIM_STATE_RESET:\n" @@ -2142,11 +2145,11 @@ "+\n" "+\t\t/* check clock and data lane state is stop state */\n" "+\t\twhile (!(s5p_dsim_is_lane_state(dsim, DSIM_LANE_CLOCK)\n" - "+\t\t\t = DSIM_LANE_STATE_STOP) &&\n" + "+\t\t\t == DSIM_LANE_STATE_STOP) &&\n" "+\t\t\t!(s5p_dsim_is_lane_state(dsim,\n" - "+\t\t\t\tdsim->data_lane) = DSIM_LANE_STATE_STOP)) {\n" + "+\t\t\t\tdsim->data_lane) == DSIM_LANE_STATE_STOP)) {\n" "+\t\t\ttime_out--;\n" - "+\t\t\tif (time_out = 0) {\n" + "+\t\t\tif (time_out == 0) {\n" "+\t\t\t\tdev_info(dsim->dev,\n" "+\t\t\t\t\t\"DSI Master is not stop state.\\n\");\n" "+\t\t\t\tdev_info(dsim->dev,\n" @@ -2187,9 +2190,9 @@ "+\n" "+int s5p_dsim_set_hs_enable(struct dsim_global *dsim)\n" "+{\n" - "+\tWARN_ON(dsim = NULL);\n" + "+\tWARN_ON(dsim == NULL);\n" "+\n" - "+\tif (dsim->state = DSIM_STATE_STOP) {\n" + "+\tif (dsim->state == DSIM_STATE_STOP) {\n" "+\t\tif (dsim->e_clk_src != DSIM_EXT_CLK_BYPASS) {\n" "+\t\t\tdsim->state = DSIM_STATE_HSCLKEN;\n" "+\t\t\ts5p_dsim_set_data_mode(dsim,\n" @@ -2211,10 +2214,10 @@ "+{\n" "+\tint ret = -1;\n" "+\n" - "+\tWARN_ON(dsim = NULL);\n" + "+\tWARN_ON(dsim == NULL);\n" "+\n" "+\tif (hs_enable) {\n" - "+\t\tif (dsim->state = DSIM_STATE_HSCLKEN) {\n" + "+\t\tif (dsim->state == DSIM_STATE_HSCLKEN) {\n" "+\t\t\ts5p_dsim_set_data_mode(dsim, data_path,\n" "+\t\t\t\tDSIM_STATE_HSCLKEN);\n" "+\t\t\tret = 0;\n" @@ -2223,7 +2226,7 @@ "+\t\t\tret = -EINVAL;\n" "+\t\t}\n" "+\t} else {\n" - "+\t\tif (dsim->state = DSIM_STATE_INIT || dsim->state =\n" + "+\t\tif (dsim->state == DSIM_STATE_INIT || dsim->state ==\n" "+\t\t\tDSIM_STATE_ULPS) {\n" "+\t\t\tdev_err(dsim->dev,\n" "+\t\t\t\t\"DSI Master is not STOP or HSDT state.\\n\");\n" @@ -2244,7 +2247,7 @@ "+\n" "+\tdsim = (struct dsim_global *)dsim_data;\n" "+\n" - "+\tWARN_ON(dsim = NULL);\n" + "+\tWARN_ON(dsim == NULL);\n" "+\n" "+\treturn _s5p_dsim_get_frame_done_status(dsim);\n" "+}\n" @@ -2255,7 +2258,7 @@ "+\n" "+\tdsim = (struct dsim_global *)dsim_data;\n" "+\n" - "+\tWARN_ON(dsim = NULL);\n" + "+\tWARN_ON(dsim == NULL);\n" "+\n" "+\t_s5p_dsim_clear_frame_done(dsim);\n" "+\n" @@ -2501,9 +2504,9 @@ "+\t\t~(0x3 << 26) & ~(1 << 25) & ~(0x3 << 18) & ~(0x7 << 12) &\n" "+\t\t~(0x3 << 16) & ~(0x7 << 8);\n" "+\n" - "+\tif (main_lcd->e_interface = DSIM_VIDEO)\n" + "+\tif (main_lcd->e_interface == DSIM_VIDEO)\n" "+\t\treg |= (1 << 25);\n" - "+\telse if (main_lcd->e_interface = DSIM_COMMAND)\n" + "+\telse if (main_lcd->e_interface == DSIM_COMMAND)\n" "+\t\treg &= ~(1 << 25);\n" "+\telse {\n" "+\t\tdev_err(dsim->dev, \"this ddi is not MIPI interface.\\n\");\n" @@ -2525,7 +2528,7 @@ "+\n" "+\treg = readl(dsim->reg_base + S5P_DSIM_CONFIG);\n" "+\n" - "+\tif (lane = DSIM_LANE_CLOCK) {\n" + "+\tif (lane == DSIM_LANE_CLOCK) {\n" "+\t\tif (enable)\n" "+\t\t\treg |= (1 << 0);\n" "+\t\telse\n" @@ -2779,7 +2782,7 @@ "+{\n" "+\tunsigned int reg = readl(dsim->reg_base + S5P_DSIM_ESCMODE);\n" "+\n" - "+\tif (state = DSIM_STATE_HSCLKEN)\n" + "+\tif (state == DSIM_STATE_HSCLKEN)\n" "+\t\treg &= ~data;\n" "+\telse\n" "+\t\treg |= data;\n" @@ -2989,4 +2992,4 @@ "+\n" +#endif /* _S5P_DSIM_LOWLEVEL_H */ -13585422968cf72abb141471885941f2838b7894fad977932d9a7106e3e80a74 +cde623a876765dd903b49edd20d8b9276e74c45762385105850c671f4f14aa2f
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.