From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=36852 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Ou3Fe-0001Ya-3s for qemu-devel@nongnu.org; Fri, 10 Sep 2010 09:02:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1Ou3Fc-0008KB-1A for qemu-devel@nongnu.org; Fri, 10 Sep 2010 09:02:45 -0400 Received: from cantor2.suse.de ([195.135.220.15]:46369 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1Ou3Fb-0008Jb-RF for qemu-devel@nongnu.org; Fri, 10 Sep 2010 09:02:44 -0400 Message-ID: <4C8A2C71.6040604@suse.de> Date: Fri, 10 Sep 2010 15:02:41 +0200 From: Alexander Graf MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH] target-ppc: clear MSR_POW on interrupt References: <20100721085316.10710.28700.malonedeb@soybean.canonical.com> <20100721085317.10710.79353.malone@soybean.canonical.com> <201009101432.06340.thomas.monjalon@openwide.fr> In-Reply-To: <201009101432.06340.thomas.monjalon@openwide.fr> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Thomas Monjalon Cc: Bug 608107 <608107@bugs.launchpad.net>, qemu-devel@nongnu.org Thomas Monjalon wrote: > From: till <608107@bugs.launchpad.net> > > According to FreeScale's 'Programming Environments Manual for 32-bit > Implementations of the PowerPC Architecture' [MPCFPE32B, Rev.3, 9/2005], > section 6.5, table 6-7, an interrupt resets MSR_POW to zero but qemu-0.12.4 > fails to do so. > Resetting the bit is necessary in order to bring the processor out of power > management since otherwise it goes to sleep right away in the exception > handler, i.e., it is impossible to leave PM-mode. > This doesn't look right. POW shouldn't even get stored in SRR1. Could you please redo the patch and make sure that mtmsr masks out MSR_POW? Alex