From: Gary Thomas <gary@mlbassoc.com>
To: Grazvydas Ignotas <notasas@gmail.com>
Cc: "linux-omap@vger.kernel.org" <linux-omap@vger.kernel.org>
Subject: Re: OMAP 3530 McBSP Frame Sync errors
Date: Mon, 13 Sep 2010 05:54:40 -0600 [thread overview]
Message-ID: <4C8E1100.6000906@mlbassoc.com> (raw)
In-Reply-To: <AANLkTik9ULkprMe9=qGAZj8P0HdaFq9TPfNUGxmBmcwc@mail.gmail.com>
On 09/13/2010 03:07 AM, Grazvydas Ignotas wrote:
> On Thu, Sep 9, 2010 at 6:56 PM, Gary Thomas<gary@mlbassoc.com> wrote:
>> I'm trying to use McBSP4 with an external CODEC which is a
>> slave device (i.e. the OMAP generates the Frame Sync pulses)
>> In this mode, the BSP is purely the master of these signals.
>>
>> What can it possibly mean to get Frame Sync errors in this case
>> (I'm reading from the external CODEC)?
>>
>> FYI, my registers look like this:
>> PCR0: 0x00000f0f
>> RCR1: 0x00000040, RCR2: 0x00008041
>> XCR1: 0x00000040, XCR2: 0x00008041
>> SRGR1: 0x00000f07, SRGR2: 0x0000101f
>>
>> Any ideas or help?
>
> Have you set the right McBSP source clock? It's in DEVCONF1/2 registers.
Yes, the channel works fine, but I only occasionally get errant Frame Sync errors.
--
------------------------------------------------------------
Gary Thomas | Consulting for the
MLB Associates | Embedded world
------------------------------------------------------------
prev parent reply other threads:[~2010-09-13 11:54 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-09-09 15:56 OMAP 3530 McBSP Frame Sync errors Gary Thomas
2010-09-13 9:07 ` Grazvydas Ignotas
2010-09-13 11:54 ` Gary Thomas [this message]
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