* OMAP 3530 McBSP Frame Sync errors
@ 2010-09-09 15:56 Gary Thomas
2010-09-13 9:07 ` Grazvydas Ignotas
0 siblings, 1 reply; 3+ messages in thread
From: Gary Thomas @ 2010-09-09 15:56 UTC (permalink / raw)
To: linux-omap@vger.kernel.org
I'm trying to use McBSP4 with an external CODEC which is a
slave device (i.e. the OMAP generates the Frame Sync pulses)
In this mode, the BSP is purely the master of these signals.
What can it possibly mean to get Frame Sync errors in this case
(I'm reading from the external CODEC)?
FYI, my registers look like this:
PCR0: 0x00000f0f
RCR1: 0x00000040, RCR2: 0x00008041
XCR1: 0x00000040, XCR2: 0x00008041
SRGR1: 0x00000f07, SRGR2: 0x0000101f
Any ideas or help?
--
------------------------------------------------------------
Gary Thomas | Consulting for the
MLB Associates | Embedded world
------------------------------------------------------------
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: OMAP 3530 McBSP Frame Sync errors
2010-09-09 15:56 OMAP 3530 McBSP Frame Sync errors Gary Thomas
@ 2010-09-13 9:07 ` Grazvydas Ignotas
2010-09-13 11:54 ` Gary Thomas
0 siblings, 1 reply; 3+ messages in thread
From: Grazvydas Ignotas @ 2010-09-13 9:07 UTC (permalink / raw)
To: Gary Thomas; +Cc: linux-omap@vger.kernel.org
On Thu, Sep 9, 2010 at 6:56 PM, Gary Thomas <gary@mlbassoc.com> wrote:
> I'm trying to use McBSP4 with an external CODEC which is a
> slave device (i.e. the OMAP generates the Frame Sync pulses)
> In this mode, the BSP is purely the master of these signals.
>
> What can it possibly mean to get Frame Sync errors in this case
> (I'm reading from the external CODEC)?
>
> FYI, my registers look like this:
> PCR0: 0x00000f0f
> RCR1: 0x00000040, RCR2: 0x00008041
> XCR1: 0x00000040, XCR2: 0x00008041
> SRGR1: 0x00000f07, SRGR2: 0x0000101f
>
> Any ideas or help?
Have you set the right McBSP source clock? It's in DEVCONF1/2 registers.
>
> --
> ------------------------------------------------------------
> Gary Thomas | Consulting for the
> MLB Associates | Embedded world
> ------------------------------------------------------------
> --
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: OMAP 3530 McBSP Frame Sync errors
2010-09-13 9:07 ` Grazvydas Ignotas
@ 2010-09-13 11:54 ` Gary Thomas
0 siblings, 0 replies; 3+ messages in thread
From: Gary Thomas @ 2010-09-13 11:54 UTC (permalink / raw)
To: Grazvydas Ignotas; +Cc: linux-omap@vger.kernel.org
On 09/13/2010 03:07 AM, Grazvydas Ignotas wrote:
> On Thu, Sep 9, 2010 at 6:56 PM, Gary Thomas<gary@mlbassoc.com> wrote:
>> I'm trying to use McBSP4 with an external CODEC which is a
>> slave device (i.e. the OMAP generates the Frame Sync pulses)
>> In this mode, the BSP is purely the master of these signals.
>>
>> What can it possibly mean to get Frame Sync errors in this case
>> (I'm reading from the external CODEC)?
>>
>> FYI, my registers look like this:
>> PCR0: 0x00000f0f
>> RCR1: 0x00000040, RCR2: 0x00008041
>> XCR1: 0x00000040, XCR2: 0x00008041
>> SRGR1: 0x00000f07, SRGR2: 0x0000101f
>>
>> Any ideas or help?
>
> Have you set the right McBSP source clock? It's in DEVCONF1/2 registers.
Yes, the channel works fine, but I only occasionally get errant Frame Sync errors.
--
------------------------------------------------------------
Gary Thomas | Consulting for the
MLB Associates | Embedded world
------------------------------------------------------------
^ permalink raw reply [flat|nested] 3+ messages in thread
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2010-09-09 15:56 OMAP 3530 McBSP Frame Sync errors Gary Thomas
2010-09-13 9:07 ` Grazvydas Ignotas
2010-09-13 11:54 ` Gary Thomas
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