From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jin Dongming Subject: [PATCH 04/11] kvm, x86: kvm_mce_inj_* subroutins for templated error injections Date: Thu, 14 Oct 2010 17:45:44 +0900 Message-ID: <4CB6C338.3000505@np.css.fujitsu.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-2022-JP Content-Transfer-Encoding: 7bit Cc: Dean Nelson , Marcelo Tosatti , Avi Kivity , Huang Ying , Hidetoshi Seto , "qemu-devel@nongnu.org" To: KVM list Return-path: Received: from fgwmail6.fujitsu.co.jp ([192.51.44.36]:43904 "EHLO fgwmail6.fujitsu.co.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754828Ab0JNIo0 (ORCPT ); Thu, 14 Oct 2010 04:44:26 -0400 Received: from m3.gw.fujitsu.co.jp ([10.0.50.73]) by fgwmail6.fujitsu.co.jp (Fujitsu Gateway) with ESMTP id o9E8iORc020558 for (envelope-from jin.dongming@np.css.fujitsu.com); Thu, 14 Oct 2010 17:44:24 +0900 Received: from smail (m3 [127.0.0.1]) by outgoing.m3.gw.fujitsu.co.jp (Postfix) with ESMTP id 98FC845DE4E for ; Thu, 14 Oct 2010 17:44:23 +0900 (JST) Received: from s3.gw.fujitsu.co.jp (s3.gw.fujitsu.co.jp [10.0.50.93]) by m3.gw.fujitsu.co.jp (Postfix) with ESMTP id 7659D45DE4D for ; Thu, 14 Oct 2010 17:44:23 +0900 (JST) Received: from s3.gw.fujitsu.co.jp (localhost.localdomain [127.0.0.1]) by s3.gw.fujitsu.co.jp (Postfix) with ESMTP id 4A075E08006 for ; Thu, 14 Oct 2010 17:44:23 +0900 (JST) Received: from m001.s.css.fujitsu.com (m001.s.css.fujitsu.com [10.23.4.39]) by s3.gw.fujitsu.co.jp (Postfix) with ESMTP id 0455DE18002 for ; Thu, 14 Oct 2010 17:44:23 +0900 (JST) Sender: kvm-owner@vger.kernel.org List-ID: Refactor codes for maintainability. Signed-off-by: Hidetoshi Seto Tested-by: Jin Dongming --- qemu-kvm.c | 96 ++++++++++++++++++++++++++++++++++++----------------------- 1 files changed, 58 insertions(+), 38 deletions(-) diff --git a/qemu-kvm.c b/qemu-kvm.c index a71c07c..9f248f0 100644 --- a/qemu-kvm.c +++ b/qemu-kvm.c @@ -1159,6 +1159,51 @@ static void kvm_do_set_mce(CPUState *env, struct kvm_x86_mce *mce, } } } + +static void kvm_mce_inj_srar_dataload(CPUState *env, unsigned long paddr) +{ + struct kvm_x86_mce mce = { + .bank = 9, + .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN + | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S + | MCI_STATUS_AR | 0x134, + .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV, + .addr = paddr, + .misc = (MCM_ADDR_PHYS << 6) | 0xc, + }; + + kvm_do_set_mce(env, &mce, 1); +} + +static void kvm_mce_inj_srao_memscrub(CPUState *env, unsigned long paddr) +{ + struct kvm_x86_mce mce = { + .bank = 9, + .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN + | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S + | 0xc0, + .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV, + .addr = paddr, + .misc = (MCM_ADDR_PHYS << 6) | 0xc, + }; + + kvm_do_set_mce(env, &mce, 1); +} + +static void kvm_mce_inj_srao_broadcast(unsigned long paddr) +{ + CPUState *cenv; + + kvm_inject_x86_mce(first_cpu, 9, + MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN + | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S + | 0xc0, + MCG_STATUS_MCIP | MCG_STATUS_RIPV, paddr, + (MCM_ADDR_PHYS << 6) | 0xc, 1); + for (cenv = first_cpu->next_cpu; cenv != NULL; cenv = cenv->next_cpu) + kvm_inject_x86_mce(cenv, 1, MCI_STATUS_VAL | MCI_STATUS_UC, + MCG_STATUS_MCIP | MCG_STATUS_RIPV, 0, 0, 1); +} #endif static void sigbus_handler(int n, struct qemu_signalfd_siginfo *siginfo, @@ -1167,11 +1212,9 @@ static void sigbus_handler(int n, struct qemu_signalfd_siginfo *siginfo, #if defined(KVM_CAP_MCE) && defined(TARGET_I386) if ((first_cpu->mcg_cap & MCG_SER_P) && siginfo->ssi_addr && siginfo->ssi_code == BUS_MCEERR_AO) { - uint64_t status; void *vaddr; ram_addr_t ram_addr; unsigned long paddr; - CPUState *cenv; /* Hope we are lucky for AO MCE */ vaddr = (void *)(intptr_t)siginfo->ssi_addr; @@ -1182,16 +1225,7 @@ static void sigbus_handler(int n, struct qemu_signalfd_siginfo *siginfo, (unsigned long long)siginfo->ssi_addr); return; } - status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN - | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S - | 0xc0; - kvm_inject_x86_mce(first_cpu, 9, status, - MCG_STATUS_MCIP | MCG_STATUS_RIPV, paddr, - (MCM_ADDR_PHYS << 6) | 0xc, 1); - for (cenv = first_cpu->next_cpu; cenv != NULL; cenv = cenv->next_cpu) { - kvm_inject_x86_mce(cenv, 1, MCI_STATUS_VAL | MCI_STATUS_UC, - MCG_STATUS_MCIP | MCG_STATUS_RIPV, 0, 0, 1); - } + kvm_mce_inj_srao_broadcast(paddr); } else #endif { @@ -1333,9 +1367,6 @@ static void flush_queued_work(CPUState *env) static void kvm_on_sigbus(CPUState *env, siginfo_t *siginfo) { #if defined(KVM_CAP_MCE) && defined(TARGET_I386) - struct kvm_x86_mce mce = { - .bank = 9, - }; void *vaddr; ram_addr_t ram_addr; unsigned long paddr; @@ -1343,28 +1374,12 @@ static void kvm_on_sigbus(CPUState *env, siginfo_t *siginfo) if ((env->mcg_cap & MCG_SER_P) && siginfo->si_addr && (siginfo->si_code == BUS_MCEERR_AR || siginfo->si_code == BUS_MCEERR_AO)) { - if (siginfo->si_code == BUS_MCEERR_AR) { - /* Fake an Intel architectural Data Load SRAR UCR */ - mce.status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN - | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S - | MCI_STATUS_AR | 0x134; - mce.misc = (MCM_ADDR_PHYS << 6) | 0xc; - mce.mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV; - } else { - /* - * If there is an MCE excpetion being processed, ignore - * this SRAO MCE - */ - if (kvm_mce_in_progress(env)) { - return; - } - /* Fake an Intel architectural Memory scrubbing UCR */ - mce.status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN - | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S - | 0xc0; - mce.misc = (MCM_ADDR_PHYS << 6) | 0xc; - mce.mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV; + /* + * If there is an MCE excpetion being processed, ignore this SRAO MCE + */ + if (siginfo->si_code == BUS_MCEERR_AO && kvm_mce_in_progress(env)) { + return; } vaddr = (void *)siginfo->si_addr; if (do_qemu_ram_addr_from_host(vaddr, &ram_addr) || @@ -1378,8 +1393,13 @@ static void kvm_on_sigbus(CPUState *env, siginfo_t *siginfo) hardware_memory_error(); } } - mce.addr = paddr; - kvm_do_set_mce(env, &mce, 1); + if (siginfo->si_code == BUS_MCEERR_AR) { + /* Fake an Intel architectural Data Load SRAR UCR */ + kvm_mce_inj_srar_dataload(env, paddr); + } else { + /* Fake an Intel architectural Memory scrubbing UCR */ + kvm_mce_inj_srao_memscrub(env, paddr); + } } else #endif { -- 1.7.1.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=37495 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1P6JQL-0007HS-PJ for qemu-devel@nongnu.org; Thu, 14 Oct 2010 04:44:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1P6JQJ-0002x8-Gf for qemu-devel@nongnu.org; Thu, 14 Oct 2010 04:44:29 -0400 Received: from fgwmail6.fujitsu.co.jp ([192.51.44.36]:43901) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1P6JQI-0002vn-N2 for qemu-devel@nongnu.org; Thu, 14 Oct 2010 04:44:27 -0400 Received: from m4.gw.fujitsu.co.jp ([10.0.50.74]) by fgwmail6.fujitsu.co.jp (Fujitsu Gateway) with ESMTP id o9E8iNOa020556 for (envelope-from jin.dongming@np.css.fujitsu.com); Thu, 14 Oct 2010 17:44:24 +0900 Received: from smail (m4 [127.0.0.1]) by outgoing.m4.gw.fujitsu.co.jp (Postfix) with ESMTP id 9161045DE70 for ; Thu, 14 Oct 2010 17:44:23 +0900 (JST) Received: from s4.gw.fujitsu.co.jp (s4.gw.fujitsu.co.jp [10.0.50.94]) by m4.gw.fujitsu.co.jp (Postfix) with ESMTP id 5AD2145DE6E for ; Thu, 14 Oct 2010 17:44:23 +0900 (JST) Received: from s4.gw.fujitsu.co.jp (localhost.localdomain [127.0.0.1]) by s4.gw.fujitsu.co.jp (Postfix) with ESMTP id 47784EF800C for ; Thu, 14 Oct 2010 17:44:23 +0900 (JST) Received: from m001.s.css.fujitsu.com (m001.s.css.fujitsu.com [10.23.4.39]) by s4.gw.fujitsu.co.jp (Postfix) with ESMTP id 056FDEF8005 for ; Thu, 14 Oct 2010 17:44:23 +0900 (JST) Message-ID: <4CB6C338.3000505@np.css.fujitsu.com> Date: Thu, 14 Oct 2010 17:45:44 +0900 From: Jin Dongming MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-2022-JP Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH 04/11] kvm, x86: kvm_mce_inj_* subroutins for templated error injections List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: KVM list Cc: Hidetoshi Seto , Dean Nelson , Marcelo Tosatti , "qemu-devel@nongnu.org" , Avi Kivity , Huang Ying Refactor codes for maintainability. Signed-off-by: Hidetoshi Seto Tested-by: Jin Dongming --- qemu-kvm.c | 96 ++++++++++++++++++++++++++++++++++++----------------------- 1 files changed, 58 insertions(+), 38 deletions(-) diff --git a/qemu-kvm.c b/qemu-kvm.c index a71c07c..9f248f0 100644 --- a/qemu-kvm.c +++ b/qemu-kvm.c @@ -1159,6 +1159,51 @@ static void kvm_do_set_mce(CPUState *env, struct kvm_x86_mce *mce, } } } + +static void kvm_mce_inj_srar_dataload(CPUState *env, unsigned long paddr) +{ + struct kvm_x86_mce mce = { + .bank = 9, + .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN + | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S + | MCI_STATUS_AR | 0x134, + .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV, + .addr = paddr, + .misc = (MCM_ADDR_PHYS << 6) | 0xc, + }; + + kvm_do_set_mce(env, &mce, 1); +} + +static void kvm_mce_inj_srao_memscrub(CPUState *env, unsigned long paddr) +{ + struct kvm_x86_mce mce = { + .bank = 9, + .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN + | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S + | 0xc0, + .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV, + .addr = paddr, + .misc = (MCM_ADDR_PHYS << 6) | 0xc, + }; + + kvm_do_set_mce(env, &mce, 1); +} + +static void kvm_mce_inj_srao_broadcast(unsigned long paddr) +{ + CPUState *cenv; + + kvm_inject_x86_mce(first_cpu, 9, + MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN + | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S + | 0xc0, + MCG_STATUS_MCIP | MCG_STATUS_RIPV, paddr, + (MCM_ADDR_PHYS << 6) | 0xc, 1); + for (cenv = first_cpu->next_cpu; cenv != NULL; cenv = cenv->next_cpu) + kvm_inject_x86_mce(cenv, 1, MCI_STATUS_VAL | MCI_STATUS_UC, + MCG_STATUS_MCIP | MCG_STATUS_RIPV, 0, 0, 1); +} #endif static void sigbus_handler(int n, struct qemu_signalfd_siginfo *siginfo, @@ -1167,11 +1212,9 @@ static void sigbus_handler(int n, struct qemu_signalfd_siginfo *siginfo, #if defined(KVM_CAP_MCE) && defined(TARGET_I386) if ((first_cpu->mcg_cap & MCG_SER_P) && siginfo->ssi_addr && siginfo->ssi_code == BUS_MCEERR_AO) { - uint64_t status; void *vaddr; ram_addr_t ram_addr; unsigned long paddr; - CPUState *cenv; /* Hope we are lucky for AO MCE */ vaddr = (void *)(intptr_t)siginfo->ssi_addr; @@ -1182,16 +1225,7 @@ static void sigbus_handler(int n, struct qemu_signalfd_siginfo *siginfo, (unsigned long long)siginfo->ssi_addr); return; } - status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN - | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S - | 0xc0; - kvm_inject_x86_mce(first_cpu, 9, status, - MCG_STATUS_MCIP | MCG_STATUS_RIPV, paddr, - (MCM_ADDR_PHYS << 6) | 0xc, 1); - for (cenv = first_cpu->next_cpu; cenv != NULL; cenv = cenv->next_cpu) { - kvm_inject_x86_mce(cenv, 1, MCI_STATUS_VAL | MCI_STATUS_UC, - MCG_STATUS_MCIP | MCG_STATUS_RIPV, 0, 0, 1); - } + kvm_mce_inj_srao_broadcast(paddr); } else #endif { @@ -1333,9 +1367,6 @@ static void flush_queued_work(CPUState *env) static void kvm_on_sigbus(CPUState *env, siginfo_t *siginfo) { #if defined(KVM_CAP_MCE) && defined(TARGET_I386) - struct kvm_x86_mce mce = { - .bank = 9, - }; void *vaddr; ram_addr_t ram_addr; unsigned long paddr; @@ -1343,28 +1374,12 @@ static void kvm_on_sigbus(CPUState *env, siginfo_t *siginfo) if ((env->mcg_cap & MCG_SER_P) && siginfo->si_addr && (siginfo->si_code == BUS_MCEERR_AR || siginfo->si_code == BUS_MCEERR_AO)) { - if (siginfo->si_code == BUS_MCEERR_AR) { - /* Fake an Intel architectural Data Load SRAR UCR */ - mce.status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN - | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S - | MCI_STATUS_AR | 0x134; - mce.misc = (MCM_ADDR_PHYS << 6) | 0xc; - mce.mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV; - } else { - /* - * If there is an MCE excpetion being processed, ignore - * this SRAO MCE - */ - if (kvm_mce_in_progress(env)) { - return; - } - /* Fake an Intel architectural Memory scrubbing UCR */ - mce.status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN - | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S - | 0xc0; - mce.misc = (MCM_ADDR_PHYS << 6) | 0xc; - mce.mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV; + /* + * If there is an MCE excpetion being processed, ignore this SRAO MCE + */ + if (siginfo->si_code == BUS_MCEERR_AO && kvm_mce_in_progress(env)) { + return; } vaddr = (void *)siginfo->si_addr; if (do_qemu_ram_addr_from_host(vaddr, &ram_addr) || @@ -1378,8 +1393,13 @@ static void kvm_on_sigbus(CPUState *env, siginfo_t *siginfo) hardware_memory_error(); } } - mce.addr = paddr; - kvm_do_set_mce(env, &mce, 1); + if (siginfo->si_code == BUS_MCEERR_AR) { + /* Fake an Intel architectural Data Load SRAR UCR */ + kvm_mce_inj_srar_dataload(env, paddr); + } else { + /* Fake an Intel architectural Memory scrubbing UCR */ + kvm_mce_inj_srao_memscrub(env, paddr); + } } else #endif { -- 1.7.1.1