From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jin Dongming Subject: [PATCH 05/11] kvm, x86: introduce kvm_inject_x86_mce_on Date: Thu, 14 Oct 2010 17:47:03 +0900 Message-ID: <4CB6C387.9030100@np.css.fujitsu.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-2022-JP Content-Transfer-Encoding: 7bit Cc: Dean Nelson , Marcelo Tosatti , Avi Kivity , Huang Ying , Hidetoshi Seto , "qemu-devel@nongnu.org" To: KVM list Return-path: Received: from fgwmail6.fujitsu.co.jp ([192.51.44.36]:43967 "EHLO fgwmail6.fujitsu.co.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754862Ab0JNIpj (ORCPT ); Thu, 14 Oct 2010 04:45:39 -0400 Received: from m2.gw.fujitsu.co.jp ([10.0.50.72]) by fgwmail6.fujitsu.co.jp (Fujitsu Gateway) with ESMTP id o9E8jcCb021121 for (envelope-from jin.dongming@np.css.fujitsu.com); Thu, 14 Oct 2010 17:45:38 +0900 Received: from smail (m2 [127.0.0.1]) by outgoing.m2.gw.fujitsu.co.jp (Postfix) with ESMTP id 0189A45DE51 for ; Thu, 14 Oct 2010 17:45:38 +0900 (JST) Received: from s2.gw.fujitsu.co.jp (s2.gw.fujitsu.co.jp [10.0.50.92]) by m2.gw.fujitsu.co.jp (Postfix) with ESMTP id 9239545DE4E for ; Thu, 14 Oct 2010 17:45:37 +0900 (JST) Received: from s2.gw.fujitsu.co.jp (localhost.localdomain [127.0.0.1]) by s2.gw.fujitsu.co.jp (Postfix) with ESMTP id 7896F1DB803A for ; Thu, 14 Oct 2010 17:45:37 +0900 (JST) Received: from m000.s.css.fujitsu.com (m000.s.css.fujitsu.com [10.23.4.38]) by s2.gw.fujitsu.co.jp (Postfix) with ESMTP id 31DE91DB8038 for ; Thu, 14 Oct 2010 17:45:37 +0900 (JST) Sender: kvm-owner@vger.kernel.org List-ID: Pass a table instead of multiple args. Note: kvm_inject_x86_mce(env, bank, status, mcg_status, addr, misc, abort_on_error); is equal to: struct kvm_x86_mce mce = { .bank = bank, .status = status, .mcg_status = mcg_status, .addr = addr, .misc = misc, }; kvm_inject_x86_mce_on(env, &mce, abort_on_error); Signed-off-by: Hidetoshi Seto Tested-by: Jin Dongming --- qemu-kvm.c | 56 ++++++++++++++++++++++++++++++++++++++------------------ 1 files changed, 38 insertions(+), 18 deletions(-) diff --git a/qemu-kvm.c b/qemu-kvm.c index 9f248f0..0ba42fc 100644 --- a/qemu-kvm.c +++ b/qemu-kvm.c @@ -1131,6 +1131,9 @@ static void sigbus_reraise(void) } #if defined(KVM_CAP_MCE) && defined(TARGET_I386) +static void kvm_inject_x86_mce_on(CPUState *env, struct kvm_x86_mce *mce, + int abort_on_error); + static int kvm_mce_in_progress(CPUState *env) { struct kvm_msr_entry msr_mcg_status = { @@ -1192,17 +1195,27 @@ static void kvm_mce_inj_srao_memscrub(CPUState *env, unsigned long paddr) static void kvm_mce_inj_srao_broadcast(unsigned long paddr) { + struct kvm_x86_mce mce_srao_memscrub = { + .bank = 9, + .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN + | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S + | 0xc0, + .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV, + .addr = paddr, + .misc = (MCM_ADDR_PHYS << 6) | 0xc, + }; + struct kvm_x86_mce mce_dummy = { + .bank = 1, + .status = MCI_STATUS_VAL | MCI_STATUS_UC, + .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV, + .addr = 0, + .misc = 0, + }; CPUState *cenv; - kvm_inject_x86_mce(first_cpu, 9, - MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN - | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S - | 0xc0, - MCG_STATUS_MCIP | MCG_STATUS_RIPV, paddr, - (MCM_ADDR_PHYS << 6) | 0xc, 1); + kvm_inject_x86_mce_on(first_cpu, &mce_srao_memscrub, 1); for (cenv = first_cpu->next_cpu; cenv != NULL; cenv = cenv->next_cpu) - kvm_inject_x86_mce(cenv, 1, MCI_STATUS_VAL | MCI_STATUS_UC, - MCG_STATUS_MCIP | MCG_STATUS_RIPV, 0, 0, 1); + kvm_inject_x86_mce_on(cenv, &mce_dummy, 1); } #endif @@ -1941,6 +1954,22 @@ static void kvm_do_inject_x86_mce(void *_data) kvm_do_set_mce(data->env, data->mce, data->abort_on_error); } + +static void kvm_inject_x86_mce_on(CPUState *env, struct kvm_x86_mce *mce, + int abort_on_error) +{ + struct kvm_x86_mce_data data = { + .env = env, + .mce = mce, + .abort_on_error = abort_on_error, + }; + + if (!env->mcg_cap) { + perror("MCE support is not enabled!"); + return; + } + on_vcpu(env, kvm_do_inject_x86_mce, &data); +} #endif void kvm_inject_x86_mce(CPUState *cenv, int bank, uint64_t status, @@ -1955,17 +1984,8 @@ void kvm_inject_x86_mce(CPUState *cenv, int bank, uint64_t status, .addr = addr, .misc = misc, }; - struct kvm_x86_mce_data data = { - .env = cenv, - .mce = &mce, - .abort_on_error = abort_on_error, - }; - if (!cenv->mcg_cap) { - fprintf(stderr, "MCE support is not enabled!\n"); - return; - } - on_vcpu(cenv, kvm_do_inject_x86_mce, &data); + kvm_inject_x86_mce_on(cenv, &mce, abort_on_error); #else if (abort_on_error) { abort(); -- 1.7.1.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=38369 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1P6JRW-000887-Up for qemu-devel@nongnu.org; Thu, 14 Oct 2010 04:45:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1P6JRV-0003Dz-P3 for qemu-devel@nongnu.org; Thu, 14 Oct 2010 04:45:42 -0400 Received: from fgwmail5.fujitsu.co.jp ([192.51.44.35]:48582) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1P6JRV-0003DF-8F for qemu-devel@nongnu.org; Thu, 14 Oct 2010 04:45:41 -0400 Received: from m6.gw.fujitsu.co.jp ([10.0.50.76]) by fgwmail5.fujitsu.co.jp (Fujitsu Gateway) with ESMTP id o9E8jcZ8018945 for (envelope-from jin.dongming@np.css.fujitsu.com); Thu, 14 Oct 2010 17:45:38 +0900 Received: from smail (m6 [127.0.0.1]) by outgoing.m6.gw.fujitsu.co.jp (Postfix) with ESMTP id C4B8045DE53 for ; Thu, 14 Oct 2010 17:45:37 +0900 (JST) Received: from s6.gw.fujitsu.co.jp (s6.gw.fujitsu.co.jp [10.0.50.96]) by m6.gw.fujitsu.co.jp (Postfix) with ESMTP id 8D28F45DE4E for ; Thu, 14 Oct 2010 17:45:37 +0900 (JST) Received: from s6.gw.fujitsu.co.jp (localhost.localdomain [127.0.0.1]) by s6.gw.fujitsu.co.jp (Postfix) with ESMTP id 773A8E38007 for ; Thu, 14 Oct 2010 17:45:37 +0900 (JST) Received: from m000.s.css.fujitsu.com (m000.s.css.fujitsu.com [10.23.4.38]) by s6.gw.fujitsu.co.jp (Postfix) with ESMTP id 307D0E38004 for ; Thu, 14 Oct 2010 17:45:37 +0900 (JST) Message-ID: <4CB6C387.9030100@np.css.fujitsu.com> Date: Thu, 14 Oct 2010 17:47:03 +0900 From: Jin Dongming MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-2022-JP Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH 05/11] kvm, x86: introduce kvm_inject_x86_mce_on List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: KVM list Cc: Hidetoshi Seto , Dean Nelson , Marcelo Tosatti , "qemu-devel@nongnu.org" , Avi Kivity , Huang Ying Pass a table instead of multiple args. Note: kvm_inject_x86_mce(env, bank, status, mcg_status, addr, misc, abort_on_error); is equal to: struct kvm_x86_mce mce = { .bank = bank, .status = status, .mcg_status = mcg_status, .addr = addr, .misc = misc, }; kvm_inject_x86_mce_on(env, &mce, abort_on_error); Signed-off-by: Hidetoshi Seto Tested-by: Jin Dongming --- qemu-kvm.c | 56 ++++++++++++++++++++++++++++++++++++++------------------ 1 files changed, 38 insertions(+), 18 deletions(-) diff --git a/qemu-kvm.c b/qemu-kvm.c index 9f248f0..0ba42fc 100644 --- a/qemu-kvm.c +++ b/qemu-kvm.c @@ -1131,6 +1131,9 @@ static void sigbus_reraise(void) } #if defined(KVM_CAP_MCE) && defined(TARGET_I386) +static void kvm_inject_x86_mce_on(CPUState *env, struct kvm_x86_mce *mce, + int abort_on_error); + static int kvm_mce_in_progress(CPUState *env) { struct kvm_msr_entry msr_mcg_status = { @@ -1192,17 +1195,27 @@ static void kvm_mce_inj_srao_memscrub(CPUState *env, unsigned long paddr) static void kvm_mce_inj_srao_broadcast(unsigned long paddr) { + struct kvm_x86_mce mce_srao_memscrub = { + .bank = 9, + .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN + | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S + | 0xc0, + .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV, + .addr = paddr, + .misc = (MCM_ADDR_PHYS << 6) | 0xc, + }; + struct kvm_x86_mce mce_dummy = { + .bank = 1, + .status = MCI_STATUS_VAL | MCI_STATUS_UC, + .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV, + .addr = 0, + .misc = 0, + }; CPUState *cenv; - kvm_inject_x86_mce(first_cpu, 9, - MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN - | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S - | 0xc0, - MCG_STATUS_MCIP | MCG_STATUS_RIPV, paddr, - (MCM_ADDR_PHYS << 6) | 0xc, 1); + kvm_inject_x86_mce_on(first_cpu, &mce_srao_memscrub, 1); for (cenv = first_cpu->next_cpu; cenv != NULL; cenv = cenv->next_cpu) - kvm_inject_x86_mce(cenv, 1, MCI_STATUS_VAL | MCI_STATUS_UC, - MCG_STATUS_MCIP | MCG_STATUS_RIPV, 0, 0, 1); + kvm_inject_x86_mce_on(cenv, &mce_dummy, 1); } #endif @@ -1941,6 +1954,22 @@ static void kvm_do_inject_x86_mce(void *_data) kvm_do_set_mce(data->env, data->mce, data->abort_on_error); } + +static void kvm_inject_x86_mce_on(CPUState *env, struct kvm_x86_mce *mce, + int abort_on_error) +{ + struct kvm_x86_mce_data data = { + .env = env, + .mce = mce, + .abort_on_error = abort_on_error, + }; + + if (!env->mcg_cap) { + perror("MCE support is not enabled!"); + return; + } + on_vcpu(env, kvm_do_inject_x86_mce, &data); +} #endif void kvm_inject_x86_mce(CPUState *cenv, int bank, uint64_t status, @@ -1955,17 +1984,8 @@ void kvm_inject_x86_mce(CPUState *cenv, int bank, uint64_t status, .addr = addr, .misc = misc, }; - struct kvm_x86_mce_data data = { - .env = cenv, - .mce = &mce, - .abort_on_error = abort_on_error, - }; - if (!cenv->mcg_cap) { - fprintf(stderr, "MCE support is not enabled!\n"); - return; - } - on_vcpu(cenv, kvm_do_inject_x86_mce, &data); + kvm_inject_x86_mce_on(cenv, &mce, abort_on_error); #else if (abort_on_error) { abort(); -- 1.7.1.1