From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp.extricom.com (smtp.extricom.com [192.114.46.18]) by ozlabs.org (Postfix) with SMTP id 3935AB70CB for ; Wed, 20 Oct 2010 21:45:24 +1100 (EST) Message-ID: <4CBEC62E.30900@extricom.com> Date: Wed, 20 Oct 2010 12:36:30 +0200 From: Natalie Shapira MIME-Version: 1.0 To: galak@kernel.crashing.org, linuxppc-dev@ozlabs.org, leoli@freescale.com, zw@zh-kernel.org Subject: Freescale P2020/ 85xx PCIe: DMA low throughtput Content-Type: multipart/alternative; boundary="------------030008030101080305010702" List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , This is a multi-part message in MIME format. --------------030008030101080305010702 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Hi, I'm working on bring up for a new board based on Freescales p2020. I have a programmable FPGA as a PCIe device with a buffer I can write to and from. I want to test performence for the PCIe bus. I encountered a problem while doing a DMA between the FPGA & DDR. The whole buffer moves to and from the device with out mismatches but with low throughtput. The thing is that the buffer divided to many transactions of byte size instead of transferring it in a burst. I must mention that even a buffer of word size, divided in to byte transactions by the DMA (the core can read a word so it seems like the DMA fault. I tried to change the latency timer, max latency, min latency and cache line in the configuration space of both sides of the pcie bus. It didn't help. Do you have an idea what can it be? Thanks, Natalie. --------------030008030101080305010702 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Hi,

I'm working on bring up for a new board based on Freescales p2020. I have a programmable FPGA as a PCIe device with a buffer I can write to and from.
I want to test  performence for the PCIe bus.
I encountered a problem while doing a DMA between the FPGA & DDR.
The whole buffer  moves  to and from  the device  with out mismatches but with low throughtput.
The thing is that the buffer divided to many transactions of byte size instead of transferring it in a burst.
I must mention that even a buffer of word size, divided in to byte transactions by the DMA (the core can read a word so it seems like the DMA fault.
I tried to change the latency timer, max latency, min latency and cache line in the configuration space of both sides of the pcie bus. It didn't help.
Do you have an idea what can it be?

Thanks,
Natalie. --------------030008030101080305010702--