From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=34263 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PAWBU-0000EC-LE for qemu-devel@nongnu.org; Mon, 25 Oct 2010 19:10:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PAW7w-0001sg-OB for qemu-devel@nongnu.org; Mon, 25 Oct 2010 19:06:53 -0400 Received: from e1.ny.us.ibm.com ([32.97.182.141]:34576) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PAW7w-0001re-M1 for qemu-devel@nongnu.org; Mon, 25 Oct 2010 19:06:52 -0400 Received: from d01relay05.pok.ibm.com (d01relay05.pok.ibm.com [9.56.227.237]) by e1.ny.us.ibm.com (8.14.4/8.13.1) with ESMTP id o9PMxEex003668 for ; Mon, 25 Oct 2010 18:59:14 -0400 Received: from d01av03.pok.ibm.com (d01av03.pok.ibm.com [9.56.224.217]) by d01relay05.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id o9PN6YtZ168096 for ; Mon, 25 Oct 2010 19:06:34 -0400 Received: from d01av03.pok.ibm.com (loopback [127.0.0.1]) by d01av03.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id o9PN6YQQ011080 for ; Mon, 25 Oct 2010 21:06:34 -0200 Message-ID: <4CC60D7B.7050002@linux.vnet.ibm.com> Date: Mon, 25 Oct 2010 18:06:35 -0500 From: Anthony Liguori MIME-Version: 1.0 Subject: Re: [Qemu-devel] Re: backdoor References: <87vd4q5yqd.fsf_-_@ginnungagap.bsc.es> <4CC5783C.8060009@redhat.com> <87pquy4cn7.fsf@ginnungagap.bsc.es> <4CC5F4AE.6020306@codemonkey.ws> <87iq0prire.fsf@fulla.xlab.taz> In-Reply-To: <87iq0prire.fsf@fulla.xlab.taz> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?B?TGx1w61z?= Cc: Paolo Bonzini , qemu-devel@nongnu.org On 10/25/2010 05:48 PM, Llu=C3=ADs wrote: >> For instance, a CPUID leaf could be used in the 0x40001xxx range. >> =20 > Right, I commented this in a previous mail as a much nicer way to do it= , > but I was just too lazy to look up how CPUID works and instead ported > the implementation I already had in bochs :) > > Although I can port it to CPUID if people find it useful to have > upstream. I just need a way to provide an immediate and a register-base= d > argument (at the same time), which does not require executing more than > a couple of extra instructions (right now everything fits on a single > instruction). > > Being able te receive back information would be a plus, which I think > CPUID already does to return its results; although I think the ISA says > that _all_ registers are "used" after executing it. > =20 I think just the base 6 GP registers. I don't think any of the extended=20 registers in 64-bit mode are affected but I would have to look it up. Regards, Anthony Liguori > Lluis > > =20