From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Hellstrom Subject: Nouveau fences? Date: Sun, 28 Nov 2010 13:39:01 +0100 Message-ID: <4CF24D65.4030008@shipmail.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: Received: from smtp-outbound-1.vmware.com (smtp-outbound-1.vmware.com [65.115.85.69]) by gabe.freedesktop.org (Postfix) with ESMTP id EDAA19E730 for ; Sun, 28 Nov 2010 04:39:21 -0800 (PST) List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org Errors-To: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org To: Ben Skeggs Cc: Ben Skeggs , "dri-devel@lists.freedesktop.org" List-Id: dri-devel@lists.freedesktop.org Ben, I'm looking at a way to make TTM memory management asynchronous with the CPU. The idea is that you should basically be able to DMA data to and from memory regions without waiting for idle, as long as the GPU has a means to provide operation ordering. While doing that I looked a bit at the Nouveau fencing. It appears like waiting for fences is polling only (no irq to signal fences)? Is that correct? /Thomas