From: cyril@ti.com (Cyril Chemparathy)
To: linux-arm-kernel@lists.infradead.org
Subject: Forced HW_BREAKPOINT
Date: Wed, 01 Dec 2010 11:48:18 -0500 [thread overview]
Message-ID: <4CF67C52.4000300@ti.com> (raw)
In-Reply-To: <004d01cb9174$c8d83ec0$5a88bc40$@deacon@arm.com>
Hi Will,
On 12/01/2010 11:28 AM, Will Deacon wrote:
[...]
>> Yes, this CPU has a trustzone capable v6.1 debug (DIDR reads
>> 0x15121004). The problem I am facing is that DSCR bit 15 (monitor
>> debug-mode enable bit) cannot be set, it always reads back 0x2. As a
>> result the hw_breakpoint code spews a WARN_ON() at boot.
>
> That's unfortunate. Is there a hardware debugger connected, or does
> the core disallow monitor debug full-stop?
>
This was without a debugger connected. It is possible that I have
missed some top level debug enable in the SoC (haven't traced through
the entire logic yet).
Regards
Cyril.
next prev parent reply other threads:[~2010-12-01 16:48 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-11-30 23:56 Forced HW_BREAKPOINT Cyril Chemparathy
2010-12-01 9:54 ` Will Deacon
2010-12-01 16:17 ` Cyril Chemparathy
2010-12-01 16:28 ` Will Deacon
2010-12-01 16:48 ` Cyril Chemparathy [this message]
2010-12-01 17:32 ` Will Deacon
2010-12-01 20:14 ` Cyril Chemparathy
2010-12-02 9:37 ` Will Deacon
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