From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andre Przywara Subject: Re: [PATCH 2/2] hvm: allow pass-through of new CPUID features Date: Thu, 27 Jan 2011 13:05:19 +0100 Message-ID: <4D415F7F.3050206@amd.com> References: <4D4029FD.6070702@amd.com> <19776.18018.384751.824459@mariner.uk.xensource.com> Mime-Version: 1.0 Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <19776.18018.384751.824459@mariner.uk.xensource.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Ian Jackson Cc: xen-devel , Keir Fraser List-Id: xen-devel@lists.xenproject.org Ian Jackson wrote: > Andre Przywara writes ("[Xen-devel] [PATCH 2/2] hvm: allow pass-through of new CPUID features"): >> there are some new CPUID features that are safe for guests to see, as >> they don't require OS awareness (FPU/ALU related instructions only). >> Among features for new AMD CPUs there is also the PCLMULQDQ bit, which >> Intel CPU have already for quite a while. > > This would seem to be a new feature. I agree to some point, although (at least in respect to PCLMULQDQ) I'd consider this more as "forgotten enablement". > We are currently in feature freeze. > > Can you make a justification for a freeze exception ? If you can make me believe that it does not take another year until this shows up in an official release, then I am totally fine with skipping 4.1.0. What is the policy regarding the 4.1.x releases? Have features like those a chance of being applied? Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany