From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andre Przywara Subject: Re: [PATCH 2/2] hvm: allow pass-through of new CPUID features Date: Thu, 27 Jan 2011 16:56:39 +0100 Message-ID: <4D4195B7.7090504@amd.com> References: <4D4029FD.6070702@amd.com> <19776.18018.384751.824459@mariner.uk.xensource.com> <4D415F7F.3050206@amd.com> <19777.34552.594880.846926@mariner.uk.xensource.com> <4D419294.6010806@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <4D419294.6010806@amd.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Ian Jackson Cc: xen-devel , Keir Fraser , Stefano Stabellini List-Id: xen-devel@lists.xenproject.org Andre Przywara wrote: > Ian Jackson wrote: >> Stefano Stabellini writes ("Re: [Xen-devel] [PATCH 2/2] hvm: allow pass-through of new CPUID features"): >>> I think Ian was just looking for a well written explanation of why we >>> need this now :) > OK, I feel challenged, what about this: > > The new CPU features are pure "compute" features (ALU/FPU only), they > don't need any support or awareness from any system level software. > Following the definition of virtualization they should be available to > guests unless explicitly disabled. > The AES feature was introduced at the same time as the PCLMULQDQ > feature, AES is passed through, PCLMULQDQ has obviously been forgotten(?). > The Linux kernel uses both instructions in newer versions for optimized > cryptographic algorithms implementation > (arch/x86/crypto/ghash-clmulni-intel_asm.S) > The current version of the Xen hypervisor would deny this feature to any > PV domains, including Dom0, leaving systems running under Xen with an > inferior cryptographic performance. > This patch allows PV domains to use the feature to get on par with > systems running with other virtualization software. Seems like I was a bit to eager with my rationale, this patch of course affects only HVM guests. Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany