Re: [Qemu-devel] [PATCH] SPARC: Fix Leon3 cache control

[Fabien Chouteau <chouteau@adacore.com>]

On 01/27/2011 11:40 AM, Fabien Chouteau wrote:
> The "leon3_cache_control_int" (op_helper.c) function is called within leon3.c
> which leads to segfault error with the global "env".
>
> Now cache control is a CPU feature and everything is handled in op_helper.c.
>
> Signed-off-by: Fabien Chouteau<chouteau@adacore.com>
> ---
>   hw/leon3.c               |    1 -
>   target-sparc/cpu.h       |    4 ++--
>   target-sparc/helper.c    |    2 +-
>   target-sparc/op_helper.c |   23 +++++++++++++++++------
>   4 files changed, 20 insertions(+), 10 deletions(-)
>
> diff --git a/hw/leon3.c b/hw/leon3.c
> index 69d8f3b..aaf26fd 100644
> --- a/hw/leon3.c
> +++ b/hw/leon3.c
> @@ -59,7 +59,6 @@ static void main_cpu_reset(void *opaque)
>   static void leon3_irq_ack(void *irq_manager, int intno)
>   {
>       grlib_irqmp_ack((DeviceState *)irq_manager, intno);
> -    leon3_cache_control_int();
>   }
>
>   static void leon3_set_pil_in(void *opaque, uint32_t pil_in)
> diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
> index 6f5990b..8141b32 100644
> --- a/target-sparc/cpu.h
> +++ b/target-sparc/cpu.h
> @@ -268,6 +268,8 @@ typedef struct sparc_def_t {
>   #define CPU_FEATURE_GL           (1<<  13)
>   #define CPU_FEATURE_TA0_SHUTDOWN (1<<  14) /* Shutdown on "ta 0x0" */
>   #define CPU_FEATURE_ASR17        (1<<  15)
> +#define CPU_FEATURE_CACHE_CTRL   (1<<  16)
> +
>   #ifndef TARGET_SPARC64
>   #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
>                                 CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
> @@ -477,8 +479,6 @@ int cpu_cwp_inc(CPUState *env1, int cwp);
>   int cpu_cwp_dec(CPUState *env1, int cwp);
>   void cpu_set_cwp(CPUState *env1, int new_cwp);
>
> -void leon3_cache_control_int(void);
> -
>   /* sun4m.c, sun4u.c */
>   void cpu_check_irqs(CPUSPARCState *env);
>
> diff --git a/target-sparc/helper.c b/target-sparc/helper.c
> index 2f3d1e6..b2d4d70 100644
> --- a/target-sparc/helper.c
> +++ b/target-sparc/helper.c
> @@ -1289,7 +1289,7 @@ static const sparc_def_t sparc_defs[] = {
>           .mmu_trcr_mask = 0xffffffff,
>           .nwindows = 8,
>           .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN |
> -        CPU_FEATURE_ASR17,
> +        CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL,
>       },
>   #endif
>   };
> diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
> index d3e1b63..698c159 100644
> --- a/target-sparc/op_helper.c
> +++ b/target-sparc/op_helper.c
> @@ -1653,7 +1653,7 @@ static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
>
>   /* Leon3 cache control */
>
> -void leon3_cache_control_int(void)
> +static void leon3_cache_control_int(void)
>   {
>       uint32_t state = 0;
>
> @@ -1741,7 +1741,7 @@ static uint64_t leon3_cache_control_ld(target_ulong addr, int size)
>           DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
>           break;
>       };
> -    DPRINTF_CACHE_CONTROL("st addr:%08x, ret:%" PRIx64 ", size:%d\n",
> +    DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n",
>                             addr, ret, size);
>       return ret;
>   }
> @@ -1760,7 +1760,9 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
>           case 0x00:          /* Leon3 Cache Control */
>           case 0x08:          /* Leon3 Instruction Cache config */
>           case 0x0C:          /* Leon3 Date Cache config */
> -            ret = leon3_cache_control_ld(addr, size);
> +            if (env->def->features&  CPU_FEATURE_CACHE_CTRL) {
> +                ret = leon3_cache_control_ld(addr, size);
> +            }
>               break;
>           case 0x01c00a00: /* MXCC control register */
>               if (size == 8)
> @@ -1994,7 +1996,9 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
>           case 0x00:          /* Leon3 Cache Control */
>           case 0x08:          /* Leon3 Instruction Cache config */
>           case 0x0C:          /* Leon3 Date Cache config */
> -            leon3_cache_control_st(addr, val, size);
> +            if (env->def->features&  CPU_FEATURE_CACHE_CTRL) {
> +                leon3_cache_control_st(addr, val, size);
> +            }
>               break;
>
>           case 0x01c00000: /* MXCC stream data register 0 */
> @@ -4325,9 +4329,16 @@ void do_interrupt(CPUState *env)
>
>   #if !defined(CONFIG_USER_ONLY)
>       /* IRQ acknowledgment */
> -    if ((intno&  ~15) == TT_EXTINT&&  env->qemu_irq_ack != NULL) {
> -        env->qemu_irq_ack(env->irq_manager, intno);
> +    if ((intno&  ~15) == TT_EXTINT) {
> +        if (env->qemu_irq_ack != NULL) {
> +            env->qemu_irq_ack(env->irq_manager, intno);
> +        }
> +
> +        if (env->def->features&  CPU_FEATURE_CACHE_CTRL) {
> +            leon3_cache_control_int();
> +        }
>       }
> +
>   #endif
>   }
>   #endif

Any comment?

-- 
Fabien Chouteau