From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: clock bindings Date: Wed, 02 Feb 2011 10:47:40 -0600 Message-ID: <4D498AAC.3090009@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: devicetree-discuss-bounces+gldd-devicetree-discuss=m.gmane.org-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org Errors-To: devicetree-discuss-bounces+gldd-devicetree-discuss=m.gmane.org-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org To: devicetree-discuss List-Id: devicetree@vger.kernel.org I've started looking at the DT clock bindings in more depth. To what level should the clock tree be defined in the DT? Should it be a one-to-one correlation of current struct clk nodes to node in DT where each node is a single input and output? Or only define a single (or few) node with the inputs (oscillators) and many outputs for SOC's clock controller (i.e. MX51 CCM). If the DT itself does not have a hierarchical construction of nodes that matches the clock tree hierarchy, then creating the hierarchy at run-time will be a challenge and not be very efficient. It would require 1 pass for each clock node type to create all the nodes, and then another pass to setup the hierarchy. Rob