From: Cyrill Gorcunov <gorcunov@gmail.com>
To: Stephane Eranian <eranian@google.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
linux-kernel@vger.kernel.org, mingo@elte.hu, paulus@samba.org,
davem@davemloft.net, fweisbec@gmail.com,
perfmon2-devel@lists.sf.net, eranian@gmail.com,
robert.richter@amd.com, acme@redhat.com, ming.m.lin@intel.com
Subject: Re: [PATCH 0/2] perf_events: add support for Intel fixed counter 2
Date: Sun, 06 Feb 2011 22:55:45 +0300 [thread overview]
Message-ID: <4D4EFCC1.2080607@gmail.com> (raw)
In-Reply-To: <AANLkTimOxf_GZtWwn3fEojKLjeVpQSiAwOn7=vBmiWRz@mail.gmail.com>
On 02/05/2011 06:19 PM, Stephane Eranian wrote:
> Hi,
>
> Ok, another, easier, choice would be to use event code 0 (and
> umaks 0x1 for instance). I doubt that one will ever be used.
>
>
Seems so, but there is no guarantee I think (at least for p4 there is
0x0 event (tc-deliver-mode)) though 0x1 should make it unique enough.
--
Cyrill
prev parent reply other threads:[~2011-02-06 19:55 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-02-04 12:00 [PATCH 0/2] perf_events: add support for Intel fixed counter 2 Stephane Eranian
2011-02-04 13:12 ` Peter Zijlstra
2011-02-04 13:19 ` Stephane Eranian
2011-02-05 15:19 ` Stephane Eranian
2011-02-06 19:55 ` Cyrill Gorcunov [this message]
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