Re: [Qemu-devel] [PATCH 02/17] lm32: translation routines

[Richard Henderson <rth@twiddle.net>]

On 01/30/2011 04:30 PM, Michael Walle wrote:
> +    if (dc->format == OP_FMT_RI) {
> +        tcg_gen_brcondi_tl(cond, cpu_R[rY], sign_extend(dc->imm16, 16), l1);
> +    } else {
> +        tcg_gen_brcond_tl(cond, cpu_R[rY], cpu_R[rZ], l1);
> +    }
> +    tcg_gen_movi_tl(cpu_R[rX], 0);
> +    tcg_gen_br(l2);
> +    gen_set_label(l1);
> +    tcg_gen_movi_tl(cpu_R[rX], 1);
> +    gen_set_label(l2);

This is tcg_gen_setcond_tl.

BTW, why the extensive extra LOG_DIS code?  Why not just run the regular 
disassembler, like other ports?

> +    if (!(dc->env->features & LM32_FEATURE_MULTIPLY)) {
> +        cpu_abort(dc->env, "hardware multiplier is not available\n");
> +    }

Aborting the VM, rather than raising an exception?

> +        tcg_gen_xor_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
> +        tcg_gen_not_tl(cpu_R[dc->r2], cpu_R[dc->r2]);

This is tcg_gen_eqv_tl.

> +    /* Large switch for all insns.  */
> +    for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
> +        if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
> +            decinfo[i].dec(dc);
> +            break;
> +        }
> +    }
> +}

No check that *some* opcode matched?  It would seem like a "return"
here instead of a break, and then an illegal opcode exception after
the loop would be in order.



r~