From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=38487 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PmrWt-0005Lt-Sk for qemu-devel@nongnu.org; Tue, 08 Feb 2011 12:39:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PmrWs-0003AF-8A for qemu-devel@nongnu.org; Tue, 08 Feb 2011 12:39:07 -0500 Received: from eu1sys200aog116.obsmtp.com ([207.126.144.141]:57767) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PmrWr-0003A4-V3 for qemu-devel@nongnu.org; Tue, 08 Feb 2011 12:39:06 -0500 Received: from zeta.dmz-eu.st.com (ns2.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 7D4C5E7 for ; Tue, 8 Feb 2011 17:39:03 +0000 (GMT) Received: from Webmail-eu.st.com (safex1hubcas5.st.com [10.75.90.71]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 25C822CF6 for ; Tue, 8 Feb 2011 17:39:03 +0000 (GMT) Message-ID: <4D517FB6.3070106@st.com> Date: Tue, 8 Feb 2011 18:39:02 +0100 From: Christophe Lyon MIME-Version: 1.0 Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH v2] target-arm: implement vsli.64, vsri.64 List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "qemu-devel@nongnu.org" Signed-off-by: Christophe Lyon --- Submitted as a standalone patch as suggested by Peter, along with his corrections. target-arm/translate.c | 14 +++++++++++++- 1 files changed, 13 insertions(+), 1 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index e4649e6..b694eed 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -4688,7 +4688,19 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1); } else if (op == 4 || (op == 5 && u)) { /* Insert */ - cpu_abort(env, "VS[LR]I.64 not implemented"); + neon_load_reg64(cpu_V1, rd + pass); + uint64_t mask; + if (shift < -63 || shift > 63) { + mask = 0; + } else { + if (op == 4) { + mask = 0xffffffffffffffffull >> -shift; + } else { + mask = 0xffffffffffffffffull << shift; + } + } + tcg_gen_andi_i64(cpu_V1, cpu_V1, ~mask); + tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1); } neon_store_reg64(cpu_V0, rd + pass); } else { /* size < 3 */ -- 1.7.2.3