From mboxrd@z Thu Jan 1 00:00:00 1970 From: Wei Huang Subject: [PATCH 2/5][RFC] lwp: adding support for AMD lightweight profiling Date: Fri, 11 Feb 2011 10:28:43 -0600 Message-ID: <4D5563BB.6020304@amd.com> Reply-To: Wei.Huang2@amd.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="------------040605040900030306030308" Return-path: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: "'xen-devel@lists.xensource.com'" , Keir Fraser , "Wei, Gang" List-Id: xen-devel@lists.xenproject.org --------------040605040900030306030308 Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit Add a new field for xsave/xrstor functions to specify the features. Current implementation set EAX:EDX to all 1's. To be prepared for LWP, we add a parameter in xsave/xrstor functions to be set in EAX:EDX. Some of the idea was borrowed from Hans Rosenfeld's Linux kernel patch. Signed-off-by: Wei Huang --------------040605040900030306030308 Content-Type: text/plain; name="lwp_patch_2.txt" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="lwp_patch_2.txt" Content-Description: lwp_patch_2.txt exporting patch: # HG changeset patch # User Wei Huang # Date 1297376221 21600 # Node ID 20d10f3a6d4c6b7357da0cf35a9fe28100cb582d # Parent b57ee5edd2924179b21fa19d35b0e2754c4caeff Add a new field for xsave/xrstor functions to specify the features. Current implementation set EAX:EDX to all 1's. To be prepared for LWP, we add a parameter in xsave/xrstor functions to be set in EAX:EDX. diff -r b57ee5edd292 -r 20d10f3a6d4c xen/arch/x86/i387.c --- a/xen/arch/x86/i387.c Thu Feb 10 16:00:34 2011 -0600 +++ b/xen/arch/x86/i387.c Thu Feb 10 16:17:01 2011 -0600 @@ -18,36 +18,42 @@ static bool_t __read_mostly cpu_has_xsaveopt; -static void xsave(struct vcpu *v) +static void xsave(struct vcpu *v, uint64_t mask) { struct xsave_struct *ptr = v->arch.xsave_area; + uint32_t hmask = mask >> 32; + uint32_t lmask = mask; asm volatile ( ".byte " REX_PREFIX "0x0f,0xae,0x27" : - : "a" (-1), "d" (-1), "D"(ptr) + : "a" (lmask), "d" (hmask), "D"(ptr) : "memory" ); } -static void xsaveopt(struct vcpu *v) +static void xsaveopt(struct vcpu *v, uint64_t mask) { struct xsave_struct *ptr = v->arch.xsave_area; + uint32_t hmask = mask >> 32; + uint32_t lmask = mask; asm volatile ( ".byte " REX_PREFIX "0x0f,0xae,0x37" : - : "a" (-1), "d" (-1), "D"(ptr) + : "a" (lmask), "d" (hmask), "D"(ptr) : "memory" ); } -static void xrstor(struct vcpu *v) +static void xrstor(struct vcpu *v, uint64_t mask) { struct xsave_struct *ptr = v->arch.xsave_area; + uint32_t hmask = mask >> 32; + uint32_t lmask = mask; asm volatile ( ".byte " REX_PREFIX "0x0f,0xae,0x2f" : - : "m" (*ptr), "a" (-1), "d" (-1), "D"(ptr) ); + : "m" (*ptr), "a" (lmask), "d" (hmask), "D"(ptr) ); } static void load_mxcsr(unsigned long val) @@ -76,7 +82,7 @@ * we set all supported feature mask before doing save/restore. */ set_xcr0(v->arch.xcr0_accum); - xrstor(v); + xrstor(v, XCNTXT_DEFAULT); set_xcr0(v->arch.xcr0); } else if ( v->fpu_initialised ) @@ -123,9 +129,9 @@ */ set_xcr0(v->arch.xcr0_accum); if ( cpu_has_xsaveopt ) - xsaveopt(v); + xsaveopt(v, XCNTXT_DEFAULT); else - xsave(v); + xsave(v, XCNTXT_DEFAULT); set_xcr0(v->arch.xcr0); } else if ( cpu_has_fxsr ) diff -r b57ee5edd292 -r 20d10f3a6d4c xen/include/asm-x86/i387.h --- a/xen/include/asm-x86/i387.h Thu Feb 10 16:00:34 2011 -0600 +++ b/xen/include/asm-x86/i387.h Thu Feb 10 16:17:01 2011 -0600 @@ -32,6 +32,9 @@ #define XSTATE_YMM_SIZE 256 #define XSAVEOPT (1 << 0) +/* The features that the OS saves/restores by default. */ +#define XCNTXT_DEFAULT (-1) + struct xsave_struct { struct { char x[512]; } fpu_sse; /* FPU/MMX, SSE */ --------------040605040900030306030308 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel --------------040605040900030306030308--