From: Timur Tabi <timur@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [u-boot-release] [PATCH 1/2] powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers
Date: Wed, 2 Mar 2011 13:58:07 -0600 [thread overview]
Message-ID: <4D6EA14F.8040009@freescale.com> (raw)
In-Reply-To: <1299095564.9847.18.camel@oslab-l1>
York Sun wrote:
> On Wed, 2011-03-02 at 13:46 -0600, Timur Tabi wrote:
>> York Sun wrote:
>>>>> if (wrrec_mclk & 1)
>>>>> wrrec_mclk++;
>>>>>
>>> Only 9, 11, 13, 15 need to round up.
>>
>> What are all the possible values for wrrec_mclk?
>>
>
> There is no limitation on register timing_cfg_1[wrrec_mclk]. It can be
> any value. The limitation comes from JEDEC spec on mode register MR0.
> The write recovery for autoprecharge is within the values of 5, 6, 7, 8,
> 10, 12, 14, 16.
My point is that we can do something like this:
if (wrrec_mclk > 8 && wrrec_mclk < 16 && wrrec_mclk & 1)
wrrec_mclk++;
But we can simplify this if I can know what all possible values are.
--
Timur Tabi
Linux kernel developer@Freescale
prev parent reply other threads:[~2011-03-02 19:58 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-03-02 18:50 [U-Boot] [PATCH 1/2] powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers York Sun
2011-03-02 18:50 ` [U-Boot] [PATCH 2/2] powerpc/corenet_ds: revise platform dependent parameters York Sun
2011-03-02 19:31 ` [U-Boot] [u-boot-release] [PATCH 1/2] powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers Timur Tabi
2011-03-02 19:39 ` York Sun
2011-03-02 19:46 ` Timur Tabi
2011-03-02 19:52 ` York Sun
2011-03-02 19:58 ` Timur Tabi [this message]
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