Re: [PATCH v1 0/3] OMAP: DSS2: Fix for DISPC core functional clock divider

[Raghuveer Murthy <x0075817@ti.com>]

On Thursday 03 March 2011 06:46 PM, Valkeinen, Tomi wrote:
> On Thu, 2011-03-03 at 15:25 +0530, Raghuveer Murthy wrote:
>> OMAP4 has 2 LCD channels and corresponding DISPC_DIVISOR1 and DISPC_DIVISOR2
>> registers to configure the pixel clock frequency, for the respective LCD
>> displays.
>>
>> There is also DISPC_DIVISOR register, which by default has the ENABLE bit
>> set to zero, for backward compatibility mode. Hence the logical clock divider of
>> DISPC_DIVISOR1.LCD, gets used for core func clk configuration. The default value
>> of DISPC_DIVISOR1.LCD is 4.
>>
>> If only the secondary LCD is enabled, at high pixel resolutions the core clk
>> lags behind the pixel clock, causing stair-step effect (diagonal lines with
>> tearing) on the display.
>>
>> Hence DISPC_DIVISOR.ENABLE is set to 1, and the core functional clock is set
>> independently and exclusively in DISPC_DIVISOR.LCD.
>
> I think this patch set is ok. However, it doesn't apply with the latest
> master branch from DSS tree, some quite trivial conflicts with dss
> features. Can you rebase and post it?
>
> Also, please send patches to my ti.com address, not iki.fi address.
>
>   Tomi
>
>
Hi Tomi,

Resent the after re-basing.

Regards,
Raghuveer