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From: David Daney <david.s.daney@gmail.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Ralf Baechle <ralf@linux-mips.org>,
	David Daney <ddaney@caviumnetworks.com>,
	linux-mips@linux-mips.org
Subject: Re: [patch 3/5] MIPS: Octeon: Simplify irq_cpu_on/offline irq chip functions
Date: Sun, 27 Mar 2011 17:12:23 -0700	[thread overview]
Message-ID: <4D8FD267.9040304@gmail.com> (raw)
In-Reply-To: <alpine.LFD.2.00.1103272337260.31464@localhost6.localdomain6>

On 03/27/2011 02:41 PM, Thomas Gleixner wrote:
> On Sun, 27 Mar 2011, Thomas Gleixner wrote:
>> On Sun, 27 Mar 2011, David Daney wrote:
>>
>>> On 03/27/2011 09:22 AM, Thomas Gleixner wrote:
>>>> Make use of the IRQCHIP_ONOFFLINE_ENABLED flag and remove the
>>>> wrappers. Use irqd_irq_disabled() instead of desc->status, which will
>>>> go away.
>>>>
>>> I rewrote my patch set and was testing it.  Interesting that I came up with a
>>> function with almost the same name and purpose.
>>>
>>> However my function told us if the irq was masked *or* disabled.  The idea
>>> being a function that returns true if the irq could fire.  We cannot be
>>> enabling the interrupt in the controller if it is masked.
>>>
>>> For example I need to test this when adjusting affinity, and taking CPUs on
>>> and off line.
>>>
>>> I don't think your genirq changes can tell the me information I really need in
>>> their current state.  I think we need to consider how the masked state
>>> interacts with IRQCHIP_ONOFFLINE_ENABLED and irqd_irq_disabled().
> So you want to know whether the core code masked the interrupt or
> not. In your case that's equivivalent to the irqd_irq_disabled check
> simply because you provide a irq_disable() callback which prevents the
> lazy disable mechanism.

      CPU1                                                 CPU2
handle_edge_irq()
    handle_irq_event()
       .
       .
       .
       enable_interrupts
       .
       handle_edge_irq()
           mask

                                                             set_affinity()
                                                                 enable 
the irq on some CPU1.


          interrupt fires again (incorrectly)






In my set affinity code I want to know if it is masked, so I don't 
inadvertently re-enable it.

David Daney

  reply	other threads:[~2011-03-28  0:12 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-03-27 16:22 [patch 0/5] MIPS: Final irq fixups Thomas Gleixner
2011-03-27 16:22 ` [patch 1/5] MIPS: Fix syncfs syscall copy and paste failure Thomas Gleixner
2011-03-28 11:55   ` Ralf Baechle
2011-03-27 16:22 ` [patch 2/5] MIPS: Octeon: Rewrite interrupt handling code Thomas Gleixner
2011-03-27 16:22 ` [patch 3/5] MIPS: Octeon: Simplify irq_cpu_on/offline irq chip functions Thomas Gleixner
2011-03-27 21:12   ` David Daney
2011-03-27 21:29     ` Thomas Gleixner
2011-03-27 21:41       ` Thomas Gleixner
2011-03-28  0:12         ` David Daney [this message]
2011-03-28  0:24       ` David Daney
2011-03-27 16:22 ` [patch 4/5] MIPS: alchemy: Use proper irq accessors Thomas Gleixner
2011-03-28 12:00   ` Ralf Baechle
2011-03-27 16:22 ` [patch 5/5] MIPS: Convert the irq functions to the new names Thomas Gleixner
2011-03-28 12:01   ` Ralf Baechle

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